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TECHNICAL ARTICLE CLK H D Figure 5: D_TYPE EDGE TRIGGERED CIRCUIT drive the output from LOW to HIGH. Moments later, the NOT gate output changes state and the AND gate reacts to the new stimulus. However, the chain reaction is still in place and what we see at the output or the AND gate is a HIGH equal to the time it took the NOT gate to switch. This may look great, but it’s not a defined period of time—other gates may not even react quickly enough to it and we are relying on the analog side effects of the gates. So what we need is a nice stable version of the glitch generator. We could, for example, have a much higher speed clock running somewhere that could help us process the signals, but then that would need higher speed clocks too… The answer, however, is in our original SR flip-flops. These react to the change of input only once when the input change is applied. With both inputs at LOW, a HIGH signal on one of the inputs generates a fast reaction and latches in a new output if one is required. The interesting effect is the DO NOTHING condition where setting both inputs HIGH will not change the output. Changing an input as LOW will then either Set or Reset the SR latch. However, driving the signal up and down as much as we want will not affect the output. If we were to connect a clock input to this circuit, then Setting or Resetting the latch would happen only on the falling edge of the clock. We are now getting close, but still not quite there. We have a circuit that responds to the edge of the clock—the wrong edge—but we can only connect this circuit so that it Sets or Resets. We need both. Q H In order to have both, you need two SR flip-flops that act as Set and Reset circuits. By connecting these circuits in opposite modes, it’s then possible to use the data input to decide which one latches and holds and which one flips back and forth with the clock input (Figure 5). First thing to notice is that the NOT gate that was used on the SR to turn it into a D-Type is simplified by using the NOT Q output on one of the SR flip-flops (in this case the bottom one). This lower flip-flop generates this NOT signal as a feedback or input to the top flip-flop, which in turn generates a NOT signal back to the first. This causes the two SR flip-flops to latch in opposite modes. The clock signal is also fed to both SR flip-flops and because of this the lower flip-flop need to have a three input NAND gate. The overall effect is that these two flipflops generate a very useful signal. One will, as I said, latch and the other flip with the clock input. These two signals can then be used to drive a third SR flip-flop that functions as before with the DO NOTHING condition, only changing its output once the D-signal has changed and when the clock edge is seen, in this case, on the rising edge. It’s quite a difficult circuit to put into words because of the number of states it can be in. I could post lots of pictures showing them, but nothing works better than an animation. If you have not seen this website before, then http://www.falstad.com is great and has a really nice little circuit simulator. Follow the link below to load the simulator and the following instruction to bring up the edge-triggered D-type flip-flop. From the menus click here, select “Circuits,” then “Sequential Logic.” Then click on “Flip-Flops” and then “Edge-Triggered D Flip-Flop.” About the Author Digital Electronics Engineer with strong software skills in assembly and C for embedded systems. At ebmpapst I’m developing embedded electronics for thermal management control solutions for the air movement industry. These controllers monitor environmental inputs like Temperature, Humidity and Pressure and then control the speed of our fans based on various profiles. Our controls also interface with other systems over RS232/485 or TCP/IP as well as a host of other user or control interfaces. ■ EEWeb | Electrical Engineering Community Visit www.eeweb.com 14 TECHNICAL ARTICLE
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