1 Code Generation Code generator phase ... - VTU e-Learning

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for i =1 to n do C[i, j] = 0; Three address code generated will be as follows 1) i = 0 2) if i < n go to 4 3) go to 15 4) j = 1 5) if j < n go to 7 6) go to 13 7) t1 = i * 10 8) t2 = t1 + j 9) t3 = 4 * t2 10) C[t3] = 0 11) j = j + 1 12) go to 5 13) i = i + 1 14) go to 2 15) Basic blocks will be as follows Stmt no Header Three address code Block no 1 H i = 0 B1 2 H if i < n go to 4 B2 3 H go to 15 B3 4 H j = 1 B4 5 H if j < n go to 7 B5 14
6 H go to 13 B6 7 8 9 10 11 12 13 14 15 H t1 = i * 10 t2 = t1 + j t3 = 4 * t2 C[t3] = 0 j = j + 1 go to 5 H i = i + 1 go to L6 Flow graph for the basic blocks is as follows in Fig 9.1 B6 B8 Directed Acyclic Graph B4 B5 B7 B1 B2 B3 B7 B8 Fig 9.1 Flow graph for the basic blocks 15
Page 1 and 2: Code Generation Code generator phas
Page 3 and 4: d. Index addressing mode- this is o
Page 5 and 6: 1. Call. 2. Return 3. end 4. action
Page 7 and 8: * code for b */ action 3 return /*
Page 9 and 10: Code Optimization has to mainly ach
Page 11 and 12: In order to generate more optimized
Page 13: Each instruction takes some machine
Page 17 and 18: Fig 9.4 DAG for the three address c
Page 19: After topological sorting t2 = b -

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