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Digital Control

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►Need to calculate the<br />

next edge position for<br />

rising and falling edges<br />

within very short period.<br />

►Software not fast<br />

enough so need<br />

hardware adder<br />

►Diagram shows 21 bit<br />

adder to control both<br />

edges automatically<br />

setting new comparator<br />

values after each edge<br />

has been triggered<br />

Ideal timing<br />

16 bits<br />

at IP Bus<br />

timing<br />

resolution<br />

5 bits<br />

NanoEdge<br />

timing<br />

resolution<br />

<strong>Digital</strong> Adder for Frequency <strong>Control</strong><br />

16 bit + 5 bit<br />

adder<br />

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,<br />

Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink<br />

and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 59<br />

Actual timing Timer<br />

16 bits<br />

at IP Bus<br />

timing<br />

resolution<br />

5 bits<br />

NanoEdge<br />

timing<br />

resolution<br />

16 bits<br />

at IP Bus<br />

timing<br />

resolution<br />

5 bits<br />

NanoEdge<br />

timing<br />

resolution<br />

resolution resolution resolution<br />

PWM<br />

Period N<br />

PWM Period N-1<br />

5 bits from previous Nano Edge<br />

Placement calculation<br />

PWM<br />

Period N<br />

PWM reload times are restricted to 16-bit IP Bus timing<br />

(truncation of 21 bit value). Any residual left over from<br />

PWM period N-1 needs to be added back to period N.<br />

TM

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