Embedded Wafer-Level-Packages - I-Micronews

Magazine on 3D-IC, TSV, WLP & Embedded Technologies 

ISSUE n°15 JUNE 2010 

e d i t o r i a l ANALYSIS 

Driving 

collaboration: 

connecting 

with 

customers 

I wanted to take this opportunity to introduce 

myself. I am excited to be a part of the 

Yole Développement team with the primary 

responsibility to build the Micronews Media 

side of our company. 

My engineering back ground combined 

with over 15 years of marketing/publishing 

experience complement the challenges we 

all face, to bring new products and ideas to 

our community. ... 

To be continued on page 2 

3D integration spurs momentum in embedded and 

fan-out wafer-level package technologies 

Both technologies are on the verge of moving to high-volume production, 

so how do they “stack up,” and can we expect to see them in direct competition 

in the future? 

Fan-out wafer-level package (FOWLP) 

technology has attracted plenty of attention 

the past few years, while embedded waferlevel 

package technology has essentially flown 

under the radar. 

Why is embedding active and passive components 

into PCB laminates being pursued so aggressively 

right now? The general consensus is that these 

components offer an advantage in terms of overall 

thickness, as well as improvements in electrical 

and thermal performance, an increase in density, 

cost reductions, and a simplification of logistics. 

The interest in embedding active and passive 

components is being driven by the push to greater 

3D integration, while at the same time trying to 

leverage the existing infrastructure as effectively 

as possible, points out Ted Tessier, CEO 

of Flip Chip International (Phoenix, Ariz.). ... 

2 

Infineon eWLB 300mm reconfigured wafer 

(Source : STATS ChipPAC) 

COMPANY vision 

3-D TSV processes redefine the ‘back-end’ 

Companies once considered solidly ‘front-end’ are busy working in the ‘back-end’ of the bus these days on TSV metallization 

for 3-D integration. 

Engineers at Novellus (San Jose, Calif.) 

recently developed a hollow cathode 

magnetron (HCM)-based advanced copper 

barrier-seed process for through-silicon via (TSV) 

packaging applications to address some of the 

technical issues and high manufacturing costs 

associated with conventional approaches. 

Their process is designed to produce highly 

conformal copper seed films that are much thinner 

than conventional seed approaches used for TSV 

applications, while also delivering excellent sidewall 

and bottom coverage and enabling a void-free 

copper fill during the subsequent TSV electroplating 

step. 

Shifting to 3-D 

The shift to TSVs is primarily to enable 3-D 

packaging, in which multiple chips can be stacked 

into a single module. These stacked chips are then 

connected with short TSV copper interconnects 

to increase device speed and reduce power 

consumption. 

The resulting 3-D TSV packaging offers the benefits 

of increased functionality in a much smaller footprint 

for mobile electronics applications. ... 

9 

Printed on recycled paper 

COMPANY vision 

Bosch’s BMA220 three-axis accelerometer is a leap 

forward in innovation 

Bosch is battling for top spot as a technical and market leader in inertial 

sensors with their launch of the BMA220 2mm x 2mm, three-axis accelerometer. 

According to recent data from Yole Développement, Bosch has moved into 3rd 

spot in the MEMS market. 

C O N T E N T S 

ANALYSIS 2 

COMPANY vision 7 

INTERVIEW 12 

In the past Bosch’s primary focus has been 

the automotive market, but they have been 

aggressively pursuing the consumer electronics 

(CE) market through their Bosch Sensortec 

subsidiary. They launched their, digital SMB380 

three-axis accelerometer in January of 

2007. ... 

7 

ANALYST CORNER 14 

Free registration on 

www.i-micronews.com

JUNE 2010 issue n°15 

Newsletter on 3D IC, TSV, WLP & Embedded Technologies 

E D I T O R I A L 

Micronews Media has been producing and 

will continue to produce valuable information 

(content) to the wafer microelectronic 

manufacturing market place. In fact, it’s one 

of the only sources analyzing and reporting 

all of technologies together under one wafer! 

For example, in this issue Jérôme Baron 

has in depth analysis of FOWLP conducting 

exclusive high level interviews while at the 

same time providing a road map to where 

it is all heading! New subscribers join our 

community every day, and almost all of you 

say you want to stay informed on usually 

more than 3 technologies. To help you stay 

current and ahead of your competition, we 

deliver magazines 30 times a year packed 

full of analysis and information plus our 

website has exclusive content every day. You 

should also feel confident that your peers, 

our subscribers, are the key decision makers 

from this industry including executives, 

engineers, marketers, biz development, 

R&D department and more, representing the 

drivers of this fast moving marketplace. 

a n a l y s i s 

3D integration spurs momentum in 

embedded and fan-out wafer-level 

package technologies 

From page 1 

“From a reliability standpoint, embedded die 

components show absolutely outstanding 

mechanical robustness — even in drop tests. 

Embedding active devices into PCBs provides an 

alternative to wafer-level fan-out WLSCP or BGA 

applications,” he says. 

“Electrical performance is the primary driver and 

benefit,” says Lee Smith, vice president of product 

marketing at Amkor Technology (Chandler, Ariz.). 

“Form factor is another driver, but typically it’s 

applications such as DDR4, where the electrical 

limitations of wirebond window BGAs may be 

reaching their practical limits.” 

How will the technology start out? “First, simple 

small dies with low pin-count will be embedded in 

motherboards, such as integrated passive dies, in 

mobile applications,” explains Caroline Beelen- 

Hendrikx, director of strategy, operations backend 

innovation at NXP (Nijmegen, The Netherlands). 

She anticipates more complicated, larger dies will 

only be embedded in module or package interposer 

“First, simple small dies with low pin-count will be embedded in 

motherboards,” explains Caroline Beelen-Hendrikx, NXP 

Part of my job will be to help you develop 

marketing programs and ideas with the goal 

of educating and meeting our subscribers 

across the world. We are all partners helping 

to grow a very important industry driven by 

technology and innovation. 

Please call or email me with any questions 

or ideas. I look forward to meeting you and 

hearing from you soon! 

Bill Stinson 

VP New Media Development, Yole Inc. 

stinson@i-micronews.com 

e v e n t s 

• Embedded Wafer Level Packaging 

Workshop, Minatec Crossroads, 

June 24, Grenoble, France 

• SEMICON West, 

July 13-15, San Francisco, CA 

• SEMICON Taiwan, 

September 8-10, Taipei, Taiwan 

• ESTC - Electronics System Integration 

Technology Conference, 

September 13-16, Berlin, Germany 

secondary or coupled with electrical performance 

as to why to embed vs. other integration options.” 

Echoing industry consensus, Imbera Corp.’s 

(Melbourne, Fla.) Risto Tuominen, chief 

technology officer, and Jeff Baloun, CEO, report 

that the primary goals of most programs they’re 

involved with today are miniaturization, product 

design flexibility, and cost. 

Applications and markets 

For now, the applications and markets for the two 

technologies are different. 

Embedded 

For embedded technology, the end markets 

and applications tend to be primarily consumer 

electronics and mobile ones. 

“Following the trail blazed by cellular volumes, 

it’s expected that the eventual adoption of these 

technologies for high-performance applications 

as possible alternatives to flip chip BGAs for 

microcontrollers and high-performance memory 

packaging applications will occur,” says Tessier. 

“Embedded die memory packaging will also be 

the next trend for high-performance computing 

boards, beginning with mobile products for which 

miniaturization is critical. And she won’t be surprised 

to see memory die embedded in a BGA interposer 

for improved electrical performance. Beelen- 

Hendrikx notes that embedding as a method to 

make a package is also possible, but yield is a big 

concern. 

Smith expects to see the technology in applications 

such as RF modules, graphic processors, FPGA, 

CPU, and high-performance ASICs. 

Werner Klingenstein, director of technology 

strategy at Infineon Technologies AG (Neubiberg, 

Germany), predicts that applications will encompass 

power supply, telecommunications, RF ID — with 

ramp-up of production beginning in 2011. 

And Imbera is already in small-volume production 

today, with significant growth forecasted for the 

beginning of Q4 2010 through 2011. 

FOWLP 

Fan-out wafer-level package (FOWLP) technology 

has been pursued more publicly, albeit every bit as 

aggressively. 

The primary drivers Seung Wook Yoon, deputy 

director of technology marketing at STATS ChipPAC 

Issue sponsored by: 

More information on page 15 

Embedded WLP fan-out package cross-section (Courtesy of Imbera) 

2



Imbera embedded die packages (Courtesy of Imbera) 

(Singapore), cites are demand for thinner and 

smaller package solutions, especially for mobile 

applications; requirements for a robust package 

with copper and low-k compatibility, and lead-free/ 

halogen-free, green material sets; proven lowercost 

path using a batch process and simplified 

supply chain; extendibility of the technology for 

device integration; and eliminating the substrate 

and bumping that serves to simplify logistics and 

the supply chain. 

FOWLP has a reputation as being a very expensive 

technology, due to the need for serial die processing 

into reconstructed wafers. And the infrastructure 

needed to support FOWLP in high-volume is much 

like a wafer fab or bump fab technology that’s more 

expensive than a laminate alternative, explains 

Tessier. “FOWLP is believed by some to be a good 

option where I/O count and die size constraints 

of some potential WLCSP applications result in 

package pitches that are finer than end-users can 

use in surface mount assembly processes with 

high yields. Only a narrow range of applications 

fall into the ‘sweet spot’ of FOWLP and, as a result, 

it’s expected to find limited usefulness. FOWLP is 

in direct competition with a number of conventional 

array packaging options, including flip chip CSPs. 

The interest in FOWLP is being driven by form 

factor without any consideration to the cost of this 

technology relative to other comparable packaging 

alternatives,” he adds. 

Aggressive players 

There are many companies making bold moves in 

the embedded space, including IDMs and fabless 

design houses. The SiP fabless segment, notably, 

appears to be leading at the moment. 

FOWLP is seeing certain companies emerge as 

“big players” as well. 


In Japan, Ibiden and Casio are working within a 

powerful industry consortium to put in place the 

infrastructure to enable embedded component 

packaging technologies for cellular and consumer 

product applications, points out Tessier. “The 

Hermes consortia in Europe, led by AT&S (Austria) 

and the Fraunhofer Institute (Germany), as well 

as a number of industry leaders, is driving the 

establishment of a robust infrastructure in Europe. 

In Asia, SEMCO and Imbera, to name a few, are 

also helping to drive this revolution in 3D packaging,” 

he says. “In the area of embeddable components, 

NXP has been an industry leader among IC 

manufacturing companies. We’ve been supporting 

NXP’s vision, as well as using our single- and multilayer 

redistribution layer (RDL) technologies to 

enable the relaxation of embedded die packaging 

requirements.” 

FOWLP 

Infineon and its partners (STATS ChipPAC, 

STMicroelectronics, and ASE) are moving the most 

boldly with FOWLP technology. 

With its eWLB technology, Infineon is the 

acknowledged trendsetter in the industry. “Other 

companies who bought technology licenses (ASE, 

STATS ChipPAC, ST, and more coming soon), have 

set up substantial production capacities,” says 

Klingenstein. 

Through its partnership with Infineon, STATS 

ChipPAC ramped its first-generation eWLB 

Cross-Sectional View of an embedded die in printed wiring board fan-out interconnect (Courtesy of FlipChip) 

technology to high-volume production in the third 

quarter of 2009. “Current shipments are in excess 

of 30,000 reconstituted wafers per quarter,” notes 

Yoon. “While the rapid volume production ramp 

has taken place within a 200mm reconstituted 

wafer manufacturing process, we moved to a 

300mm reconstituted wafer manufacturing process 

to expand capacity and to realize a lower cost 

structure through the economy of scale.” 

And with the recent resolution of Freescale’s 

(Austin, Texas) and Epic Technologies’ (Woburn, 

Mass) intellectual property dispute in this space 

involving their RCP and ChipsFirst technologies, 

there’s an alternative technology source for FOWLP 

technology, as Tessier points out. 

Which current packages might the 

technologies replace? 

Between the two technologies, they’ll provide 

alternatives to many popular packages. 


The general expectation is that embedded 

technology may replace or compete with 3D 

packages ranging from stacked die and stacked 

packages. While it might not actually “replace” 

a package, it can replace the practice of external 

mounting of passives or die with the embedding 

process at the substrate manufacturing stage. 

Tessier expects embedded component technology 

packages to displace reconstructed waferbased 

fan-out WLCSP technologies. Despite the 

industry’s current preoccupation with TSV-based 

3D packaging solutions, he thinks embedded 

component technology provides a highly 

practical packaging alternative with comparable 

density potential, while avoiding the logistical 

nightmares inherent in most TSV-based packaging 

alternatives. “Embedded die applications also 

provide alternatives to flip chip BGA applications 

involving copper low-k and other fragile package 

constructions that generally don’t do well in thermal 

cycling and mechanical stressing,” he says. 

3



A limitation with embedding, beside yield, is still the 

bond pad pitch that can be handled. “So it will be 

low and medium pin-count packages, not high pincount 

BGAs. Cost and yield will determine which 

packages will be replaced,” says Beelen-Hendrikx. 

Tuominen and Baloun note that embedding is a 

subset to many of the package solutions today. In 

embedded BGA or SiP with embedded, the die is 

typically facing down, representing flip chip. If it’s 

possible to design your product into a WLP, then 

the embedded solution will become a secondary 

choice, they say, although we have reached 

physical limits that embedding can solve without 

too great of a cost overhead penalty. They expect 

typical wirebond products may see diminished 

growth as a result of embedding, but believe the 

package families themselves will continue with the 

compliment of embedded. 

FOWLP 

The general consensus is that based on its highperformance, 

small footprint, and lower cost 

structure, FOWLP could potentially replace flip chip 

FBGA and flip chip CSP packaging in the near-term 

and wirebond packages such as FBGA over the 

longer-term. With volume and cost erosion, FOWLP 

may also replace QFN for applications that don’t 

have stringent power dissipation requirements. 

Supply chain challenges 

First eWLB package was found in a LG cell-phone (Courtesy of SystemPlus Consulting) 

need to share a greater portion of the value-add 

with the high-density PCB suppliers that enable 

the high-density array packaging that will be used 

in the industry going forward, says Tessier. “Yield 

considerations are always a major concern in 

‘chips-first’ embedded component technologies,” 

he adds. “The infrastructure developed to provide 

known good WLCSPs will be leveraged to provide 

the high levels of die quality required to enable 

embedded die packaging with the yields needed to 

enable viable and cost-effective alternatives.” 

And another key point, according to Beelen- 

Hendrikx, is that now PCB manufacturers will 

be placing and interconnecting dies. The board 

manufacturer will also do final test. She believes 

this may result in issues with respect to the 

responsibilities of failures, both zero-hour and 

in the field. Also, semiconductor companies will 

have to disclose the final test program to the PCB 

manufacturer, which isn’t currently the case for 

chip-last technologies, in which the semiconductor 

manufacturer does the die placement, interconnect, 

and testing. 

FOWLP 

Since FOWLP doesn’t require substrates or 

bumping, it has a simplified logistics and supply 

chain structure. 

Beelen-Hendrikx points out that while there aren’t 

a lot of supply chain issues for FOWLP, proving 

high yield is still a problem and the reason for the 

high cost associated with the technology. “Yield is 

hampered, for example, by die shift during curing 

of the molding compound and warpage of the 

reconfigured wafer. Board-level reliability is an 

issue for larger packages,” she adds. 

Positioning embedded die vs. FOWLP 

In theory, embedded die can replace the same 

segment of products as FOWLP. The challenges 

faced by the two packaging schemes are the same: 

proving yield. “The consequences of the underlying 

two different infrastructures can be very different,” 

Yoon explains. “Embedded die using an existing 

PCB infrastructure has an advantage of cheaper 

capital, but also faces a severe yield challenge. The 

yield of manufacturing a 20-50µm feature (line and 

space) alone (without die) ranges from 70 to 95%. 

The goal is to achieve yields greater than 99% for 

a 10µm feature with die using a technology that is 

essentially already mature. The envelope is pushed 

beyond its limit here. FOWLP technology, on the 

other hand, uses a µm to sub-µm proven thinfilm 

technology infrastructure to generate a 10µm 

feature. Thus, yield is less of a challenge. Cost is a 

bigger challenge, since the equipment set is more 

expensive. The real challenge is achieving a rapid 

transition to a larger panel (300mm and beyond).” 

Yoon also believes it’s likely that embedded die will 

start with very simple, low pin-count devices to be 

embedded due to the severe challenge in yield. As a 

“Embedded die using an existing PCB infrastructure has an 

advantage of cheaper capital, but also faces a severe yield 

challenge”, explains Seung Wook Yoon, STATS ChipPAC 

result, these two package technologies may end up 

finding applications in different market segments. 

FOWLP, being an inherently more scalable 

technology, will find use in a wider spectrum of 

applications vs. embedded die, which is likely to 

remain a niche application — at least in the near 

future. 

4 


There are many challenges ahead with the supply 

chain for embedded technology, primarily because 

one hasn’t been established with clear ownership 

yet. 

SATS companies that have historically been privy 

to the majority of the value-add associated with 

semiconductor packaging will be under pressure 

to share a greater portion of this value-add with 

high-density array packaging, which will also 

To successfully compete against existing packaging 

technologies, Tuominen and Baloun say the 

embedding supply chain needs to be highly integrated 

to provide a sufficient production lead-time and costeffective 

manufacturing solution. Imbera’s approach 

is to focus on the consolidation of the whole value 

chain. Further integration is needed in the area of 

RDL and backend processes, they note. 

The bottom line is that many questions related to 

the supply chain, such as “who’s doing what,” still 

require answers, says Klingenstein. 

Optical micrograph of NXP EMBIDS 

Daisy chain test vehicle

AT&S AG 

ECP ® - Embedded Component Packaging Technology 



AT&S introduces the industry standard for embedding of active and discrete passive components inside a printed circuit 

board. ECP ® (Embedded Component Packaging) offers the most reliable chip embedding solution based on qualified 

processes validated to the highest quality standards in the industry. 

ECP ® is a highly efficient technology which benefits a broad application range, from single chip modules and printed circuit 

boards with several embedded passives up to high complexity System-in-Package modules and System-in-Board applications. 

PCB and SiB Applications 

ECP ® releases surface space for other components 

or allows the overall PCB size to be reduced 

Highly Reliable PCB for Harsh Conditions 

Car Engine Control PCB 

PCB for Portable Music Player 

Notebook and Netbook PCB 

PCB for Mobile Internet Devices 

PCB for Digital Cameras 

Mobile Modem Boards 

Mobile Phone Boards 

Hearing Aid PCB 

Integrated RFID 

Single Chip and SiP Modules 

ECP ® represents a powerful alternative for existing 

packaging types and enables advanced 3D packaging 

concepts 

ESD / EMI Protection Networks 

Power MosFet 

Power Modules 

MEMS Modules 

Sensor Modules 

RFID Modules 

Radio Modules 

Camera Modules 

IC Drivers 

Audio Modules 

DC/DC Converters 

By using the ECP ® technology, electronic products can be miniaturised efficiently while providing a whole feature-set to 

increase the overall performance of your application. 

Miniaturisation in xy dimensions and in thickness 

Integration of active and discrete passive components 

Enhanced mechanical reliability and stability by 

avoiding soldering between component and substrate 

Improved electrical performance and better thermal 

performance through short signal paths 

High flexibility in design by enabling 3D routing from 

front to back side of embedded components 

Advanced packaging capability: 3D stacking in 

package and stacking of packaged ICs 

Cost efficiency by using a large production format 

(18” x 24”) and substituting gold bonding with 

galvanic interconnection 

Nikolai Haslebner 

Product Manager 

Business Line Advanced Packaging 

e-mail: n.haslebner@ats.net 

AT&S AG 

Fabriksgasse 13 

8700 Leoben, Austria 

www.ats.net 

® Registered Trademark AT 255868 

5



Due to the robust infrastructure in place for laminatebased 

embedded die technologies, Tessier expects 

embedded die technologies will capture the lion’s 

share of 3D applications in that space. 

Some applications may be the same, Tuominen and 

Baloun say, although the embedded die application 

area is wider and the I/O range is probably also 

wider. Further, they firmly believe 2nd-gen FOWLP will 

develop the technology closer to the embedded die. 

And Klingenstein expects embedded die technology 

to find its niche in applications that don’t require fine 

pitches or high accuracy. 

Will the two technologies compete 

in the long-term (after 2013), when 

FOWLP 2nd-gen with TMV arrive, and 

FOWLP also shifts to 3D? 

Tessier expects laminate-based embedded die 

to win out both in the mid-term and long-term, 

thanks to an existing infrastructure that can support 

widespread adoption of the technology. “The 

evolution of packaging solutions to incorporate TMV 

advancements is more readily applicable to laminatebased 

solutions. It appears embedded die options 

will benefit most from TMV technologies,” he says. 

The most important objective for the technologies, 

according to Tuominen and Baloun, is to be 

technically competitive and cost-effective compared 

to existing packaging technologies. Both embedded 

die and FOWLP technologies will be further 

developed to meet these needs, they say. 

Long-term competitiveness comes from the timing 

of a credible manufacturing infrastructure, Yoon 

points out. Embedded die technology must prove 

itself within a year or so, he says, or it’s likely to 

remain a niche technology at best. 

And ultimately, as Beelen-Hendrikx notes, 

whichever technology can deliver the lowest 

cost and highest yield with acceptable reliability 

performance will eventually win out. 

3D Packaging Tool-Box 

Sally Cole Johnson for Yole Développement 

It’s entirely possible, but we’ll have to wait and see 

because opinions vary greatly. 

It’s difficult to envision 2nd-generation FOWLP with 

TMV as cost-effective as package-on-package 

(PoP) technology, says Smith. «Embedded die and 

top components must be designed so that there’s 

only one RDL per side, and small package sizes, to 

end up with a high number of die per rebuilt wafer,» 

he adds. “There may be niche applications for the 

technology, but for the mainstream, baseband 

processor, and combination memory applications 

in smartphones that PoP serves, FOWLP can’t 

cost-effectively handle the interconnect density 

requirements and package size range.” 

Source : Yole Développement, Embedded WLP – 2010 Report 

Jeff Baloun, managing director 

and CEO of Imbera Corp., has 

more than 25 years’ semiconductor 

manufacturing experience. He 

holds a B.S. degree in computer 

science-business from the Florida 

Institute of Technology. 

Caroline Beelen-Hendrikx, 

director of strategy, operations 

backend innovation at NXP, is 

responsible for the semiconductor 

packaging roadmap. She has 18 

years’ experience in electronics 

packaging and assembly at Philips 

and NXP as a process engineer and development 

manager. 

Werner Klingenstein, Ph.D., 

is the director of technology 

strategy at Infineon Technologies 

AG. He began his career with 

wafer technology development 

at Siemens Semiconductor, 

focusing on CMOS and EEPROM 

devices. He later spent 2 years on assignment 

in the U.S. working on DRAM wafer technology 

development and design interface. For the past 

13 years, Klingenstein has worked for the strategy 

department with a focus on technology screening 

and evaluation. He specializes in advanced MEMS 

and packaging technologies. 

Lee Smith is vice president 

of product marketing at Amkor 

Technology. He’s an industry 

expert in 3D packaging, with nearly 

30 years of diverse technology and 

market development experience. 

Ted Tessier is the chief technical 

officer at FlipChip International. He 

has more than 25 years’ experience 

in the semiconductor packaging 

industry and a comprehensive 

industry perspective, based 

on senior engineering and 

management positions at Nortel, Motorola, 

Biotronik, Amkor, STATS ChipPAC, and FCI. He has 

published actively and is well known in the industry 

for his work in the areas of advanced packaging 

technologies, including wafer bumping, multichip 

modules/system-in-package technologies, flip 

chips, 3D packaging, WLSCPs, and wafer-level 

processes. 

Risto Tuominen, chief technology 

officer at Imbera Corp., is responsible 

for technology licensing, technology 

roadmaps, R&D, development, 

adoption, and ramp-up to high volume. 

He graduated with a M.S. from Helsinki 

University of Technology. His major 

was Electronics Production Technology, and for his 

thesis he developed the first integrated module board 

technology generation. He later launched Imbera and 

served as CEO. 

Seung Wook Yoon, Ph.D., MBA, 

deputy director of technology 

marketing at STATS ChipPAC, is 

in charge of technology marketing 

of next-generation integration 

technology, including TSVs, 

embedded packaging, integrated 

passive device, and 3-D IC packaging. Prior to 

joining STATS ChipPAC, he was deputy lab director 

of the Microsystem, Module, and Components Lab 

at the Institute of Microelectronics in Singapore. 

Yoon received a Ph.D. in materials science and 

engineering in 1998 from KAIST in Korea. He also 

holds an MBA from Nanyang Business School in 

Singapore. He has authored more than 80 journal and 

conference papers, and holds several U.S. patents on 

microelectronic materials and electronic packaging. 

6



c o m p a n y v i s i o n 

Bosch’s BMA220 three-axis accelerometer 

is a leap forward in innovation 

From page 1 

This was the first three-axis acceleration 

sensor to be offered in a 3 mm x 3 mm x 0.9 

mm plastic package; however, within less than 

two years all their major competitors, including 

STMicroelectronics, Freescale, Analog Devices 

and Kionix, were offering similar 3 mm x 3 mm 

products targeted at the CE market. Chipworks 

provided a review of these products in a recent 

article in Yole I-Micronews. 

In late 2007, Chipworks completed a detailed 

structural analysis of the SMB380. This was 

followed by a circuit analysis of the ASIC. The 

structural analysis found that the SMB380 was 

fabricated using separate ASIC and MEMS devices 

mounted side-by-side in the plastic QFN package. 

The MEMS die was formed using a three-poly, 

DRIE surface micromachining (“Bosch-etch”) 

process. The MEMS structure showed completely 

independent capacitive sensors for X, Y and Z 

acceleration. The poly 3 used to form the movable 

structures was the thickest we had seen at that 

time. 

Since the launch of the SMB380, Bosch has 

released a number of other 3 mm x 3 mm 

accelerometers, including the BMA140 and 

BMA150 in LGA packages, which Chipworks has 

found are based on essentially the same MEMS die 

technology as the SMB380. The analog BMA140 

uses a different ASIC, while the digital BMA150 

uses the same ASIC as the SMB380. Chipworks 

has seen the BMA150 (usually unbranded) in a 

Figure 2: Tilt-View SEM Micrograph of BMA220 

MEMS Structure (Courtesy of Chipworks) 

Figure 3: BMA 220 X-ray side 

(Courtesy of Chipworks) 

variety of CE products, including most recently 

the Google Nexus One smart phone. As an aside, 

STMicroelectronics continues to win sockets in 

Apple products, including the recent design win for 

the LIS331DLH accelerometer in the new iPad. In 

January of 2010 Bosch has once again leapt ahead 

of the competition with the BMA220, which comes 

in an LGA plastic package. 

At Chipworks, we were very curious to find out how 

Bosch had achieved the smaller package size used 

for the BMA220. Our article in Yole I-Micronews 

speculated that Bosch could have achieved a 2.4 

mm x 2.4 mm package with the SMB380 MEMS 

and ASIC chips if they adopted the stacked 

geometry used by STMicroelectronics. This would 

have required thinning the ASIC die, and perhaps 

the MEMS die, to keep the thickness below 1 mm. 

Chipworks has procured samples of the BMA220 

and our analysis has confirmed that Bosch had 

indeed moved to a stacked geometry for the 

BMA220. They also needed to shrink the chip sizes 

and the ASIC thickness. A tilt-view SEM, which 

reveals the internal structure of the BMA220, is 

presented in Figure 2. 

The BMA220 is a disruptive, market leading 

innovation from Bosch. The competition for inertial 

sensor sockets in CE devices is fierce. Printed 

circuit board space is at a premium in CE products, 

and so we can expect their competitors to respond 

aggressively. STMicroelectronics is presently 

Figure 1: Decapsulated BMA220 MEMS and ASIC Chips (Courtesy of Chipworks) 

one of Bosch’s most serious competitors, and we 

might expect to see a 2 mm x 2 mm product from 

them soon (see January 7, 2010 press release). It 

is worth noting that VTI has had a 2 mm x 2 mm 

product available for more than a year. This device 

was made using their novel 3D MEMS technology 

and is essentially unpackaged, with the ASIC flipchipped 

to the underside of the silicon and glass 

MEMS device. It would appear; however, that the 

market prefers the standard LGA packaging, since 

we have not seen examples of the VTI technology 

in a commercial product. 

St.J. Dixon-Warren 

Chipworks Inc. 

sdixonwarren@chipworks.com 

St. J. (Sinjin) Dixon-Warren 

manages the Process Analysis 

group in the Technical Intelligence 

business unit at Chipworks. 

His group provides technical 

competitive analysis services 

to the semiconductor industry, 

currently with a special focus on the analysis of 

MEMS, CMOS images sensor, advanced CMOS 

and advanced Power devices. He is the Sector 

Analyst for MEMS analysis at Chipworks. 

7



E V E N T S 

Embedded wafer level packaging workshop 

On June 24, a workshop dedicated to Embedded wafer level packaging and co-organized by LETI and IMAPS-France, 

will be held during the event Minatec- Crossroad 

On June 24, a workshop 

dedicated to Embedded wafer 

level packaging will be held 

during the event Minatec- Crossroad 

2010. From 8:15 to 5:15, attends the 

two sessions – Fan-Out and Chip 

Embedding. 

Driven by the increasing demand from 

portable products and need to be 

smaller, lighter and cheaper; the wafer 

level packaging demand is growing 

strongly. Today, embedded wafer level 

package technologies are emerging 

on wafer level processes to improve integration 

level from the single chip to the SiP. Different 

concepts and various types of embedded wafer 

level packages have been developed in relation to 

application fields and market strengths. One typical 

development is a fan-out structure proposed by 

Jean-Marc Yannou, Project 

Manager, Advanced 

Packaging, WLP & 3D 

system Integration, 

Yole Développement 

many companies. The objective 

of the workshop is to present an 

overview on embedded wafer level 

packaging. The principle worldwide 

actors will attend and present the 

state of the art and the potentialities 

of innovative packaging concepts. 

Jean-Marc Yannou, Project 

Manager at Yole Développement 

and Technical Director of IMAPS- 

France, will be one of the keynote 

speakers and will chair the afternoon 

session. His presentation, entitled 

“Fan-out WLCSP and chip embedding: two different 

technologies with similar benefits”, will open the 

workshop at 8:30. 

Among the confirmed speakers, there are: Thorsten 

Meyer – Infineon, Christian Val - 3D Plus, Andreas 

Spotlight on 3DIC at SEMICON West 2010 

SEMICON West from July 13 to 15 in San Francisco, CA. 

Ostmann - Fraunhofer IZM, Jean-Charles Souriau - 

CEA/Leti, Caroline Beelen – NXP, Xavier Baraton 

– ST, Franck Murray – IPDIA, Jean-Marc Yannou - 

Yole Développement, In-Soo Kang – Nepes, Nokolai 

Haslebner - AT&S and Eric Beyne – IMEC. 

For one week, the world’s leading researchers and 

manufacturers in micro and nanotechnologies will 

meet at the MINATEC campus in Grenoble, France. 

MINATEC Crossroads offers a unique opportunity 

to network with international-caliber researchers, 

leaders of industry, and top academics in the fields 

of micro and nanotechnologies. 

For more information, please visit 

www.minatec-crossroads.com 

MINATEC Campus, Grenoble, France 

8 

3DIC technologies have jumped to the forefront 

of innovation in the microelectronics industry, 

touching every aspect of the supply chain 

from design to final test, with each step and process 

presenting unique challenges and opportunities. 

Visitors to SEMICON West 2010 next month in 

San Francisco will find a special focus on 3DIC 

throughout the exhibition as well in adjacent 

programs and events. 

Many exhibitors are planning to showcase new 

products and innovations for 3DIC, addressing 

challenges across the device manufacturing 

spectrum, from design to wafer processing, 

packaging, and test. SEMICON West 2010 will 

spotlight a number of these exhibitors as part of 

the new 3DIC TechZONE in North Hall, a dedicated 

exhibit area for companies uniquely focused on 

products and technologies for 3DIC manufacturing. 

3DIC-focused technical sessions at 

SEMICON West 2010 include: 

- «Bridging the Gap» – Tuesday, July 13, 

10:30am–12:30pm, TechXPOT (North Hall) 

Semiconductor packaging continues to play a larger 

part in the industry’s attempt to scale devices. 

Over the last few years, the attempt to stack and 

connect silicon with Through Silicon Vias (TSV) has 

increased dramatically. This session will explore 

the demands and opportunities for this emerging 

technology and other packaging technologies by 

various market segment leaders. 

- «Diving into Deep Submicron» – Tuesday, July 

13, 2:00pm–4:30pm, TechXPOT (North Hall) 

As the Semiconductor industry continues to follow 

Moore’s law, a number of challenges present 

themselves on the backend of manufacturing as 

well. As geometries continue to shrink, a greater 

apprehension of chip-to-package interaction has 

become apparent. This session will explore the next 

set of challenges with Flip-Chip, Wirebond, Wafer 

Level, and 3D IC TSV. 

- «3DIC Co-Design Challenges: How to Speed 

3DIC Development» – Tuesday, July 13, 2:00pm– 

4:30pm, TechSITE North (North Hall) 

The advantages of deploying 3DIC with TSV are 

clear, with increased speed, lower power and 

higher density among the desired outcomes. As 

the industry strives to reach these goals, engineers 

have encountered a few speed bumps. 3DIC with 

TSV requires additional attention to detail for 

semiconductor design and fabrication through 

package design and final test. This session will 

explore these new requirements and the issues that 

we’ve encountered that are slowing the successful 

adoption of high volume heterogeneous IC stacks. 

- «3D Interconnect Challenges and Need 

for Standards Workshop» – Tuesday, July 

13, 1:00pm–5:00pm, San Francisco Marriott 

Marquis 

3D integration using TSV interconnects is creating 

many new challenges for the semiconductor 

industry. Metrology, overlay alignment, thin wafer 

handling and other TSV processes are among the 

list of concerns that are high priority for robust 

high volume manufacturing. As these solutions 

are implemented, a whole host of new problems 

may arise due to collision with present equipment, 

materials and processes. This workshop will provide 

the vision, progress to date, and solicit concern 

areas for 3D TSV integration, as well as identify the 

areas of variance between existing solutions and 

proposed/ anticipated solutions. 

- «IMAPS/SEMI Workshop on Advanced 

Interconnect Technologies» – Wednesday, July 

14, 8:00am–5:00pm, San Francisco Marriott 

Marquis 

The Advanced Interconnect Technologies Workshop 

will feature presentations and discussions of 

some of the latest interconnect and processing 

technologies in electronic packaging, including: 

Nano Printing Technology and Optointerconnect; 

Integration of Packaging and Semiconductor 

Technology; Nano Materials Applications in 

Electronic Packaging Industry; 3D ICs Interconnect 

Technologies; Wafer Level Chip Scale Packaging; 

and Printed Electronics. 

A complete roundup of 3DIC at SEMICON West 

can be found online at 

www.semiconwest.org/Segments/3DIC.



c o m p a n y v i s i o n 

3-D TSV processes redefine the ‘back-end’ 

From page 1 

Copper interconnects in TSVs rely on a conventional 

damascene deposition sequence of PVD copper 

barrier-seed, followed by electrochemical copper 

fill to create the “pillars” that connect one chip to 

another. Compared to traditional dual-damascene 

copper interconnects, TSV features are extremely 

deep, in some cases 200µm. And high aspect 

ratio structures make deposition of conformal seed 

layers extremely challenging. Nonconformal copper 

seed layers have minimal sidewall coverage and 

can lead to void formation during the subsequent 

copper TSV fill step, which negatively impacts 

device reliability. 

PVD HCM technology 

While HCM sounds suspiciously like something 

straight out of Calvin & Hobbes, fortunately it’s 

not. Novellus describes its technology as using a 

patented ring of electromagnets outside the PVD 

process chamber to create a strong, locally ionized 

field that results in increased ion density. Increasing 

the ion density causes a larger fraction of the 

sputtered species to land on the sidewall, which 

results in a more conformal deposition. This highly 

conformal process eliminates the need for tapered 

sidewalls of the TSVs and allows the deposited film 

thickness to be 4x thinner than the typical PVD seed 

layers used for TSV applications (Figure 2). 

“This process can achieve void-free feature fill in 

a 60µm-deep, 10:1 aspect ratio TSV feature with 

vertical sidewalls using a 2000Å-thick copper seed 

layer,” said Girish Dixit, vice president of process 

applications and worldwide field process support at 

Novellus. “A conventional PVD approach requires 

an 8000Å-thick seed layer to achieve the same 

result. This 4x thinner TSV seed layer results in 

a substantial increase in system throughput and 

reduces the cost of consumables by more than 50% 

compared to more traditional PVD approaches.” 

Figure 2: Two separate TEMs, a barrier seed 

structure and a copper-filled structure 

(Courtesy of Novellus) 

In any of the TSV flows, eventually the material must 

be removed from the flat surface of the wafer. If it 

can be thinned down, it benefits not just the process 

being used to deposit it, but also the subsequent 

processes like CMP. “We see a large impact on 

the overall cost of the TSV using processes like 

these. We’re getting a positive response from wafer 

manufacturers, as well as the packaging houses 

because of the reduced seed thickness,” noted 

Dixit. 

What might surprise people about the barrier-seed 

technology is that even though it’s called “ioninduced 

reflow,” it’s not a high-temperature process. 

It’s deposited at a temperature of ~100°C, without 

positive heating of the wafer. The chuck that the 

wafer sits on is controlled to a very low temperature, 

explained Dixit. 

PECVD 

TSVs require a dielectric liner film that can be 

deposited over a range of temperatures, depending 

on the application it will be used for (via-middle 

or via-last). One of the primary concerns is step 

coverage. “Our focus is to ensure a high step 

coverage process for the liner dielectric film, and 

be able to achieve this at temperatures as low as 

100°C. In doing this, the technical challenge is in 

depositing a high quality film that delivers good 

electrical isolation characteristics,” Dixit said. 

Another important attribute Novellus is looking at is 

the dielectric constant, and how to keep it as low 

as possible to ensure low RC delays. Maintaining 

high film conformality to meet aspect ratios as high 

as 12:1, 15:1 and even 20:1, while maintaining the 

excellent electrical properties of the dielectric film, 

is one of the biggest challenges. Conventional 

PECVD technology isn’t really suited to providing 

conformal coverage on TSV structures with high 

aspect ratios, so significant innovation is necessary 

to ensure quality films. 

“In addition to the liner film within the TSV structure, 

another area dielectrics are used is where dielectric 

isolation is required between different wafers of 

the multi-wafer stack. In this case, the challenge 

is in depositing these PECVD dielectric films at 

low temperature (usually below 180°C) so that the 

integrity of the adhesive used to bond the silicon 

wafer to the glass or silicon substrate is preserved,” 

said Dixit. “There are two types of dielectric films 

used here. One is a copper diffusion barrier, which 

blocks the copper from connecting to the adjacent 

TSV, and a passivation layer used to isolate the 

different wafers in the stack. The big challenge here 

was to take our front-end knowledge and deposit 

films with the same quality at low temperatures.” 

Figure 1: Inova PVD equipment from Novellus 

(Courtesy of Novellus) 

Several films used in the TSV arena are much thicker 

than those in silicon processing, and there is work 

still to be done to ensure film quality. “The wafer 

thickness may vary from wafer to wafer stacked 

using TSVs, and when thick films are deposited on 

very thin substrates, an ability to modulate the backside 

dielectric film stress is required to maintain a 

flat wafer,” Dixit noted. 

The liner dielectric film and the back-side low 

temperature films have been developed with an 

aim to minimize the overall cost to the TSV stack 

through optimization of the liner conformality, liner 

dielectric constant, back-side film properties and 

the deposition rates, added Dixit. 

Electroplating 

For the past 10 years, the industry has been filling 

increasingly smaller structure sizes—from 90nm 

down to 60nm, 40nm and 20nm. The supposition 

has always been that smaller is harder. 

“When TSVs first came around, the assumption 

was that if you could fill a 22nm structure, it should 

be relatively easy to fill a 22µm structure. However, 

there are several challenges related to plating 

larger vias that simply aren’t present in leadingedge 

damascene technology,” said David Porter, 

development engineering director for Electrofill, 

at Novellus. “Working together with chemistry 

suppliers and through our own internal chemistry 

and hardware development, we’ve been able to 

engineer a plating process that overcomes the key 

challenges associated with TSV plating to produce 

intrinsically robust fill while providing process time 

and plated film characteristics consistent with our 

customers’ goals of low cost of ownership and a 

high degree of integratability.” 

9



Looking at the progression the industry’s gone 

through with TSVs, it all began with the question of 

how to fill a via. “The first step was understanding 

and developing the chemistry, the plating waveform, 

and the additive set needed to optimally fill throughsilicon 

vias,” Porter said. “We then transitioned our 

focus to ensuring the fill was reliable and robust 

across entire wafers, which incorporate millions of 

such vias. This led to another round of innovation 

which produced a couple of technologies to 

fundamentally ensure 100% void-free fill across 

an entire wafer. Going from filling a single via to 

filling a million in a reliable fashion was a big step. 

It enabled us to move past unit fill concerns to more 

integration-focused work.” 

As Novellus moved into integration, controlling 

the thermal expansion of copper became a key 

focus. “We’re looking at how to keep the copper 

mechanically in place,” said Porter. “One issue 

with TSVs, especially when putting copper inside 

silicon, is that the difference in thermal expansion 

rates between the two materials leads to an 

extrusion effect, and the copper ends up sticking 

out of the via. This was important to resolve, 

because it can happen after the wafer has been 

planarized, and you don’t want the copper moving 

once planarization is complete. Extrusion can be 

modulated by the properties of plated copper and 

the process by which copper is deposited. One of 

our key programs now is working with customers to 

develop a copper plating process that’s integratable 

from a thermal standpoint through modulation of the 

copper microstructure.” 

Reducing TSV production costs 

As far as helping to cut costs, PVD is an area in 

which advanced seed technology can provide a 

direct and immediate cost benefit. “PVD cost scales 

directly with PVD thickness so reducing the PVD 

thickness by a factor of 4 offers an immediatelyrecognizable 

cost savings,” Dixit pointed out. 

From the electrofill standpoint, cost is driven largely 

by the length of time it takes to fill large structures. 

“Typical plating rates in copper range from about 1 

to 4µm/min., so if you have a 60-100µm-deep TSV 

structure, you’re looking at a plating process that’s 

tens of minutes long,” explained Porter. “It’s quite 

expensive. So it’s critical to provide not only robust 

fill, but also a process that is as fast as possible to 

minimize the plating cost of ownership.” 

Another area Novellus is now exploring to reduce 

costs is copper overburden. Overburden is the term 

for the copper that’s plated on the field, or not in 

the vias, that must then be removed by CMP. CMP 

costs scale directly with the thickness of that film, 

so if the overburden is thick then CMP costs are 

very high. “One of our focuses is on developing 

copper plating technologies that minimize copper 

overburden, to reduce copper CMP costs and 

eliminate the need for our customers to develop new 

CMP technologies,” Porter said. “Low overburden 

Conventional PVD Cu 

Seed Thickness 

2000Å 4000Å 8000Å 

enables them to continue to use their established 

low-overburden damascene CMP technologies, 

therefore minimizing both development and unit 

process costs.” 

Partnerships 

In fact, Novellus is working with industry partners 

to design a manufacturable copper-based 3-D 

semiconductor technology using processes that 

include its PVD advanced seed, electroplated 

copper and PECVD dielectric barriers. 

Like any other advanced semiconductor process, 

TSV development requires an understanding of 

both unit process technology and final integration 

scheme. “You could bifurcate this into separate 

equipment supplier and device manufacturing 

functions, but we believe there’s a strong 

interplay between the various TSV processes and 

device integration,” Porter explained. “Effective 

development requires optimization of both unit 

process and integration, which necessitates a close 

partnership with customers.” 

This development approach is also helping resolve 

the tradeoff between the advanced technology 

required for TSV integration and cost optimization, 

which has limited TSV implementation for some 

time. TSV technology is definitely appealing and 

the applications are numerous. Partnerships will 

help accelerate the use of TSVs for advanced 3-D 

integration. 

Novellus Advanced Cu 

Seed Thickness 

2000Å 

Void Void Fill Fill 

60μm 

Figure 3: Comparison of conventional PVD and Novellus advanced copper seed technology 

for TSV applications (Courtesy of Novellus) 

Line between front-end/back-end? 

With 3-D integration, the line between front-end 

and back-end has become a serious blur. Novellus 

isn’t the only “front-end” company working in the 

“back-end” now. And it’s something we’ll probably 

be seeing much more of from now on. 

“The semiconductor industry is implementing 3-D 

integration with technologies like TSV to meet 

the needs of today’s shrinking electronics such 

as netbooks, slate computers and smartphones,” 

said Dixit. “This new technology allows multiple 

chips with different functionality to be packaged 

into one space-saving device. Chip packaging is 

traditionally performed by back-end-of-line fabs, 

using comparatively low technology processes. 

TSVs are being manufactured with front-end copper 

damascene-like advanced processing technology. 

This is where equipment suppliers will need to 

provide new processes and hardware to meet the 

requirements of this new packaging technology, 

while keeping cost goals in mind.” 

www.novellus.com 


10

(C2W or W2W) 

TSV Etch 

FEOL 1000 C 

FEOL 1000 C 

FEOL 1000 C 

BEOL 450 C 

TSV Fill 

TSV Etch 

BEOL 450 C 

FEOL 1000 C 

TSV Fill 

BEOL 450 C 

BEOL 450 C 

TSV Etch 

TSV Etch 

Thinning + 

Backside prep 

Handling carrier 

Thinning + 

Backside prep 

Handling carrier 

TSV Fill + 

Backside prep 

Handling carrier Handling carrier Handling carrier 

TSV Fill + 

Backside prep 

De-Bonding 

De-Bonding 

De-Bonding 



Single Wafer W et ProceSSorS & c leanerS 

Solid State Equipment Corporation 

FABRICATION EquI pmENT FOR THE INTEGRATED CIRCu IT INDu STRY 

SINGLE WAFER WET PROCESSORS & CLEANERS 

Configure your wet fabrication process to increase yields and lower costs with SSEC’s 3300 Series of Single Wafer Wet Processors. 

SSEC provides complete process development services to enable system configuration according to your process and manufacturing requirements. 

CLEAN 

99% Particle Removal Efficiency at the 88 nm, 65 nm, and 45 nm Nodes 

STRIP & LIFT-OFF 

Immersion and Single Wafer Processing 

High Velocity Spray 

Rotary PVA Brush 

Heated Solvent Immersion 

Heated High Pressure Scrub 

WET ETCH 

Uniform, Selective Etching on Multiple Process Levels 

COAT / DEVELOP 

Photolithography Clusters 

Wafer Thinning 

Stream Etch for Films & Metals 

Spin Coating 

Low Impact Developing 

ssecusa.com 

©2010 Solid State Corporation 

SSE-255 micronews 1/2 Ad update_v1.indd 1 

3D-IC & TSV Interconnects 

2010 Reports 

5/14/10 10:50:48 AM 

MaRKEt tREnDs 

One report update making the business case for 3D IC Packaging 

One new report to understand 3D TSV via process options 

We have identified as of today more than 15 different 300mm 3-D IC pilot lines running 

or currently being installed world-wide (within R&D centers, at packaging houses, cMos 

foundries or within IDM fabs). 

Via 

First 

Vias are 

made 

before 

CMOS 

3D TSV via integration MAIN scenarios 

Step #1 Step #2 Step #3 Step #4 Step #5 

Step #6 

KEY FEatuREs 

SSEC (nouvelle version 

• Revamped market forecasts & technology roadmaps for 3D IC components: impact 

of the economic downturn on the 3D tsV market - market forecast update for MEMs, 

cMos image sensors …- new application areas covered: HB-LED modules, power and 

solar components - business case for 3D interposers: applications, market and players. 

• 3D IC players 2009 market shares & revenues breakdown in $M (as packaging 

services or estimated in relative packaging value) 

• Supply chain perspectives, key players and emerging infrastructure for 3D 

Packaging 

• Strategic technology choices for 3D integration scenarios: analysis of the different 

possibility for the implementation of tsVs and the rationale behind – analysis of the 

cost structure for different implementation cases 

contact us 

IPD Digital 

interposer 

Via 

Middle 

Vias are 

made between 

CMOS and 

BEOL 

Via 

Last 

Vias are 

made after 

BEOL 

Via After 

Bonding 

Vias are 

made after 

Bonding 

+ 

“Via-Last” TSV 

DRAM 

DRAM 

DRAM 

DSP 

Bonding 

Thinning 

Thinning 

3D TSV Silicon interposer Concept 

PCB / laminated substrate 

“Via-First” TSV 

eRAMe 

eFLASHH 

YOLE DÉVELOPPEMENT 

eRAM 

SRAM 

Logic Multi-cores 

BAW / SAW filters 

“Integrated passive” 

Decoupling Capacitors, 

Inductors… 

eRAM 

Integrated passive 

Y O L E D É V E L O P P E M E N T 

For more information, feel free to contact David Jourdan: 

tel: +33 472 83 01 90, Email: jourdan@yole.fr 


11



I N T E R V I E W 

NANIUM one of the first company to ramp-up 

300mm eWLB into high volume production 

We recently had the chance to visit NANIUM (previously Qimonda Portugal) nearby Porto in Europe. It is a pretty nice place 

for holidays for sure… but it also has a unique situation for packaging, assembly and test in Europe. With an impressive 

cumulated fab investment of about 1B$, NANIUM, founded in 2010 as a newly independent company, is shifting its business 

model and is moving from pure DRAM memory packaging, assembly and test to enter the more diversified contract 

manufacturing & engineering services business. And the company holds its lot of surprises as they recently announced to be 

one of the first player in the world to ramp into high volume production the eWLB package technology of Infineon on 300mm! 

Yole Développement: Can you introduce 

to our readers more about NANIUM’s 

background as a newly settled company? 

Armando Tavares – President of Executive 

Board of Directors: NANIUM S.A. was formally 

established in February 2010 as an independent 

company. However, the company itself has already 

a 13 years’ long experience in the demanding 

semiconductor market. Having started back in 

1996 as Siemens Semicondutor, the site followed 

the spinoff of the group into Infineon Technologies 

(1999) and more recently into Qimonda (2006). 

NANIUM is owned by the two largest privately 

owned Portuguese banks - Banco Espírito Santo 

and Banco Comercial Português with 41,06% each 

and by the Portuguese State with 17,88%. 

We are dedicated to provide development, 

manufacturing, testing and engineering services 

in the semiconductor business, operating namely 

in WLP/RDL and in traditional substrate and 

Armando Tavares – President of Executive Board 

of Directors 

Armando Tavares graduated with a Degree in 

Electronics Engineering. He began his career at 

Texas Instruments Portugal first as Operations 

Director then as Vice President. He later spent 9 

years at Infineon Technologies, in Portugal and 

France. He also worked at Qimonda as President 

of Executive Board of directors from 2006 to 2010. 

NANIUM’s packaging, 

assembly and test facility in Porto (Portugal) 

leadframe based packages (see www.nanium. 

com). 

YD: We were very impressed with NANIUM’s 

facilities. It was like visiting an entire OSAT 

facility, but right here in Europe. Could you tell 

us more about your assembly and test facility 

as well as more about its people? 

AT: The site was designed from scratch (green field) 

to be a leading Assembly and Test SC facility. Over 

the years more than US$ 1 billion were invested in 

the latest technologies. 

NANIUM has state-of-the-art equipment and a 

highly secure, functional infrastructure, with a 

clean-room area of 20 600m 2 as well as technical 

areas and labs to support the manufacturing 

processes. With our past experience as high 

volume backend site for complex DRAM products, 

we have highly developed engineering and 

laboratorial competencies. 

Thanks to a continued investment on the training 

of our people and a limited turnover we count 

today with a very experienced, highly competent 

team prepared to meet tomorrow’s challenges 

and to provide services beyond our customer’s 

expectations. 

YD: NANIUM claims to be one of the first 

companies to have successfully settled the 

eWLB process on 300mm reconstructed wafers. 

Can you give us a word on how this technical 

achievement has been made possible? 

AT: As one of Infineon’s backend sites, we were 

involved in the development of 300mm wafer 

technology in volume capacity in the late 90’s. 

We were also pioneers in the processing of RDL 

in 300mm wafers which we produced in volume 

to meet Qimonda’s customers demand for high 

density memory modules based on DRAM MCP’s. 

Therefore, we departed with a significant advantage 

versus our competitors; not only we were already 

equipped with state-of-the-art 300mm RDL volume 

production equipment but we also had already 

gained substantial engineering knowledge and 

experience in this cutting-edge technology. 

NANIUM’s know-how, capacity and immediate 

availability were key to attract Infineon as a 

business partner and to have NANIUM as 

one of the first companies to produce 300mm 

eWLB reconstructed wafers in volume. (Volume 

production of 300mm eWLB wafers will start in the 

3rd quarter this year). 

YD: Could you share with us more about 

NANIUM’s strategy to open and grow the 

company within the IC Packaging business? 

AT: We want to make use of our existing solid base 

as a multi-faceted Backend site with solid knowhow 

and competitive cost. To be fast and efficient, 

meeting our customer’s needs. We plan to continue 

to capitalize on our high volume Probe/ Assembly 

/ Test capacity, continue to ramp our 300mm WLP 

capacity (Fan-in and Fan-out namely eWLB based) 

and make use of our fast prototyping / small series 

line to support our customer (for example SiP and 

MCP). 

12



In parallel we offer package design in partnership 

with our clients and engineering services including 

supply chain management, qualification and failure 

analysis support. 

YD: NANIUM is located in Portugal. Could you 

tell us more about what are the advantages of 

working with an OSAT partner based in Europe? 

AT: With competitive labor costs, Portugal’s 

geographic location assures a good proximity to 

customers based in Europe and USA both in terms 

of flying time as well as time zone. Also being within 

EU, Portugal has highly efficient customs with short 

cycle-times, in addition to political stability and a 

high degree of intellectual protection. 

The site itself is strategically positioned, close to an 

international airport and to a deep sea-harbor, and 

with quick access to the country’s main highways. 

Its excellent facilities allow for secure environments 

to be set-up and customized for leading edge 

products according to the client’s needs. 

Furthermore, NANIUM has a sound IT/ 

Communications infrastructure which can provide 

remote access/ interface applications by customers 

to equipment in-house. 

First 300mm eWLB reconfigured wafer (Courtesy of NANIUM, Infineon) 

Armando Tavares 

President of Executive Board of Directors 

NANIUM S.A. 

Armando.tavares@nanium.com 

Infineon IFX-213 – eWLB Package 

The first reverse engineering analysis report of a Fan-Out Wafer Level Package ! 

The Infineon eWLB is a Wafer Level Package with a Fan-Out in 

order to increase the bump number and pitch. The IFX-213 in 

eWLB package is directly assembled on a PCB, with a 0.5mm 

pitch. One redistribution layer is used for this package. 

CONSULTING 

Physical Analysis Methodology 

KEY FEATURES 

This report provides a complete teardown including: 

• Detailed photos 

• Material analysis 

• Schematic assembly description 

• Manufacturing Process Flow 

• In-depth economical analysis 

• Manufacturing cost breakdown 

• Selling price estimation 

conTAcT US 

For more information, feel free to contact David Jourdan, 

Tel: +33 472 83 01 90, Email: jourdan@yole.fr 

CONSULTING 

Analysis performed by 

CONSULTING 



Distributed by 


13



A N A L Y S T C O R N E R 

Embedded wafer-level package technologies move to 

high-volume production 

The technology isn’t new, but it’s experiencing a sudden surge of momentum. Yole analyst Jerôme Baron offers his insights 

on what’s causing the acceleration and where the market’s heading. 

While embedded wafer-level package 

technology isn’t new, it’s gaining serious 

momentum — with chip embedding 

into PCB laminate and fan-out WLP 

(FOWLP) on both 200mm and 300mm 

infrastructures currently ramping for 

high-volume production. 

The primary motivations behind 

embedded package integration include 

miniaturization, improved electrical and 

thermal performance, cost reductions, 

and simplified logistics for OEMs in 

final board assembly. 

“The initial applications for embedded 

die in PCB laminate packages will 

be rather small dies, low-pin-count 

analog applications such as RFID, 

power components (MOSFET, IGBT), 

and integrated passive devices (IPD). This will 

be driven mostly by handset applications during 

the next 2 to 4 years. As second adopters of this 

technology, the automotive and medical markets 

will later drive further its developments. And once 

the yield and test infrastructure is in place, the 

technology will spread to digital and mixed-signal 

analog applications such as GPU, CPU, memories 

stack, PMU, transceiver, audio modules, Hall effect 

sensors, and MEMS directly competing in the 

package-on-package (PoP), BGA, and QFN space 

by then,” says Baron. 

Some industry players are clearly pursuing the 

market aggressively. Baron believes that Imbera/ 

Daeduck and AT&S are making some of the boldest 

moves because they have everything 

to gain by launching a packaging 

business out of embedding die into 

PCB laminates. “PCB giant Ibiden 

is more than ready technically, but 

isn’t being quite as aggressive, since 

the company is already making the 

most of its business in the laminate 

BGA substrate space. Their pursuit 

Jérôme Baron, 

New Technologies 

Marketing, Advanced 

Packaging, Yole 

Développement 

Hurdles 

of the market will be to introduce the 

embedded die package technology 

more as an evolution of their current 

business line in flip chip BGA, etc.,” 

Baron pointed out. 

There are hurdles ahead worth noting. For starters, 

the supply chain is a huge issue. Baron believes this 

is the main challenge for embedded die technology, 

because it means that the “packaging value” will 

move to the side of the PCB/motherboard providers 

— changing who does the packaging, assembly, 

and testing of ICs. To overcome this, he says that 

serious standardization of embedded package 

technology is needed, in the same manner that it’s 

needed for 3D ICs with through-silicon vias (TSVs). 

“Only company partnerships that are able to cross 

over the traditional packaging, assembly, and test 

supply chain will be successful. A good example 

is to combine a leading analog IC player with a 

wafer-level packaging/redistribution layer partner, 

a PCB integrator, and eventually, an OSAT player. 

This type of emerging partnership is absolutely 

necessary to standardize the embedded package 

technology and to leverage an entirely new 

packaging infrastructure based on low-cost, panelsize 

PCB manufacturing techniques,” he notes. 

“Only company partnerships that are able to cross over the 

traditional packaging, assembly, and test supply chain will be 

successful” explains Jérôme Baron, Yole Développement 

Another hurdle is to overcome test and yield issues 

associated with embedded die technology. “The 

yield issue is important, but one that’s dependent 

on application (analog/power vs. digital) and player 

(high-quality and experienced vs. standard and 

low-cost PCB),” Baron says. “For example, Ibiden, 

14 

Current and future Tool-Box for 3D Packaging (Courtesy of Yole Développement, Embedded WLP – 2010 Report)



which began R&D on embedded die packages 

about 10 years ago, claims to already have yields 

greater than 98% for its embedded die packages.” 

FOWLP vs. Embedded Die Packages? 

Looking ahead a few years, the question of whether 

FOWLP, which are also currently headed for highvolume 

production, may one day compete directly 

with embedded die packages is a tricky one. At 

the moment, the two don’t compete at all and are 

targeted at entirely different applications. But that 

will likely change. 

“Unlike embedded die packages, FOWLP is targeting 

the direct replacement of higher I/O BGA package 

applications,” explains Baron. “Today, the market 

is being driven mainly by Taiwan-based ACE, but 

is now being especially accelerated by Germanybased 

Infineon for wireless communication ICs for 

Nokia and LG handsets. Infineon is on the verge 

of qualifying various subcontractors for embedded 

wafer-level BGA (eWLB) manufacturing on both 

200mm/300mm, including ASE (Taiwan), STATS 

ChipPAC (Singapore), and NANIUM (Portugal).” 

He believes, however, that over the long term, 

as standardization progresses and technology 

improvements result in better yield, greater electrical 

performance, lower profile, better testability, and 

smaller pitch features, FOWLP and embedded die 

technologies could end up competing in the fastgrowing 

3D packaging market. Both technologies 

enable the construction of increasingly more 

complex, larger system-in-package modules with 

different active and passive functions, all connected 

on both sides of an active substrate. 

Fan-Out WLP technology is extending WL-CSP application space 

(Courtesy of Yole Développement, Embedded WLP – 2010 Report) 

“Eventually, FOWLP and chip embedding into 

PCB laminates will become two more key tools in 

the expanding toolbox for 3D packaging,” Baron 

predicts. 


Embedded Wafer-Level-Packages 

Fan-out WLP / Chip Embedding in Substrate 

NEW 

REPORT 

MARKET TRENDS 

Be ready for the next generation of IC packaging & substrate assembly waves! 

• Embedded wafer-level-packaging technology is not new at all. Key 

benefits of the technology include miniaturization, improvement of 

electrical and thermal performance, cost reduction and simplification 

of logistic for OEMs 

• Things are moving really fast at the moment as this year, we see both 

Fan-Out wafer level packaging and chip embeddeding into PCB 

laminate package infrastructures emerging at the same time, ramping 

to high volume production 

KEY FEatuRES 

• Both Fan-Out WLP and Chip embedded package technologies 

analyzed 

• Key market drivers, benefits and challenges application by 

application 

• Market trends & figures with detailed breakdown by application 

• Description of the complete manufacturing tool-box for embedded 

wafer level packaging 

• Analysis of several embedded package target prices for a few key 

applications 

• Supply chain perspectives, key players and emerging infrastructure 

for embedded packaging 

3DIC 

with 

tSV 

Fan-out 

WLP 

Package 

PCB 

300mm eWLB reconfigured wafer 

(Courtesy of NANIUM / Infineon). 

Flip-Chip 

IPDs 


3-D WLP 

MEMS 


ContaCt uS 


tel: +33 472 83 01 90, Email: jourdan@yole.fr 


15



HB LED & LED Packaging 2009 

The HB LED & LED Packaging market is a high-growth field in the semiconductor industry. 

HB LED & LED Packaging 2009 highlights the main technical 

challenges, current solutions and future trends. It also includes 

market analysis on process, equipment, materials and services. 

COMPOUND SEMICONDUCTORS 

3 000 M$ 

2 500 M$ 

Cumulative market size for Die-attach, Interconnect, substrate 

and Phosphor in HB/UHB LED manufacturing process 

KEY FEATURES 

• Detailed process flow of LED packaging (dicing step, electrical 

interconnect, Wafer Level Packaging, encapsulation, substrates,…) 

• Market trends and figures for linked material and equipment 

(in million $, in number of units, ASP,…) 

• Key drivers for each technology & material in use 

• Supply chain analysis: who is doing what? 

Market size (M$) 

2 000 M$ 

1 500 M$ 

1 000 M$ 

500 M$ 

0 M$ 

2008 2009 2010 2011 2012 2013 2014 2015 

WHO SHOULD BUY THIS REPORT? 

• Equipment, material and chemical manufacturers to: 

- Have a global view on main market metrics 

- Identify new business opportunities 

- Understand the value-proposition of your product in this market 

• LED makers: 

- Get an overview on the competing solutions 

- Learn and anticipate the future trends in LED packaging 

CONTACT US 


Tel: +33 472 83 01 90, Email: jourdan@yole.fr 

(mm 3 ) 

10000 

1000 

100 

10 

0 

Volume of the © October 2009 

package 

Mold 

Top View 

Mold 

Side 

View 

Mold 

Top View 

+ heatsink 

Ceramic 

(AL 2 O 3 ) 

0.1 

0 1 10 

100 

Ceramic (AIN) 

+ heatsink 

YOL E DÉVE LOPPEMENT 

Y O L E 

Power 

D É V E L O P P E M E N T 

(W) 


About Yole Développement 

Created in 1998, Yole Développement is a market research and strategy consulting firm analyzing emerging applications using silicon and micro 

manufacturing. With 20 full time analysts tracking MEMS, Microfluidics, Compound Semiconductor, Power Electronics, Photovoltaic, Advanced 

Packaging and Nanomaterials, Yole Développement supports companies and investors worldwide to help them understand markets and follow tech 

nology trends. 

SERVICES 

• Market research and market data 

• Technology analysis 

• Market workshop 

• Strategy consulting 

• M&A support, fund raising and due diligence through Yole Finance 

CONTACTS 

For more information about : 

• Yole Développement: Jean-Christophe Eloy (eloy@yole.fr) 

• Publications: David Jourdan (jourdan@yole.fr) 

• Media activities: Sandrine Leroy (leroy@yole.fr) 

PUBLICATIONS 

• Collection of market & technology reports 

• Players & technology databases and market data 

• Manufacturing cost simulation tools 

• Component reverse costing analysis 

More information on Yole.fr in reports section 

MEDIA 

• Critical news, Bi-weekly: Micronews, the magazine 

• In-depth analysis & Quarterly Technology Magazines: MEMS Trends Magazine – 3D Packaging Magazine – PV Manufacturing Magazine 

• Online disruptive technologies website: www.i-micronews.com 

• Exclusive Webcasts 

• Live event with Market Briefings 

Editorial Staff 

Managing Editor: Jean-Christophe Eloy - Editor in chief: Dr Eric Mounier 

Editors: Jérôme Baron, Jean-Marc Yannou, Sally Cole Johnson 

PR & Media Manager: Sandrine Leroy - Assistant: Camille Favre - Production: Rouge Amande 

16

Embedded Wafer-Level-Packages - I-Micronews

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?