Fan-in WLCSP matures, what's next? IMT on the role ... - I-Micronews

M a g a z i n e o n 3 D - I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s 

I S S U E N ° 1 4 F E B R U A R Y 2 0 1 0 

E D I T O R I A L A N A L Y S I S 

2010: 

Year of the 

CMOS BSI 

sensor 

wave? 

If you are follow<strong>in</strong>g recent announcements 

<strong>in</strong> the digital imag<strong>in</strong>g area closely, you may 

have noticed that CMOS image sensors 

are on the verge of mak<strong>in</strong>g another giant 

step over CCD technology this year. And 

Japanese imag<strong>in</strong>g companies seem to be 

lead<strong>in</strong>g the way <strong>in</strong> this area! 

Indeed, Sony made the first step last 

year by <strong>in</strong>troduc<strong>in</strong>g its CMOS BSI sensor 

technology. The Japanese electronics 

To be cont<strong>in</strong>ued on page 2. 

<strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong> <strong>matures</strong>, what’s <strong>next</strong>? 

<strong>Fan</strong>-<strong>in</strong> wafer-level chip-scale packag<strong>in</strong>g is matur<strong>in</strong>g and costs are becom<strong>in</strong>g 

competitive with other ‘ma<strong>in</strong>stream’ packages, so it begs the question: what’s 

<strong>next</strong> for wafer-level packag<strong>in</strong>g? 

<strong>Fan</strong>-<strong>in</strong> wafer-level chip-scale packag<strong>in</strong>g 

(<strong>WLCSP</strong>) is matur<strong>in</strong>g and grow<strong>in</strong>g at a 

relatively brisk pace, and its success appears 

to be serv<strong>in</strong>g as a spr<strong>in</strong>gboard of sorts for the 

technology <strong>in</strong>to applications beyond handsets and 

also accelerat<strong>in</strong>g development of other types of 

wafer-level packages (WLP). So now is a perfect 

time to take a look at what the <strong>in</strong>dustry sees on the 

horizon for WLP. 

Cost 

One of the key questions now that fan-<strong>in</strong> <strong>WLCSP</strong> is 

considered ma<strong>in</strong>stream, is: Can it become cheaper 

than other compet<strong>in</strong>g semiconductor packages? 

This isn’t a simple question, because selection of 

fan-<strong>in</strong> <strong>WLCSP</strong> still depends largely on package type, 

die size, and I/O, accord<strong>in</strong>g to Eric Beyne, program 

director of the Advanced Packag<strong>in</strong>g and Interconnect 

Research Center at IMEC (Leuven, Belgium; www. 

imec.be). Reasons to use wafer-level chip-scale 

packages (<strong>WLCSP</strong>s) primarily <strong>in</strong>volve footpr<strong>in</strong>t and 

package height reductions for portable devices, he 

expla<strong>in</strong>s. 

Tom Strothmann, manager of <strong>WLCSP</strong> Bus<strong>in</strong>ess 

Development at STATS ChipPAC Inc. (S<strong>in</strong>gapore; 

www.statschippac.com), also believes that the use of 

<strong>WLCSP</strong> is still primarily driven by form factor 

rather than cost. ... 

2 

C O M P A N Y V I S I O N 

<strong>IMT</strong> on the role of Wafer-Level Packag<strong>in</strong>g <strong>in</strong> MEMS 

Innovative Micro Technology is a MEMS contract manufacturer/foundry partner. 

The company operates <strong>in</strong> one of the largest <strong>in</strong>dependent MEMS fabs <strong>in</strong> the world. 

Built for MEMS manufactur<strong>in</strong>g, <strong>IMT</strong> provides complete foundry services from 

design through production. 

Yole Développement: What MEMS devices do 

you expect to use wafer-level packag<strong>in</strong>g? 

Craig Trautman: There are several areas 

<strong>in</strong> which we expect to see the use of wafer-level 

packag<strong>in</strong>g expand, but <strong>in</strong>terest<strong>in</strong>gly, <strong>IMT</strong> has been 

us<strong>in</strong>g WLP for a number of years now. At any given 

time, <strong>IMT</strong> can have as many as 30 to 40 programs 

T O P 3 F R O M I - M I C R O N E W S . C O M 

Through Silicon Via technology is known to 

offer numerous advantages: application and 

electrical performance benefits with shortest 

connections between dies for sensitive signals, double 

side assembly solution result<strong>in</strong>g <strong>in</strong> package design 

simplification and better power supply redistribution, 

underway. Of these programs, I would estimate that 

nearly 75% use WLP for one reason or another. Today, 

I can count four different programs that comb<strong>in</strong>e four 

wafers that make up some of our more sophisticated 

devices. WLP is already be<strong>in</strong>g used across all 

of the markets and <strong>in</strong> the majority of 

devices we manufacture. ... 

IPDiA opens multi-parties 3D TSV Silicon Interposer 

Program 

IPDiA, a lead<strong>in</strong>g supplier of silicon passive components and 3D silicon packag<strong>in</strong>g 

is offer<strong>in</strong>g first call to participate to a Through Silicon Via (TSV) Multi Part Wafer 

(MPW) program also called “pizza mask”. 

6 

high density pack<strong>in</strong>g and f<strong>in</strong>ancial benefit with a high 

degree of m<strong>in</strong>iaturization and therefore lower costs. 

Thanks to this MPW opportunity, companies which 

would like to make an evaluation design with Through 

Vias <strong>in</strong> Silicon could take advantage of 

this open proposal and have the product... 

18 

Released SiO2 <strong>in</strong>terlayer dielectric shows a matrix 

of copper <strong>in</strong>terconnect traces for <strong>in</strong>terposers and 3D 

packag<strong>in</strong>g applications. 

C O N T E N T S 

A N A L Y S I S 2 

C O M P A N Y V I S I O N 6 

A N A L Y S T C O R N E R 1 6 

T O P 3 1 8 

Pr<strong>in</strong>ted on recycled paper 

Free registration on 

www.i-micronews.com

F E B R U A R Y 2 0 1 0 i s s u e n ° 1 4 

N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s 

E D I T O R I A L 

giant is now mass produc<strong>in</strong>g the CMOS 

BSI sensor <strong>in</strong> its newest video camcorders 

and digital still cameras. But Sony is not 

an isolated case as <strong>in</strong> early January, many 

other announcements have followed and not 

only Casio but also Nikon, Ricoh, Samsung, 

JVC and Fujifilm all separately announced 

their first digital camera products us<strong>in</strong>g a 

CMOS sensor… based on BSI “Backside 

illum<strong>in</strong>ation” technology! 

So, a lot of <strong>in</strong>terest<strong>in</strong>g announcements <strong>in</strong> the 

high-end imag<strong>in</strong>g market have happened 

early this year. But the low-end image sensor 

market will not stand by and watch as we 

believe that CMOS BSI technology will also 

appear <strong>in</strong>to different smart-phone camera 

products later this year. Omnivision is ready 

and currently sampl<strong>in</strong>g its second generation 

BSI image sensor. Apt<strong>in</strong>a Imag<strong>in</strong>g, Toshiba, 

Samsung and STMicro are also <strong>in</strong> the 

start<strong>in</strong>g-blocks. 

Yole is follow<strong>in</strong>g the CMOS image sensor 

market very closely for several years now. We 

are very pleased to announce the imm<strong>in</strong>ent 

release of our all new market study <strong>in</strong> this 

area. This report will of course provide the 

key technical <strong>in</strong>sights about the very latest 

technology trends such as BSI, Wafer Level 

Cameras, image stabilization and auto-focus 

technologies that are under development for 

the camera module market! 

A N A L Y S I S 

<strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong> <strong>matures</strong>, what’s <strong>next</strong>? 

From page 1 

QFN packages are the most competitive with 

<strong>WLCSP</strong> <strong>in</strong> the market space requir<strong>in</strong>g reduced 

form factor, he says. <strong>WLCSP</strong> cost is competitive 

with QFN today <strong>in</strong> small die sizes with low I/O 

counts and less expensive than QFN as the I/O 

count <strong>in</strong>creases. <strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong> is expected to 

become less expensive than QFN packages <strong>in</strong> all 

die sizes as <strong>WLCSP</strong> volume <strong>in</strong>creases. 

<strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong>s cont<strong>in</strong>ue to have the highest 

year-over-year adoption rate of all semiconductor 

packages, says Ted Tessier, chief technical 

officer of FlipChip International (Phoenix, Ariz.; 

www.flipchip.com), thanks to their m<strong>in</strong>imalist form 

factor at an attractive price po<strong>in</strong>t. “Most of the 

high-volume suppliers of <strong>WLCSP</strong>s are driv<strong>in</strong>g 

an aggressive cost-reduction roadmap and, as a 

result, the pric<strong>in</strong>g has dropped gradually. But after 

10 years of high-volume usage, cont<strong>in</strong>ued price 

reduction is becom<strong>in</strong>g <strong>in</strong>creas<strong>in</strong>gly difficult and 

level<strong>in</strong>g off,” he adds. 

lead<strong>in</strong>g semiconductor package because many 

applications where space isn’t critical don’t have 

strong drivers to migrate to <strong>WLCSP</strong>. 

“It’s one of the faster-grow<strong>in</strong>g packages, along with 

QFN, but both have a way to go to catch up with the 

more established packages, which will cont<strong>in</strong>ue to 

grow at a slower pace,” says Stepniak. 

Beyne notes that the majority of packages are 

still lead-frame-based solutions, but expects the 

compound annual growth rate (CAGR) of <strong>WLCSP</strong>s 

will be much greater. 

Expand<strong>in</strong>g to more apps? 

Another big question is: Will the success of fan<strong>in</strong> 

<strong>WLCSP</strong> <strong>in</strong> mobile applications, first <strong>in</strong>tegrated 

for size/m<strong>in</strong>iaturization drivers, allow for its wide 

adoption by other consumer applications? 

“… QFN packages are the most competitive with <strong>WLCSP</strong> <strong>in</strong> the 

market space requir<strong>in</strong>g reduced form factor …”, accord<strong>in</strong>g to Tom 

Strothmann, STATS ChipPAC Inc. 

Jérôme Baron 

Technology & Market Analyst & Editor 

baron@yole.fr 

E V E N T S 

• DATE 2010 - Design, Automation & 

Test <strong>in</strong> Europe 

March 8-9, Dresden, Germany 

• IMAPS 2010 : 6th International 

Conference and Exhibition on Device 

Packag<strong>in</strong>g, 

March 9- 11, Scottsdale, AZ, USA 

• Image Sensors Europe, 

March 23-25, London, UK 

Issue sponsored by: 

While fan-<strong>in</strong> is becom<strong>in</strong>g cheaper, so are compet<strong>in</strong>g 

semiconductor packages, po<strong>in</strong>ts out David 

Stepniak, manager of WCSP and 3D packag<strong>in</strong>g at 

Texas Instruments (Dallas, Texas; www.ti.com). He 

doesn’t anticipate a change <strong>in</strong> packag<strong>in</strong>g strategy 

between fan-<strong>in</strong> <strong>WLCSP</strong> and other packages based 

on relative price or cost changes. 

And <strong>in</strong> many cases, David Kress, director of 

Technical Market<strong>in</strong>g at Analog Devices Inc. 

(Norwood, Mass.; www.analog.com), says that 

<strong>WLCSP</strong> has already become the least expensive 

package. 

Lead<strong>in</strong>g package? 

Is fan-<strong>in</strong> <strong>WLCSP</strong> emerg<strong>in</strong>g as the overall lead<strong>in</strong>g 

semiconductor package? With so many packages 

out there to choose from, it’s hardly surpris<strong>in</strong>g that 

op<strong>in</strong>ions vary a little. 

<strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong> has the highest growth rate of 

all ma<strong>in</strong>stream semiconductor packages, says 

Strothmann, but it’s start<strong>in</strong>g from a smaller base 

than other package technologies. He expects it 

will become the dom<strong>in</strong>ant package <strong>in</strong> handheld 

products where a reduced form factor is critical, 

but feels it’s unlikely to become the overall 

“The <strong>in</strong>dustry-wide high-volume <strong>in</strong>frastructure that 

was put <strong>in</strong>to place for the fabrication, back-end die 

process<strong>in</strong>g, and surface mount technology (SMT) 

usage of <strong>WLCSP</strong>s to support the ultrahigh-volume 

requirements of mobile applications is def<strong>in</strong>itely 

provid<strong>in</strong>g a robust base from which the proliferation 

of <strong>WLCSP</strong>s is spr<strong>in</strong>g<strong>in</strong>g <strong>in</strong>to other application 

spaces,” says Tessier. “We’re see<strong>in</strong>g significant 

adoption and eng<strong>in</strong>eer<strong>in</strong>g <strong>in</strong>terest <strong>in</strong> automotive, 

medical, comput<strong>in</strong>g, and digital photography. 

SEM Photomicrograph of a <strong>Fan</strong>-In <strong>WLCSP</strong> 

embedded <strong>in</strong> a PCB lam<strong>in</strong>ate (Courtesy of FlipChip) 

2



Tessier also believes that the requirement for fanout 

<strong>WLCSP</strong>s is limited to quite a small number of 

higher I/O applications that may not be compatible 

with the pitch limitations, I/O count or other 

factors associated with fan-<strong>in</strong> <strong>WLCSP</strong>s. “There 

is a substantial amount of buzz <strong>in</strong> the <strong>in</strong>dustry <strong>in</strong> 

the area of fan-out <strong>WLCSP</strong>s today, but there are 

other packag<strong>in</strong>g options with very large <strong>in</strong>stalled 

capacities, <strong>in</strong>clud<strong>in</strong>g flip chip BGAs, wirebond 

array packag<strong>in</strong>g, etc., which will require fan-out 

<strong>WLCSP</strong>s to realize dramatic cost reductions to 

become viable alternatives,” he expla<strong>in</strong>s. 

Cross-Sectional View of an Embedded Die <strong>in</strong> Pr<strong>in</strong>ted Wir<strong>in</strong>g Board <strong>Fan</strong>-Out Interconnect 

(Courtesy of FlipChip) 

Stepniak anticipates research-related items will 

be directed more toward 3D, SiP, and MEMStype 

packag<strong>in</strong>g. “<strong>Fan</strong>-out WCSP is likely only an 

<strong>in</strong>terim step until 3D is available. <strong>Fan</strong>-<strong>in</strong> WCSP will 

cont<strong>in</strong>ue strong with similar research for apply<strong>in</strong>g 

to 3D,” he says. 

<strong>WLCSP</strong>s are also f<strong>in</strong>d<strong>in</strong>g broader use <strong>in</strong> device 

applications beyond silicon semiconductors and 

are start<strong>in</strong>g to be adopted by a broad assortment 

of substrate and device technologies, <strong>in</strong>clud<strong>in</strong>g 

MEMS, SAW and BAW filters, GaAs RF devices, 

etc.” 

There are some issues with meet<strong>in</strong>g automotive 

requirements. “Automotive and similar low to zero 

DPPM requirements are a challenge, because the 

standard <strong>WLCSP</strong> flow doesn’t have a f<strong>in</strong>al package 

test,” po<strong>in</strong>ts out Stepniak. 

And a key factor pac<strong>in</strong>g the adoption rate has been 

and will cont<strong>in</strong>ue to be board cost, Strothmann says. 

“As f<strong>in</strong>e pitch board costs decl<strong>in</strong>e, the adoption 

rate of <strong>WLCSP</strong> <strong>in</strong> other consumer applications 

will <strong>in</strong>crease. Most consumer applications are 

heavily cost-driven and the end product will use 

the least expensive solution that meets design 

requirements. Applications that use high-density 

PCBs similar to mobile applications are f<strong>in</strong>e for 

small die, low I/O count. <strong>Fan</strong>-out <strong>WLCSP</strong> will be 

more important <strong>in</strong> the future than fan-<strong>in</strong> <strong>WLCSP</strong> 

because it can deliver an I/O footpr<strong>in</strong>t that’s larger 

than the IC size,” he stresses. 

Beyne also believes that fan-out <strong>WLCSP</strong> will be 

more important <strong>in</strong> the future than fan-<strong>in</strong> <strong>WLCSP</strong>, 

because it can deliver an I/O footpr<strong>in</strong>t that’s larger 

than the IC size. 

New directions for WLP? 

Beyne. “<strong>Fan</strong>-out <strong>WLCSP</strong> is <strong>in</strong> the early phase of 

development. New solutions are required to allow 

for larger die and package size with high reliability. 

Significant improvements can still be realized. 3D 

stack<strong>in</strong>g isn’t <strong>in</strong> competition with WLP, but 3D WLP 

stacks are also possible.” 

There cont<strong>in</strong>ues to be a large amount of eng<strong>in</strong>eer<strong>in</strong>g 

activity <strong>in</strong> the <strong>in</strong>dustry to push the envelope 

of <strong>WLCSP</strong> usage to enable larger I/O counts 

through f<strong>in</strong>er pitches, improve reliability for given 

array sizes, and enable cost reduction through 

<strong>WLCSP</strong> process simplification, notes Tessier. 

He anticipates migration toward 0.3mm-pitch 

components, which will require substantial SMT 

assembly process improvements and equipment 

upgrades. In parallel to this ongo<strong>in</strong>g activity <strong>in</strong> 2D 

<strong>WLCSP</strong> packag<strong>in</strong>g activities, he expects some of 

the focus will be directed <strong>in</strong>crementally toward 3D 

<strong>WLCSP</strong> stack<strong>in</strong>g, etc. 

Strothmann expects that cont<strong>in</strong>ued research 

will make fan-<strong>in</strong> <strong>WLCSP</strong> more reliable and less 

expensive, and fan-<strong>in</strong> <strong>WLCSP</strong> will cont<strong>in</strong>ue to have 

cost advantages over competitive technologies. 

“The fan-<strong>in</strong> bump pitch will decrease and numbers of 

I/Os used on fan-<strong>in</strong> packages will <strong>in</strong>crease as new 

materials and structures become available,” he 

says. “By the nature of these technologies many 

of the <strong>in</strong>novations developed are <strong>in</strong>terchangeable 

between fan-<strong>in</strong>, fan-out, and 3D packag<strong>in</strong>g, so <strong>in</strong> 

many respects the <strong>in</strong>novation expenses are spread 

across the technologies.” 

Silicon <strong>in</strong>terposers? 

Will we see the widespread adoption of silicon 

<strong>in</strong>terposers, and will it contribute to a higher rate 

of fan-<strong>in</strong> <strong>WLCSP</strong> use <strong>in</strong> the packag<strong>in</strong>g <strong>in</strong>dustry? 

The general consensus is that it’s not likely any 

time soon because of limited applications and the 

associated high costs. 

Will more research and effort be directed toward 

mak<strong>in</strong>g cheaper or more reliable fan-<strong>in</strong> <strong>WLCSP</strong>, or 

will these <strong>in</strong>novation expenses be diverted to fanout 

<strong>WLCSP</strong> or other WLP technologies such as 

3D IC stack<strong>in</strong>g with TSVs or MEMS capp<strong>in</strong>g and 

packag<strong>in</strong>g? 

“<strong>Fan</strong>-<strong>in</strong> <strong>WLCSP</strong>s are established schemes, and 

development is ma<strong>in</strong>ly related to <strong>in</strong>cremental 

improvement of materials to obta<strong>in</strong> better thermal 

cycl<strong>in</strong>g performance. There is little value <strong>in</strong> scal<strong>in</strong>g 

I/O pitch (narrows down the application space to 

special, expensive PCB board technologies),” says 

eWLB reconstituated water (Courtesy of STATS ChipPac) 

3



“… Silicon <strong>in</strong>terposers are currently s<strong>in</strong>gle-sided relatively 

expensive <strong>in</strong>terconnection media compared to other comparable 

density PCB-based technologies …” accord<strong>in</strong>g to Ted Tessier, 

FlipChip International 

for TCE match<strong>in</strong>g or additional functionality <strong>in</strong> the 

form of power rout<strong>in</strong>g and passive components. 

Other than these segments, widespread adoption 

isn’t expected. 

<strong>Fan</strong>-<strong>in</strong> WLP market growth 

The application space is limited to high-end 

products for large silicon <strong>in</strong>terposers, accord<strong>in</strong>g 

to Beyne, like those with <strong>in</strong>tegrated functionalities 

such as ESD, RF, power-conversion modules. 

“… Silicon <strong>in</strong>terposers are currently s<strong>in</strong>glesided 

relatively expensive <strong>in</strong>terconnection media 

compared to other comparable density PCB-based 

technologies …” accord<strong>in</strong>g to Ted Tessier, FlipChip 

International 

Tessier doesn’t expect to see widespread 

adoption of silicon <strong>in</strong>terposers <strong>in</strong> the foreseeable 

future. “Silicon <strong>in</strong>terposers are currently s<strong>in</strong>glesided 

relatively expensive <strong>in</strong>terconnection media 

compared to other comparable density PCBbased 

technologies,” he expla<strong>in</strong>s. “Although 

there may be some niche opportunities for them 

<strong>in</strong> high-performance packag<strong>in</strong>g applications, the 

costs <strong>in</strong>volved will be prohibitive. There has been 

considerable <strong>in</strong>dustry mention recently <strong>in</strong> the area 

of TSV-based double-sided silicon <strong>in</strong>terposers. 

Though such double-sided silicon substrates 

should provide improved 3D functional <strong>in</strong>tegration 

potential, the added costs of z-axis process<strong>in</strong>g will 

likely provide significant cost obstacles relative to 

other options. If anyth<strong>in</strong>g, silicon <strong>in</strong>terposers will 

likely contribute to a higher rate of f<strong>in</strong>e-pitch flip 

chip usage at pitches below the practical pitches 

of lam<strong>in</strong>ate and other substrate technologies— 

typically 100µm pitch or less.” 

Widespread adoption will occur only if the 3D 

packag<strong>in</strong>g solutions without an <strong>in</strong>terposer are 

found to take longer time to develop and an <strong>in</strong>terim 

solution is needed, says Stepniak. Otherwise, it’s 

a cost adder that will be targeted for elim<strong>in</strong>ation. 

Kress believes that <strong>in</strong>terposers will be used for 

certa<strong>in</strong> applications, but aren’t likely to be adopted 

across the board, and will contribute only a small 

amount to fan-<strong>in</strong> <strong>WLCSP</strong> usage. 

And Strothmann sums it up: Silicon <strong>in</strong>terposers 

have market segments where<strong>in</strong> they add value 

Yole estimates that fan-<strong>in</strong> <strong>WLCSP</strong> now accounts 

for more than 6% of all IC packages worldwide. 

Growth of WLP-type packages is expected to 

cont<strong>in</strong>ue, with the general consensus <strong>in</strong> the 

<strong>in</strong>dustry be<strong>in</strong>g that it will likely reach between 15 to 

20% of the market with<strong>in</strong> the <strong>next</strong> decade. 

Interest<strong>in</strong>gly, Tessier believes that chip embedd<strong>in</strong>g 

WLP will displace wafer-based fan-out technology 

options like RCP and eWLB due to the very broad 

supply base for high-density PCBs. 

And Strothmann expects that penetration of these 

advanced markets will cont<strong>in</strong>ue to be limited, 

but given the rapid <strong>in</strong>crease <strong>in</strong> form factor driven 

products, estimates it may comprise as much as 

15% of all IC packages <strong>in</strong> the <strong>next</strong> few years. 

Emerg<strong>in</strong>g WLP technologies 

Will the success of fan-<strong>in</strong> <strong>WLCSP</strong> pave the way to 

further development of emerg<strong>in</strong>g 3D stack<strong>in</strong>g with 

TSV? Or fan-out <strong>WLCSP</strong> technologies? 

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“The only relationship is the potential use of WLP 

<strong>in</strong>frastructure for realiz<strong>in</strong>g 3D WLP TSVs,” says 

Beyne. “However, WLP subcontractors are under 

heavy cost pressure and operate with low marg<strong>in</strong>s 

that won’t pay for the development of novel 

technologies such as 3D WLP. The move to 3D 

technology from a WLP background is possible, 

but requires <strong>in</strong>creased process<strong>in</strong>g skills and 

significant capital expenditures.” 

Wafer-level process<strong>in</strong>g <strong>in</strong>volv<strong>in</strong>g processes 

and assembly applications are go<strong>in</strong>g to grow 

<strong>in</strong>creas<strong>in</strong>gly more popular, s<strong>in</strong>ce its parallel 

process<strong>in</strong>g enables very cost-effective packag<strong>in</strong>g 

solutions, notes Tessier. He po<strong>in</strong>ts out that although 

the <strong>in</strong>dustry currently seems to be enamored 

with TSV-based wafer/die stack<strong>in</strong>g, there are 

significant challenges associated with the logistics 

needed to support wafer-to-wafer and die-to-wafer 

<strong>WLCSP</strong> assembly (Courtesy of STATS ChipPac) 

stack<strong>in</strong>g. He expects chip-embedd<strong>in</strong>g WLP will be 

a dom<strong>in</strong>ant option over TSV 3D packag<strong>in</strong>g, s<strong>in</strong>ce 

3D <strong>in</strong>terconnects can be conf<strong>in</strong>ed to the packag<strong>in</strong>g 

part of the logistics flow. “The complexity <strong>in</strong>volved 

<strong>in</strong> align<strong>in</strong>g multiple device foundries, packag<strong>in</strong>g 

subcontractors, bump service providers to enable 

TSV 3D packag<strong>in</strong>g will be a major challenge <strong>in</strong> 

the proliferation of these technologies,” he adds. 

“More than 40 companies provide a very robust 

global supply cha<strong>in</strong> for high density, build-up flip 

chip BGA substrates today. These lam<strong>in</strong>ate-based 

embedded die options can be readily leveraged to 

provide a compell<strong>in</strong>g alternative to the wafer-levelbased 

fan-out <strong>WLCSP</strong> technology options that are 

temporarily enjoy<strong>in</strong>g the limelight today.” 

The success of fan-<strong>in</strong> <strong>WLCSP</strong> opens the door 

for the growth of fan-out as well as advanced 3D 

structures, says Stepniak. “As the WLP assembly 

<strong>in</strong>frastructure <strong>matures</strong>, <strong>in</strong>creas<strong>in</strong>g the package size 

beyond the capability of fan-<strong>in</strong> designs is a natural 

progression. <strong>Fan</strong>-out WLP and 3D structures will 

penetrate the mobile market space first for the 

same form factor and performance advantages 

that have driven the growth of fan-<strong>in</strong> products.” 

Adoption paradigm for 3D 

Will 3D stack<strong>in</strong>g with TSVs follow the same 

adoption paradigm as fan-<strong>in</strong> <strong>WLCSP</strong>, with 

m<strong>in</strong>iaturization first, then cost follow<strong>in</strong>g? 

The consensus is mixed on this one. Beyne, Kress, 

Stepniak, and Strothmann believe that it will likely 

follow a similar adoption paradigm. 

Weigh<strong>in</strong>g <strong>in</strong> with a “contrarian” viewpo<strong>in</strong>t, Tessier 

doesn’t believe it will, because the costs and 

<strong>in</strong>frastructure changes required to enable 3D 

stack<strong>in</strong>g with TSVs are very significant and affect 

the complete supply cha<strong>in</strong> from wafer fabrication 

through the wafer foundry through wafer-level 

process<strong>in</strong>g, packag<strong>in</strong>g, and test<strong>in</strong>g. “Proof of 

be<strong>in</strong>g able to achieve aggressive cost conta<strong>in</strong>ment 

goals across the whole supply cha<strong>in</strong> is go<strong>in</strong>g 

to be required for this class of technology to be 

considered. There is too much risk <strong>in</strong>volved <strong>in</strong> 

tak<strong>in</strong>g on such a far-reach<strong>in</strong>g challenge. S<strong>in</strong>ce the 

nature of fan-<strong>in</strong> <strong>WLCSP</strong>s allowed for leverag<strong>in</strong>g 

of exist<strong>in</strong>g flip chip bump<strong>in</strong>g and redistribution 

technologies, a much smaller leap of faith was 

<strong>in</strong>volved,” he says. 

Sally Cole Johnson for Yole Développement 

Eric Beyne is the Program Director 

of the Advanced Packag<strong>in</strong>g and 

Interconnect Research Centre 

(APIC) at imec. The APIC team 

performs R&D <strong>in</strong> the field of 

high-density <strong>in</strong>terconnection and 

packag<strong>in</strong>g techniques focused on 

system-<strong>in</strong>-package <strong>in</strong>tegration, 3D-<strong>in</strong>terconnections, 

wafer-level packag<strong>in</strong>g, RF front-end design and 

technology us<strong>in</strong>g <strong>in</strong>tegrated passives and RF-MEMS, 

as well as research on packag<strong>in</strong>g reliability, <strong>in</strong>clud<strong>in</strong>g 

thermal and thermo-mechanical characterization. 

Beyne obta<strong>in</strong>ed a degree <strong>in</strong> electrical eng<strong>in</strong>eer<strong>in</strong>g 

<strong>in</strong> 1983 and a Ph.D. <strong>in</strong> Applied Sciences <strong>in</strong> 1990, 

both from the University of Leuven. He has been 

with IMEC s<strong>in</strong>ce 1986 and is president of the IMAPS- 

Benelux committee, member of the IMAPS-Europe 

Liaison committee, elected member of the board 

of governors of the IEEE-CPMT society and IEEE- 

CPMT Strategic Director for Region 8. 

David Stepniak manages WCSP 

and 3D packag<strong>in</strong>g at Texas 

Instruments. He received his 

BSEE from Case Western Reserve 

University and an MBA from Butler 

University. 

Tom Strothmann manages 

<strong>WLCSP</strong> Bus<strong>in</strong>ess Development for 

STATS ChipPAC Inc. Before jo<strong>in</strong><strong>in</strong>g 

STATS ChipPAC, Strothmann 

was Vice President of New 

Bus<strong>in</strong>ess Development at FlipChip 

International. In that role he set up 

FlipChip Millennium Shanghai Co. as a jo<strong>in</strong>t venture 

partnership. He has more than 30 years’ experience 

<strong>in</strong> both wafer fabrication and flip chip wafer-level 

packag<strong>in</strong>g. 

Ted Tessier is Chief Technical 

Officer at FlipChip International. He 

has more than 25 years’ experience 

<strong>in</strong> the semiconductor packag<strong>in</strong>g 

<strong>in</strong>dustry and a comprehensive 

<strong>in</strong>dustry perspective, based 

on senior eng<strong>in</strong>eer<strong>in</strong>g and 

management positions at Nortel, Motorola, Biotronik, 

Amkor, STATS ChipPAC, and FCI. 

David Kress is Director of Technical 

Market<strong>in</strong>g at Analog Devices 

Inc. He’s responsible technical 

communications and new product 

processes and procedures. 

previously served as director of 

applications eng<strong>in</strong>eer<strong>in</strong>g, and also 

worked <strong>in</strong> analog chip design and th<strong>in</strong> film process 

technology. 

5




<strong>IMT</strong> on the role of Wafer-Level Packag<strong>in</strong>g <strong>in</strong> MEMS 

From page 1 

In the future, WLP will play a greater role <strong>in</strong> the 

<strong>in</strong>tegration of heterogeneous technologies. Right 

now, we’re see<strong>in</strong>g die-level MEMS and CMOS 

devices wire bonded and encapsulated. We also see 

build<strong>in</strong>g MEMS directly on CMOS wafers. Not too 

far off, we expect to see completed MEMS wafers 

or wafer stacks bonded to completed CMOS wafers. 

IR emitter/gas sensor is hermetically packaged at wafer 

level with sub-mTorr vacuum. As a technology platform 

<strong>IMT</strong> <strong>in</strong>tegrates wafer-level packag<strong>in</strong>g to improve 

performance and reliability, and reduce backend cost. 

Image courtesy of ICx Precision Photonics. 

YD: What key materials, equipment, and 

technologies still need to developed for MEMS 

wafer-level packag<strong>in</strong>g? 

CT: There isn’t a simple answer to this question. 

<strong>IMT</strong> has been <strong>in</strong>corporat<strong>in</strong>g WLP technology 

<strong>in</strong>to our customers’ products for a long time. Our 

standard solution already fulfills and exceeds the 

requirements of the applications it serves. We 

believe all of the build<strong>in</strong>g blocks are already out 

there. There are, however, specific applications that 

require additional R&D to better understand how 

those blocks fit together. For those applications, 

WLP has to be customized to meet a number of 

variables, such as vacuum level, thermal budget, 

and cost. 

YD: What is <strong>IMT</strong>’s approach to MEMS waferlevel 

packag<strong>in</strong>g? 

CT: <strong>IMT</strong> began WLP development <strong>in</strong> 2002, and 

manufactured its first product us<strong>in</strong>g WLP <strong>in</strong> 2003. 

We traveled some roads that led to dead ends, 

but my po<strong>in</strong>t is that WLP is not new to <strong>IMT</strong>. We’ve 

learned what works and, just as important, what 

doesn’t. Through the years, we’ve developed proven 

approaches and technologies used specifically for 

WLP applications. 

<strong>IMT</strong> now makes hermetic WLP us<strong>in</strong>g glass frit, 

eutectic, anodic, Au-Au thermocompression, and 

silicon fusion bond<strong>in</strong>g. We tailor the use of these 

depend<strong>in</strong>g upon the application. 

As device and wafer <strong>in</strong>tegration <strong>in</strong>creases, we’re 

keen to recognize temperature sensitivity to 

mechanical structures or material stresses that can 

occur from the results of additional high-temperature 

bond<strong>in</strong>g. For this reason, <strong>IMT</strong> developed a 

proprietary metal alloy bond that can be used to 

create a hermetic seal at a temperature less than 

200°C. The bond l<strong>in</strong>e width is reduced compared to 

other techniques, provid<strong>in</strong>g more usable space for 

the MEMS. This can be as big a benefit as the lowtemperature 

feature of the bond. This bond is well 

proven and has been used <strong>in</strong> many programs with 

product yields exceed<strong>in</strong>g 99%. 

Along with our diverse list of bond<strong>in</strong>g options, we 

believe that our low-temperature bond sets us apart 

<strong>in</strong> the market today. 

YD: How is <strong>IMT</strong> ‘WLP-specific’ compared to 

other MEMS foundries? 

CT: Like any pure-play foundry, <strong>IMT</strong> is very 

fortunate to get great perspective on the market 

because we’re like the ‘Switzerland’ of the MEMS 

space—we’re exposed to and service multitudes 

of customers across many diverse markets. In the 

past, technology requirements for creat<strong>in</strong>g products 

were as separate as the markets themselves. 

This isn’t the case anymore. We now see that 

technology requirements are converg<strong>in</strong>g and <strong>IMT</strong> 

f<strong>in</strong>ds it commonplace to <strong>in</strong>tegrate what were once 

disparate process technologies and modules <strong>in</strong>to 

s<strong>in</strong>gle devices at wafer level. 

<strong>IMT</strong> has developed some of the most advanced 

processes that have resulted <strong>in</strong> manufactur<strong>in</strong>g 

some of the most lead<strong>in</strong>g-edge MEMS devices 

on the market today. We’ve taken the <strong>next</strong> step to 

<strong>in</strong>tegrate these processes and materials <strong>in</strong>to s<strong>in</strong>gle, 

unique devices. Today, <strong>IMT</strong> is manufactur<strong>in</strong>g a 

device that <strong>in</strong>tegrates reflexive and refractive optics, 

3D microfluidics, and high-speed electromagnetic 

actuation us<strong>in</strong>g numerous materials <strong>in</strong> a fourwafer 

stack, mak<strong>in</strong>g what we believe is the most 

sophisticated device ever built us<strong>in</strong>g WLP. We like 

to th<strong>in</strong>k that <strong>IMT</strong> separates itself by blaz<strong>in</strong>g the trail 

<strong>in</strong> complex <strong>in</strong>tegration of process and technologies 

through WLP. 

YD: What’s <strong>IMT</strong>’s stance on us<strong>in</strong>g 3D TSV <strong>in</strong> MEMS? 

CT: Of course we’re ‘bullish.’ We’re already build<strong>in</strong>g 

products with nearly 140,000 hermetic copper 

TSVs per wafer. There’s no argument that further 

m<strong>in</strong>iaturization of products will require TSVs. 

Convenient consequences of us<strong>in</strong>g TSVs are that 

they reduce rout<strong>in</strong>g complexity and device footpr<strong>in</strong>t, 

which can ultimately lead to lower-cost products. 

Copper TSVs can dramatically improve electrical 

performance-specifically required <strong>in</strong> the RF world. As 

an example, <strong>IMT</strong>’s copper TSVs offer a DC resistance 

of less than 0.1 Ohms per via, with an <strong>in</strong>sertion loss of 

-0.1dB at 6GHz. 

Fill<strong>in</strong>g metal TSVs with higher aspect ratios and 

achiev<strong>in</strong>g good yields has been a challenge for our 

<strong>in</strong>dustry. <strong>IMT</strong> has solved the problem and shipped 

hundreds of wafers with a fully characterized 15µm x 

60µm hermetic copper TSVs. We plan to announce a 

larger TSV soon, which we’re currently characteriz<strong>in</strong>g. 

YD: Where do you see wafer-level packag<strong>in</strong>g for 

IR sensors head<strong>in</strong>g? 

CT: IR sensors are used across commercial 

applications for gases <strong>in</strong> biomedical and <strong>in</strong>dustrial 

safety, but are also used by the military. It’s an 

application <strong>in</strong> which size and weight of the emitter 

or sensor are critical. S<strong>in</strong>ce grams and millimeters 

count, we feel that WLP represents a great 

opportunity for product enhancement. But there are 

two considerations: The product must be packaged 

<strong>in</strong> high vacuum to m<strong>in</strong>imize heat loss; and due to 

the characteristics of VOx, which is the prevalent 

material for microbolometers, the bond must be 

made at low temperature. While either requirement 

on its own isn’t an issue, comb<strong>in</strong><strong>in</strong>g the two for WLP 

creates a challenge. 

This is where <strong>IMT</strong> can help. We’ve been mass 

produc<strong>in</strong>g an IR emitter and gas sensor for 

several years, which is a three-wafer-bonded 

stack packaged <strong>in</strong> a vacuum of less than 1mTorr. 

Leverag<strong>in</strong>g this process and comb<strong>in</strong><strong>in</strong>g it with 

our low-temperature hermetic alloy bond, <strong>IMT</strong> is 

positioned to help move microbolometer-based 

IR sensors <strong>in</strong>to WLP, reduc<strong>in</strong>g weight, size, and 

ultimately, cost. This is simply an evolution of 

<strong>in</strong>ternal development that we will be talk<strong>in</strong>g about 

soon. Stay tuned! 

X-ray tomography of a copper TSV wafer, show<strong>in</strong>g 

plated metal vias without voids. 

Craig Trautman, Vice President of Bus<strong>in</strong>ess 

Development at Innovative Micro Technology 

www.imtmems.com 

Craig Trautman, Vice President 

of Bus<strong>in</strong>ess Development at 

Innovative Micro Technology 

Trautman has more than 25 

years’ experience work<strong>in</strong>g <strong>in</strong> 

eng<strong>in</strong>eer<strong>in</strong>g, market<strong>in</strong>g, and 

bus<strong>in</strong>ess development <strong>in</strong> the semiconductor 

and MEMS <strong>in</strong>dustries. He holds B.S. degrees <strong>in</strong> 

Electrical Eng<strong>in</strong>eer<strong>in</strong>g and Computer Eng<strong>in</strong>eer<strong>in</strong>g 

from the University of Missouri. 

6



E V E N T 

3D Integration - applications, technology, 

architecture, design, automation and test 

DATE 2010 will be held <strong>in</strong> Dresden, Germany, on Friday March 12, 2010. 

The Design, Automation, and Test <strong>in</strong> Europe 

conference and exhibition is the ma<strong>in</strong> European 

event br<strong>in</strong>g<strong>in</strong>g together designers and design 

automation users, researchers and vendors, as well 

as specialists <strong>in</strong> hardware and software design, test 

and manufactur<strong>in</strong>g of electronic circuits and systems. 

The conference <strong>in</strong>cludes plenary <strong>in</strong>vited papers, 

regular papers, panels, hot-topic sessions, tutorials 

and workshops, two special focus days, and a track 

for executives. Friday Workshops are focus<strong>in</strong>g on 

emerg<strong>in</strong>g research and application topics. At DATE 

2010, one of the Friday Workshops is devoted to 

3D Integration. This one-day event consists of 

two <strong>in</strong>vited keynote addresses, regular and poster 

presentations, and a panel session. 

3D Integration is a promis<strong>in</strong>g technology for 

extend<strong>in</strong>g Moore’s momentum <strong>in</strong> the <strong>next</strong> decennium, 

offer<strong>in</strong>g heterogeneous technology <strong>in</strong>tegration, 

higher transistor density, faster <strong>in</strong>terconnects, and 

potentially lower cost and time-to-market. But <strong>in</strong> order 

to produce 3D chips, new capabilities are needed: 

process technology, architectures, design methods 

and tools, and manufactur<strong>in</strong>g test solutions. The goal 

of this Workshop is to br<strong>in</strong>g together researchers, 

practitioners, and others <strong>in</strong>terested <strong>in</strong> this excit<strong>in</strong>g 

and rapidly evolv<strong>in</strong>g field, <strong>in</strong> order to update each 

other on the latest state-of-the-art, exchange ideas, 

and discuss future challenges. The first edition of this 

workshop took place <strong>in</strong> conjunction with DATE 2009 

(see http://www.date-conference.com/conference/ 

date09-workshop-W5). 

The workshop program conta<strong>in</strong>s the follow<strong>in</strong>g 

elements: two <strong>in</strong>vited keynote addresses - “What 

We Have Learned from SOC Is What Is Driv<strong>in</strong>g 

3D Integration” and “OSAT – Role as Partner 

<strong>in</strong> 3D Integration” -, two sessions with <strong>in</strong> total six 

regular presentations, two poster sessions, a panel 

session. 

You are <strong>in</strong>vited to participate <strong>in</strong> the workshop. 

Participation requires registration and a registration 

fee. 

Registration will be available through the DATE’10 

web site, as well as on-site <strong>in</strong> Dresden, Germany. 

Check the DATE web site (http://www.dateconference.com) 

for rates and other <strong>in</strong>formation. 

www.date-conference.com 

Inf<strong>in</strong>eon IFX-213 – eWLB Package 

The first reverse eng<strong>in</strong>eer<strong>in</strong>g analysis report of a <strong>Fan</strong>-Out Wafer Level Package ! 

The Inf<strong>in</strong>eon eWLB is a Wafer Level Package with a <strong>Fan</strong>-Out <strong>in</strong> 

order to <strong>in</strong>crease the bump number and pitch. The IFX-213 <strong>in</strong> 

eWLB package is directly assembled on a PCB, with a 0.5mm 

pitch. One redistribution layer is used for this package. 

KEY FEATURES 

CONSULTING 

Physical Analysis Methodology 

This report provides a complete teardown <strong>in</strong>clud<strong>in</strong>g: 

• Detailed photos 

• Material analysis 

• Schematic assembly description 

• Manufactur<strong>in</strong>g Process Flow 

• In-depth economical analysis 

• Manufactur<strong>in</strong>g cost breakdown 

• Sell<strong>in</strong>g price estimation 

conTAcT US 

For more <strong>in</strong>formation, feel free to contact David Jourdan, 

Tel: +33 472 83 01 90, Email: jourdan@yole.fr 

CONSULTING 

Analysis performed by 

CONSULTING 

Y O L E D É V E L O P P E M E N T 


Distributed by 


7




Elpida looks to TSV to move beyond the DRAM bus<strong>in</strong>ess 

Elpida Memory, Inc. is try<strong>in</strong>g to diversify beyond the memory bus<strong>in</strong>ess to higher value-added systems by us<strong>in</strong>g its own 

through silicon via technology to make vertically <strong>in</strong>terconnected devices. Yole Développement partner Nikkei Microdevices 

asked Elpida Director and CTO Takao Adachi about the company’s new bus<strong>in</strong>ess strategy. 

Nikkei Micro Devices: We hear you’ve 

developed an 8G multilayer DRAM us<strong>in</strong>g 

TSV. 

Takao Adachi: The DRAM we developed is a 

n<strong>in</strong>e-layer device, with eight 1G DRAM chips and 

an <strong>in</strong>terposer layer. In 2010 we are develop<strong>in</strong>g a 

16G device composed of eight stacked 2G chips, 

which is currently very close to the commercial 

product stage. However, our aim <strong>in</strong> develop<strong>in</strong>g 

TSV stack<strong>in</strong>g technology is not just to make higher 

density memory devices. We <strong>in</strong>tend to use this key 

technology to make systems solutions, by stack<strong>in</strong>g 

memory together with other k<strong>in</strong>ds of chips like logic, 

sensors, and RF devices. We aim to make systems 

chips with TSV <strong>in</strong>stead of on-chip <strong>in</strong>tegration. 

NMD: Usually it had been the logic makers that 

have developed system solutions. 

TA: Up to now it has been primarily logic makers 

that have taken the lead<strong>in</strong>g role and come to the 

memory suppliers for components. Memory 

makers couldn’t take the lead, because memory 

chips were all JEDEC standard products. But TSV 

technology changes all that. By us<strong>in</strong>g TSV we can 

easily expand the DRAM I/O <strong>in</strong>terface bus beyond 

16 or 32 bits to as much as 1000 or 2000 bit width. 

So we can achieve far faster graphic management 

circuits, or, alternatively, can greatly lower power 

consumption. 

NMD: So TSV means that memory will determ<strong>in</strong>e 

the system capabilities. 

TA: All DRAM makers are typically whipped about 

by capex costs and spot market prices. We w<strong>in</strong> or 

lose on production capacity and price. We now aim 

to establish a better position <strong>in</strong> the electronics value 

cha<strong>in</strong>. 

NMD: What are you develop<strong>in</strong>g <strong>in</strong> logic and 

other areas besides memory? 

TA: We are form<strong>in</strong>g cooperative relationships with 

other companies to supply the other chips for our 

stacked systems devices. We are not plann<strong>in</strong>g to 

develop our own logic or RF or sensors. But <strong>in</strong> order 

to offer our own system solution, I th<strong>in</strong>k we will need 

to develop the software ourselves. 

NMD: Will the partners <strong>in</strong>clude companies from 

Taiwan and elsewhere overseas? 

TA: We currently move volume production to Taiwan 

Elpida Memory TSV Roadmap 

about six months after we start <strong>in</strong>itial production 

of DRAMs we develop <strong>in</strong> Japan. However, we 

are th<strong>in</strong>k<strong>in</strong>g of focus<strong>in</strong>g on Japanese partners for 

the TSV system solutions bus<strong>in</strong>ess, and do<strong>in</strong>g 

the whole process from design to production <strong>in</strong> 

Japan. We are currently do<strong>in</strong>g the design at our 

development center <strong>in</strong> Kanagawa, the DRAM and 

TSV process<strong>in</strong>g at the Hiroshima plant, and the 

packag<strong>in</strong>g at Akita Elpida. We have capacity for 

10,000 300mm wafers per month when demand 

warrants. 

NMD: Is the system solutions bus<strong>in</strong>ess easier 

than the DRAM bus<strong>in</strong>ess? 

TA: The problem is that the DRAM supplier is so 

far removed from the f<strong>in</strong>al customer. Without direct 

contact with the end user, we cannot respond rapidly 

enough to the market demands. By be<strong>in</strong>g <strong>in</strong> the 

system bus<strong>in</strong>ess, <strong>in</strong> direct contact with the end users, 

we can make sure we’re develop<strong>in</strong>g the right products. 

NMD: What’s the progress <strong>in</strong> solv<strong>in</strong>g the 

technical problems of <strong>in</strong>terconnect<strong>in</strong>g 

multilayer device stacks with TSVs? 

TA: The devices we will ship <strong>in</strong> 2010 are commercial 

Elpida Memory TSV roadmap. The 8G chip developed <strong>in</strong> 2009 uses a 70nm generation process. The 16G product slated for 2010 uses a 50nm process. 

(Source: Elpida Memory, Nikkei Microdevices) 

8



devices, but there are still some issues. We need 

to br<strong>in</strong>g down the <strong>in</strong>terposer costs, improve the 

high reliability test technology, and reduce process 

costs. On the stacked DRAM chips we will ship <strong>in</strong> 

2010, the TSV position on all the chips is the same, 

so no <strong>in</strong>terposer is needed. But to stack different 

k<strong>in</strong>ds of chips, <strong>in</strong>terposers will be required. To stack 

a logic chip that tends to have the TSVs <strong>in</strong> the center 

with a memory chip that has them on the periphery, 

for example, we’ll have to use an <strong>in</strong>terposer layer to 

connect the circuits. 

NMD: How will <strong>in</strong>terposer costs be reduced? 

TA: Hard issues still rema<strong>in</strong>. Silicon has excellent 

heat expansion and electrical properties, but it is 

too expensive to use. Res<strong>in</strong> is a possibility, but 

there is not yet a specific strong candidate. 

NMD: How about the other issues? 

TA: For the DRAMS we are shipp<strong>in</strong>g <strong>in</strong> 2010, we use 

dedicated test circuits on the chips, but these waste 

chip real estate, so we aim to elim<strong>in</strong>ate them. But 

this will require prob<strong>in</strong>g several thousand f<strong>in</strong>e pitch 

elements per chip without static electricity damag<strong>in</strong>g 

the circuits. It’s an extremely difficult bus<strong>in</strong>ess and 

we haven’t yet perfected the technology. 

NMD: What about lower<strong>in</strong>g production costs? 

TA: The cost of mak<strong>in</strong>g TSVs is currently around 

$130 to $150 per wafer. The target is often said to be 

$100. This level appears to be with<strong>in</strong> reach, but we 

would prefer it to be lower still. Our <strong>in</strong>ternal goal is 

$50. But gett<strong>in</strong>g there will require a radical change 

<strong>in</strong> production technology. The particular bottleneck 

is etch<strong>in</strong>g the vias and fill<strong>in</strong>g them with copper. We 

are re-th<strong>in</strong>k<strong>in</strong>g these steps. 

NMD: What about attach<strong>in</strong>g the chips? 

TA: Currently we are us<strong>in</strong>g solder bump<strong>in</strong>g. In the 

future direct copper-to-copper metal bond<strong>in</strong>g will 

likely be necessary, so we are develop<strong>in</strong>g that. 

One key is the technology for clean<strong>in</strong>g the bond<strong>in</strong>g 

surface. We are develop<strong>in</strong>g a special liquid coat<strong>in</strong>g, 

but it is not yet ready for commercial production. I 

th<strong>in</strong>k stack<strong>in</strong>g the chips after dic<strong>in</strong>g (chip-to- chip) 

will be the ma<strong>in</strong> approach. Wafer-level stack<strong>in</strong>g 

before dic<strong>in</strong>g (wafer-to-wafer) is possible, but 

won’t work for chips of different sizes, and will also 

have issues with lower yields. But a wafer-scale 

process could be used to put each chip on a silicon 

<strong>in</strong>terposer. 

NMD: Is customer attitude chang<strong>in</strong>g towards 

TSV chip stack<strong>in</strong>g? 

TA: We are currently talk<strong>in</strong>g to customers who are 

look<strong>in</strong>g for higher performance for graphics and 

server management applications. I used to get the 

impression that customers were look<strong>in</strong>g far ahead, 

but lately they’re start<strong>in</strong>g to talk about nearer time 

frames. 

Paula Doe for Yole Développement 

Translated by permission of Nikkei Microdevices 

Takao Adachi, Elpida Memory, 

Director and CTO, New 

Technology Development 

Elpida Director and CTO Takao 

Adachi previously served as the 

general manager of technology 

development. Prior to jo<strong>in</strong><strong>in</strong>g Elpida, he was 

project manager of plann<strong>in</strong>g and development 

for the First Memory Division of NEC. He also 

concurrently serves as a director of Rexchip 

Electronics Corp. <strong>in</strong> Taiwan. (Courtesy of Nikkei 

Microdevices) 

KEY FEATURES 

TSV CoSim + 

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Evaluate the Cost of Ownership for your TSV Scenario with this New Version 

of Yole Simulation Tool 

T he functions: 

• Possibility to run the cost simulation for different geographical zone, 

clean room class … 

• Integrated fab units database 

• Integrated Alchimer AquiVia process for comparison between 

wet and dry processes for <strong>in</strong>sulation/seed/barrier 

• Integrated equipment, wafer & materials databases 

• Two calculation modes: dedicated and non-dedicated fab 

• Up to five scenarios simulation allow<strong>in</strong>g the user to compare 

yields improvement, manufactur<strong>in</strong>g location impact on cost… 

The use of TSV CoSim+ : 

• Understand<strong>in</strong>g of the cost structure 

• Competitive analysis 

• Cost evaluation for different technological options 

• Identification of the cost pa<strong>in</strong> po<strong>in</strong>ts <strong>in</strong> your process 

ConTACT Us 

For more <strong>in</strong>formation, feel free to contact David Jourdan, 

Tel: +33 472 83 01 90, Email: jourdan@yole.fr 




9




Packag<strong>in</strong>g challenges <strong>in</strong> high performance comput<strong>in</strong>g 

Over the past half century, the semiconductor <strong>in</strong>dustry has been at the forefront of technological progress as demonstrated 

by its own products and what they have made possible. The ma<strong>in</strong> areas of improvement <strong>in</strong>clude functionality per unit 

volume, speed of performance, power consumed per unit performance, cost per function, etc. The bulk of the credit goes 

to the m<strong>in</strong>iaturization and <strong>in</strong>tegration at the chip/wafer level as predicted by Moore’s Law, and made possible through 

advancements <strong>in</strong> manufactur<strong>in</strong>g, design, simulation and materials. 

Even less than twenty years back, packag<strong>in</strong>g 

was considered an afterthought by 

most of the <strong>in</strong>dustry, though the high 

performance comput<strong>in</strong>g segment was the first 

to devote significant resources for optimiz<strong>in</strong>g 

the package performance. Start<strong>in</strong>g with the 

C4 flip-chip package, there have been steady 

improvements <strong>in</strong> high performance packag<strong>in</strong>g 

<strong>in</strong>clud<strong>in</strong>g hav<strong>in</strong>g <strong>in</strong>terconnects greater than 

10,000, pitch less than 200 µm, migration from 

ceramic to organic substrates, and from highlead 

to lead-free <strong>in</strong>terconnects. But fundamental 

challenges rema<strong>in</strong>, and the ones that impact 

packag<strong>in</strong>g are: (i) cost-effective manufactur<strong>in</strong>g 

with <strong>in</strong>terconnects at f<strong>in</strong>er pitch than 150 µm, (ii) 

mitigat<strong>in</strong>g the failures <strong>in</strong>duced by high currents 

due to the phenomenon termed electromigration, 

(iii) reliability of low-k dielectrics and <strong>in</strong>terconnects 

under thermo-mechanical loads, and (iv) materials 

and assembly issues. The <strong>in</strong>dustry is address<strong>in</strong>g 

these issues through (i) substrate development 

<strong>in</strong>clud<strong>in</strong>g solder on pad application improvements, 

(ii) <strong>in</strong>terconnect modifications to avoid Copper 

depletion and creation of voids, (iii) optimiz<strong>in</strong>g the 

underfill properties to balance the stresses <strong>in</strong> the 

low-k dielectric and <strong>in</strong>terconnects, and (iv) underfill 

process improvements us<strong>in</strong>g jet or vacuum 

dispense. 

The one feature that has the most impact on 

the above mentioned issues is the <strong>in</strong>terconnect 

structure. The current ones <strong>in</strong> the <strong>in</strong>dustry 

<strong>in</strong>clude high-lead solder bump, lead-free bump, 

copper core, copper post, etc. In this article, an 

<strong>in</strong>terconnect structure called µPILR TM <strong>in</strong>terconnect 

is presented <strong>in</strong> detail as it addresses each of 

the four challenges identified above. It consists 

of a substrate manufactur<strong>in</strong>g technique that 

results <strong>in</strong> a copper structure on a substrate pad. 

This elim<strong>in</strong>ates the need for apply<strong>in</strong>g solder on 

substrate, which is an issue at f<strong>in</strong>er pitches. Due 

to the presence of copper structure, the failure due 

to electromigration phenomenon is significantly 

delayed on the substrate side due to the fact 

that there is enough copper to eventually form a 

relatively stable <strong>in</strong>termetallic, which has much 

lower migration rate compared to copper <strong>in</strong> t<strong>in</strong>. 

This retards the void growth and hence improves 

reliability. Due to the 3D nature of the µPILR 

<strong>in</strong>terconnect, the aspect ratio (height to diameter) 

is higher than a solder bump; which eases the 

package assembly issues such as <strong>in</strong>terconnect 

jo<strong>in</strong>ts yield, underfill voids, etc. F<strong>in</strong>ally, the reliability 

is improved because the fracture toughness of the 

µPILR <strong>in</strong>terconnect is higher than solder bump 

as the µPILR structure acts as a fatigue crack 

growth <strong>in</strong>hibiter. It also offers better low-k dielectric 

reliability as the lead-free solder <strong>in</strong>terface on the 

chip side exerts lower stress than the copper post 

on chip. This article presents design, simulation, 

substrate manufactur<strong>in</strong>g, package assembly, 

electromigration and reliability results for a test 

vehicle represent<strong>in</strong>g CPU applications. 

Flip-chip <strong>in</strong>terconnects 

There are three ma<strong>in</strong> types of flip-chip <strong>in</strong>terconnect 

be<strong>in</strong>g used <strong>in</strong> the <strong>in</strong>dustry: high-lead bump, leadfree 

bump and copper post. The high-lead bump 

is be<strong>in</strong>g phased out due to ROHS requirements. 

The lead-free bump has f<strong>in</strong>e-pitch limitations due 

to solder collapse and has low electromigration 

performance. The copper post is emerg<strong>in</strong>g as 

an option for high performance packag<strong>in</strong>g as 

it offers f<strong>in</strong>e pitch capabilities and has good 

electromigration performance. Some of the issues 

with copper post on chip are lower reliability 

with extreme low-k dielectrics and relatively 

higher cost. In this paper, a new type of flip-chip 

<strong>in</strong>terconnect called µPILR is presented that offers 

the advantages of copper post on chip (f<strong>in</strong>e pitch 

and good electromigration performance) while 

offer<strong>in</strong>g good reliability and lower cost. 

The typical failure modes seen <strong>in</strong> <strong>in</strong>terconnects 

are related to <strong>in</strong>terconnect reliability (solder jo<strong>in</strong>t 

fatigue life), package reliability (low-k dielectric 

crack<strong>in</strong>g) and package performance (void<strong>in</strong>g 

due to electromigration phenomemon from high 

Figure 1: µPILR substrate with <strong>in</strong>terconnects that are highly co-planar 

current densities). A new <strong>in</strong>terconnect design has 

to address these issues while offer<strong>in</strong>g a roadmap 

to f<strong>in</strong>e-pitch well below 100 µm and be able to 

be manufactured us<strong>in</strong>g conventional <strong>in</strong>dustry 

equipment and materials. The µPILR <strong>in</strong>terconnects 

consist of an array of solid copper pillars that are 

part of the substrate. Depend<strong>in</strong>g on the method of 

manufactur<strong>in</strong>g, these <strong>in</strong>terconnects have different 

sizes and shapes, and can be jo<strong>in</strong>ed to chips with 

or without copper posts. Some of the different 

configurations. 

µPILR substrate 

The µPILR substrate can be manufactured with 

or without lam<strong>in</strong>ate core. The coreless method 

consists of start<strong>in</strong>g with a copper sheet as the 

base layer, carry<strong>in</strong>g out the build-up process to 

the required number of layers and then process<strong>in</strong>g 

the copper sheet to form µPILR <strong>in</strong>terconnects. The 

core-based substrate approach consists of start<strong>in</strong>g 

with a conventional substrate and then attach<strong>in</strong>g 

a copper sheet and form<strong>in</strong>g µPILR <strong>in</strong>terconnects. 

The ma<strong>in</strong> technical challenges <strong>in</strong> this process are: 

• Uniformity of jo<strong>in</strong><strong>in</strong>g layer and its surface 

properties • Formation of µPILRs through various 

techniques 

• Remov<strong>in</strong>g of jo<strong>in</strong><strong>in</strong>g layer and <strong>in</strong>termetallics 

without damag<strong>in</strong>g the top circuit layer and 

Uniformity of solder mask and alignment 

Figure 1 shows the µPILR <strong>in</strong>terconnects on the 

substrate. As they are formed from a copper sheet, 

the measured co-planarity was excellent (± 2 µm). 

10



Reliability 

The reliability simulations were done compar<strong>in</strong>g 

the copper post on chip and µPILR <strong>in</strong>terconnects 

under two test conditions, -55 to 125 0C (thermal 

shock) and 0 to 100 °C (thermal cycl<strong>in</strong>g). The 

µPILR <strong>in</strong>terconnect is expected to pass the 

reliability tests and is approximately 20% better 

<strong>in</strong> fatigue life, which is primarily due to the extra 

amount of solder. Reliability test<strong>in</strong>g was also done 

and no failures were observed after 1000 cycles 

under -55 to 125 °C thermal shock test conditions. 

Conclusions 

The substrates underwent conventional hot oil 

tests (20-260 °C, 50 cycles) successfully. Bump 

shear tests were done before and after age<strong>in</strong>g (150 

°C, 1000 hours) and the shear force was <strong>in</strong> 40-60 

gm range, well above the required 35 gm force. 

Test vehicle design and assembly 

The test vehicle was designed to represent a high 

comput<strong>in</strong>g application. The chip measured 20 mm 

x 18 mm x 0.75 mm with 10,132 <strong>in</strong>terconnects at 

0.15 mm (signal) and 0.2 mm (power/ground) pitch. 

The substrate measured 40 mm x 40 mm x 1.2 

mm and had 10 metal layers <strong>in</strong> a 3-4-3 build-up on 

core stack. The <strong>in</strong>terconnect details along with the 

package cross-section are given <strong>in</strong> Figure 2. 

The package assembly was done us<strong>in</strong>g 

conventional flip-chip equipment and processes. 

After process optimization, both flip-chip reflow 

and underfill processes were close to 100% yield. 

Figure 3 shows the package assembly results. 

After the underfill process, the heat spreader was 

attached with Indium as the thermal <strong>in</strong>terface 

material (TIM), accord<strong>in</strong>g to the design as shown 

<strong>in</strong> Figure 2. 

Figure 2: Test vehicle design for reliability and electromigration test<strong>in</strong>g 

Electromigration performance 

For high performance comput<strong>in</strong>g, two ma<strong>in</strong> 

requirements are electromigration performance 

and reliability. The electromigration test<strong>in</strong>g 

was done under two different conditions. The 

samples passed 1300 hours without failure under 

accelerated test conditions of 30.0kA/cm2 (1.0A) 

& 160°C and passed 1000 hours without failure 

under highly accelerated test conditions of 45.0kA/ 

cm2 (1.5A) & 160°C. The resistance was monitored 

cont<strong>in</strong>uously and the rise <strong>in</strong> resistance was less 

than 3%. There are no voids on the substrate side 

and void formation can be seen on the chip side. 

Compared to published results for high-lead 

bump, lead-free bump and copper post on chip, 

these results are the best when the acceleration 

factors are taken <strong>in</strong>to account. It is estimated 

that the acceleration factor is approximately 2.5x 

from 15.0kA/cm2 to 45.0kA/cm2, and about 2x 

from 125 °C to 160 °C for a total of 5x for 45.0kA/ 

cm2 & 160°C compared to 15.0kA/cm2 & 115°C 

test conditions. This implies that 1000 hours of 

successful test<strong>in</strong>g under 45.0kA/cm2 & 160°C 

corresponds to about 5000 hours under 15.0kA/ 

cm2 & 115°C, which is better than the results 

published <strong>in</strong> for copper posts on chip. 

The packag<strong>in</strong>g performance has to keep improv<strong>in</strong>g 

to meet the ITRS roadmaps and to m<strong>in</strong>imize 

negatively impact<strong>in</strong>g the performance of the chip 

and the system. The flip-chip <strong>in</strong>terconnects are 

the key enablers for better package performance 

through improvements <strong>in</strong> f<strong>in</strong>e-pitch, current 

carry<strong>in</strong>g capacity and reliability. High-lead 

bumps are be<strong>in</strong>g phased out and lead-free 

bumps have limitations regard<strong>in</strong>g f<strong>in</strong>e-pitch and 

electromigration performance. Copper post on 

chip and µPILR on substrate are two <strong>in</strong>terconnect 

technologies that meet the future packag<strong>in</strong>g 

requirements, with µPILR expected to perform 

better <strong>in</strong> reliability. The reliability benefit gets 

more pronounced with the transition from low-k to 

extreme low-k dielectrics on the chip side. More 

research work is ongo<strong>in</strong>g with µPILR <strong>in</strong>terconnects 

and more research <strong>in</strong> general is needed by the 

<strong>in</strong>dustry to ensure that the packag<strong>in</strong>g for high 

performance comput<strong>in</strong>g facilitates excellent 

electrical and thermal performance while meet<strong>in</strong>g 

reliability and cost requirements. 

Ilyas Mohammed 

Tessera Inc. 

3025 Orchard Parkway, San Jose CA 95134 

www.tessera.com 

Ilyas Mohammed 

Figure 3: Package assembly results us<strong>in</strong>g conventional flip-chip reflow and underfill processes yielded near 100% 

with well-aligned jo<strong>in</strong>ts and void-free underfill 

Ilyas Mohammed is director, package development 

Micro-electronics, at Tessera Technologies <strong>in</strong> San 

Jose, Calif. Prior to this position, Mohammed 

served as senior manager, Design and Simulation, 

and lead eng<strong>in</strong>eer<strong>in</strong>g, Micro-electronics Products, 

at Tessera. He is a post doctoral fellow at The 

University of Texas at Aust<strong>in</strong>, and holds degrees 

from Iowa State University <strong>in</strong> Ames, Iowa, and the 

Indian Institute of Technology <strong>in</strong> Madras, India. 

11

(C2W or W2W) 

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Handl<strong>in</strong>g carrier 

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De-Bond<strong>in</strong>g 





two day <strong>in</strong>tertechpira conference plus expert pre-conference workshop 

Image Sensors Europe 2010 

Focus on digital imag<strong>in</strong>g 

23 – 25 March 2010 

Copthorne Tara Hotel, London, UK 

www.image-sensors.com 

Image Sensors Europe (ISE) is the lead<strong>in</strong>g <strong>in</strong>dustry event 

where the leaders of the image sensors world convene to meet 

new customers, suppliers and partners each year. 

ISE 2010 attendees will... 

» See where the image sensors market is head<strong>in</strong>g 

» Get to grips with the latest technical advances 

» Improve speed and efficiency of configuration 

» Learn about new niche markets and opportunities 

» Hear the latest on future applications such as gesture control 

» Network with the lead<strong>in</strong>g players <strong>in</strong> the European market 

» Experience the whole conference on a state-of-the-art AV system 

» Be a part of THE <strong>in</strong>dustrial forum for image sensors <strong>in</strong> Europe! 

Book onl<strong>in</strong>e at www.image-sensors.com 

or call us on +44 (0) 1372 802164 

Featur<strong>in</strong>g over 30 presentations from: 

Alacron / Panavision • Apt<strong>in</strong>a • Awaiba 

BBC Research • Chipworks • CMOSIS • CSEM 

DALSA • DXO Labs • FormFactor 

Heidelbery University • Imatest 

InVision Technologies • Micazook • RICAtek Ltd 

Sony • Silicon Hive • ST Microelectronics 

Tessera • University of Sheffield 

...plus many others! 

3D-IC & TSV Interconnects 

2010 Reports 

MaRKEt tREnDs 

One report update mak<strong>in</strong>g the bus<strong>in</strong>ess case for 3D IC Packag<strong>in</strong>g 

One new report to understand 3D TSV via process options 

We have identified as of today more than 15 different 300mm 3-D IC pilot l<strong>in</strong>es runn<strong>in</strong>g 

or currently be<strong>in</strong>g <strong>in</strong>stalled world-wide (with<strong>in</strong> R&D centers, at packag<strong>in</strong>g houses, cMos 

foundries or with<strong>in</strong> IDM fabs). 

Via 

First 

Vias are 

made 

before 

CMOS 

3D TSV via <strong>in</strong>tegration MAIN scenarios 

Step #1 Step #2 Step #3 Step #4 Step #5 

Step #6 

KEY FEatuREs 

• Revamped market forecasts & technology roadmaps for 3D IC components: impact 

of the economic downturn on the 3D tsV market - market forecast update for MEMs, 

cMos image sensors …- new application areas covered: HB-LED modules, power and 

solar components - bus<strong>in</strong>ess case for 3D <strong>in</strong>terposers: applications, market and players. 

• 3D IC players 2008 market shares & revenues breakdown <strong>in</strong> $M (as packag<strong>in</strong>g 

services or estimated <strong>in</strong> relative packag<strong>in</strong>g value) 

• Supply cha<strong>in</strong> perspectives, key players and emerg<strong>in</strong>g <strong>in</strong>frastructure for 3D 

Packag<strong>in</strong>g 

• Strategic technology choices for 3D <strong>in</strong>tegration scenarios: analysis of the different 

possibility for the implementation of tsVs and the rationale beh<strong>in</strong>d – analysis of the 

cost structure for different implementation cases 

contact us 

For more <strong>in</strong>formation, feel free to contact David Jourdan: 

tel: +33 472 83 01 90, Email: jourdan@yole.fr 

Via 

Middle 

Vias are 

made between 

CMOS and 

BEOL 

Via 

Last 

Vias are 

made after 

BEOL 

Via After 

Bond<strong>in</strong>g 

Vias are 

made after 


“Via-Last” TSV 

DRAM 

DRAM 

DRAM 

IPD Digital 

DSP 

<strong>in</strong>terposer 

+ 

PCB / lam<strong>in</strong>ated substrate 

Th<strong>in</strong>n<strong>in</strong>g 


Th<strong>in</strong>n<strong>in</strong>g 

3D TSV Silicon <strong>in</strong>terposer Concept 

“Via-First” TSV 

“Integrated passive” 

Decoupl<strong>in</strong>g Capacitors, 

Inductors… 

eRAMe 

eFLASHH 

eRAM 

Y O L E D É V E L OeRAM 

P P E M E N T 

SRAM 

Logic Multi-cores 

BAW / SAW filters Integrated passive 



12




OmniBSI: the third approach to Backside 

Illum<strong>in</strong>ated (BSI) Sensor Integration 

In summary, BSI technology for small pixel CMOS image sensors (CIS) enables <strong>in</strong>creased fill factor and quantum efficiency, 

reduced pixel cross talk, and th<strong>in</strong>ner camera modules. Image sensor technologists migrat<strong>in</strong>g to a BSI configuration have 

many new (for them) eng<strong>in</strong>eer<strong>in</strong>g problems to solve. 

The choices of start<strong>in</strong>g substrate (bulk 

vs. SOI), carrier wafer bond, substrate 

thickness, surface passivation, and 

pixel isolation can <strong>in</strong>fluence both the sensor’s 

manufactur<strong>in</strong>g cost and performance. Once the 

BSI sensor’s desired performance is set at the 

silicon level, it still needs to be <strong>in</strong>tegrated <strong>in</strong>to 

the camera module supply cha<strong>in</strong>. To achieve this 

<strong>in</strong>tegration, companies need to choose a course 

for packag<strong>in</strong>g, whether it be through licens<strong>in</strong>g or 

<strong>in</strong>novation. Mak<strong>in</strong>g this decision is not optional; 

the reality of a th<strong>in</strong> substrate BSI sensor forces an 

eng<strong>in</strong>eer<strong>in</strong>g response. 

metallization to the edge <strong>in</strong> front illum<strong>in</strong>ated 

sensors was easily transferrable to the BSI 

solution. By go<strong>in</strong>g horizontal first, and then 

connect<strong>in</strong>g the traces with a sidewall redistribution 

layer, a flip of the image sensor substrate had 

m<strong>in</strong>imal impact on the new packag<strong>in</strong>g. Despite the 

radical reeng<strong>in</strong>eer<strong>in</strong>g of the now 2.1 µm thick CIS 

substrate, OmniVision/TSMC were able to avoid 

Three avenues exist for BSI sensor <strong>in</strong>tegration: 

wafer level chip scale packag<strong>in</strong>g (WL-CSP) both 

with and without through silicon vias (TSVs), and 

backside wire bond<strong>in</strong>g. Be<strong>in</strong>g early adopters of 

WL-CSP packag<strong>in</strong>g for their front illum<strong>in</strong>ated 

sensors, OmniVision and foundry partner TSMC 

were fortuitously able to recycle their exist<strong>in</strong>g 

solution for their bulk BSI process. A quick review 

of OmniVision’s advanced packag<strong>in</strong>g roadmap 

beg<strong>in</strong>s with its 2003 <strong>in</strong>vestment <strong>in</strong> Taiwanese 

wafer level packag<strong>in</strong>g (WLP) company X<strong>in</strong>tec 

Inc. TSMC has also been a longtime <strong>in</strong>vestor <strong>in</strong> 

X<strong>in</strong>tec, f<strong>in</strong>ally tak<strong>in</strong>g a controll<strong>in</strong>g share <strong>in</strong> 2007. 

X<strong>in</strong>tec licensed Shellcase/Tessera’s ShellOP WLP 

technology <strong>in</strong> 2002, mak<strong>in</strong>g it an attractive partner 

for OmniVision/TSMC. Chipworks found this <strong>in</strong> use 

<strong>in</strong> 2007, <strong>in</strong> an OmniVision 2 Mp front illum<strong>in</strong>ated 

camera module. The sensor had a thickness of 

700 µm, as measured from the top of Glass 1 to 

the bottom of Glass 2. 

Figure 1 X<strong>in</strong>tec WL-CSP for BSI – Cross Section Overview 

OmniVision chose to <strong>in</strong>sert its BSI technology 

at the 1.4 µm pixel generation. After hav<strong>in</strong>g codeveloped 

the process flow with TSMC, mass 

production began <strong>in</strong> early 2009, with X<strong>in</strong>tec 

cont<strong>in</strong>u<strong>in</strong>g to handle the packag<strong>in</strong>g. Chipworks 

analyzed a 5 Mp OmniBSI CIS (OV5642), a cross 

section of which is shown <strong>in</strong> Figure 1. At a glance, 

the cross section could be mistaken for a front 

illum<strong>in</strong>ated sensor. Closer <strong>in</strong>spection reveals the 

ultrath<strong>in</strong> BSI sensor substrate bonded to a silicon 

carrier wafer, and the absence of a lower glass 

support. X<strong>in</strong>tec’s WL-CSP BSI version is only 570 

µm thick, a thickness reduction of about 0.13 mm 

compared to the front illum<strong>in</strong>ated device. 

Figure 2 shows a detailed view of the “T” contact 

modified for use <strong>in</strong> the BSI configuration. As it 

turns out, the philosophy of extend<strong>in</strong>g the die 

Figure 2 X<strong>in</strong>tec WL-CSP for BSI – Cross Section Detail 

13



TSV <strong>in</strong>tegration <strong>in</strong> their first BSI sensor. As before, an epoxy is used both to 

attach a front glass to the light receiv<strong>in</strong>g side of the sensor, and also as part of 

the redistribution layer build up. 

While arguably not as elegant as TSVs, the ShellOP packag<strong>in</strong>g provides 

nearly the same advantages, and has proven to be a highly manufacturable 

approach for 200 mm CIS wafers. For now, OmniVision/TSMC are happy to 

not add TSV <strong>in</strong>tegration costs to the already significant <strong>in</strong>vestment it took 

to get BSI <strong>in</strong>to mass production. It is worth mention<strong>in</strong>g that the real world 

examples are a snapshot of current production. TSMC developed its TSV 

technology <strong>in</strong> parallel, but did not <strong>in</strong>sert it <strong>in</strong>to production, <strong>in</strong> part because 

of mechanical stress issues impact<strong>in</strong>g wafer yield. TSMC estimates a 5% to 

15% gross die per wafer yield <strong>in</strong>crease (compared to exist<strong>in</strong>g sidewall CSP) 

is possible through TSV <strong>in</strong>tegration. The sensor area reduction comes from 

elim<strong>in</strong>at<strong>in</strong>g the lateral extensions and mov<strong>in</strong>g the circuitry under the pads 

(CUP), form<strong>in</strong>g a vertical <strong>in</strong>terconnect. 

Look<strong>in</strong>g at the competitive landscape, the simplest option was executed by 

Sony, who was first to market with a SOI-based BSI sensor. The relatively 

relaxed form factor constra<strong>in</strong>ts of its camcorder CIS enabled a simple 

backside wire bond<strong>in</strong>g approach. While effective for the application, this 

approach would not be an option for a camera phone module. With<strong>in</strong> the 

realm of camera phone modules, Chipworks has analyzed front illum<strong>in</strong>ated 

image sensors us<strong>in</strong>g TSVs fabricated by Toshiba and STMicroelectronics. 

Both companies are <strong>in</strong> BSI development, and will likely go straight to BSI + 

TSV. Several other CIS companies have published papers and/or have been 

awarded patents for both BSI and TSV implementations. One th<strong>in</strong>g is certa<strong>in</strong>: 

to vary<strong>in</strong>g degrees all CIS IDMs and foundries will be forced to evolve their 

packag<strong>in</strong>g solutions. TSVs may not be a necessity at the moment, but <strong>in</strong> the 

quest for a 3D <strong>in</strong>tegrated imager, their <strong>in</strong>tegration seems <strong>in</strong>evitable. 

Lithography for 3D-ICs and CMOS image sensors 

Wafer-to-wafer and chip-to-wafer bond<strong>in</strong>g 

www.chipworks.com 

Temporary bond<strong>in</strong>g and debond<strong>in</strong>g for th<strong>in</strong> wafer 

process<strong>in</strong>g 

Ray Fonta<strong>in</strong>e has been a process analyst at Chipworks s<strong>in</strong>ce 

2001, specializ<strong>in</strong>g <strong>in</strong> image sensors. He has authored and 

technically reviewed numerous image sensor process review 

(IPR) reports. 

Chipworks is the recognized leader <strong>in</strong> reverse eng<strong>in</strong>eer<strong>in</strong>g and patent 

<strong>in</strong>fr<strong>in</strong>gement analysis of semiconductors and electronic systems. The 

company’s ability to analyze the circuitry and physical composition of 

these systems makes them a key partner <strong>in</strong> the success of the world’s 

largest semiconductor and microelectronics companies. Intellectual 

property groups and their legal counsel trust Chipworks for success <strong>in</strong> 

patent licens<strong>in</strong>g and litigation – earn<strong>in</strong>g hundreds of millions of dollars 

<strong>in</strong> patent licenses and sav<strong>in</strong>g as much <strong>in</strong> royalty payments. Research & 

Development and Product Management rely on Chipworks for success 

<strong>in</strong> new product design and launch, sav<strong>in</strong>g hundreds of millions of dollars 

<strong>in</strong> design and earn<strong>in</strong>g even more through superior product design and 

faster launches. Headquartered <strong>in</strong> Canada, Chipworks ma<strong>in</strong>ta<strong>in</strong>s offices 

<strong>in</strong> the USA, Japan, Korea, and Taiwan. 

14



IPDiA 

Lead<strong>in</strong>g Innovation <strong>in</strong> Silicon solution for 50 years 

Silicon <strong>in</strong>terposer for 

packag<strong>in</strong>g 

Advanced Silicon Interposer with 3D TSVs and 

built-<strong>in</strong> capacitors, resistors, <strong>in</strong>ductors, ESD 

diodes 

Passive components 

Network 

Silicon capacitor network 

Custom Passive network 

Silicon Passive 

components 

Embedded Silicon capacitors 

Low profile Silicon capacitors 

High stability Silicon capacitors 

Wire Bond<strong>in</strong>g Silicon capacitors 

Couplers 

Baluns/Transformers 

Splitters 

Filters 

Diplexers / Duplexers 

HB LED TVS diodes 

HB LED Submounts 

Please come and visit our latest 

products on our website 

www.ipdia.com 

15



A N A L Y S T C O R N E R 

<strong>WLCSP</strong> quietly edges <strong>in</strong>to #1 position 

Yole analyst Jean-Marc Yannou provides a ‘primer’ on wafer-level packag<strong>in</strong>g trends. 

Wafer-level chip-scale packages (<strong>WLCSP</strong>s) 

comprise only about 6% of all ICs, yet 

quietly became the IC <strong>in</strong>dustry’s most 

popular type of package <strong>in</strong> 2009. This just goes to 

show how many packag<strong>in</strong>g options are out there, 

Yannou says, but also proves that <strong>WLCSP</strong> has f<strong>in</strong>ally 

established itself with<strong>in</strong> the <strong>in</strong>dustry. <strong>WLCSP</strong>s are 

now the fastest-grow<strong>in</strong>g package on the market, on 

target to claim 8.3% of the entire market by 2013. 

Background 

Wafer-level packages (WLPs) are created through 

a set of techniques of wafer-level-based assembly 

operations. This can apply to a variety of process 

flows for different purposes. The most common form 

of these process flows is the <strong>WLCSP</strong>. 

There are several emerg<strong>in</strong>g <strong>WLCSP</strong> 

technologies, which encompasses 3D 

ICs, MEMS devices, and fan-out WLPs. 

Silicon <strong>in</strong>terposers are also emerg<strong>in</strong>g as 

an enabler for 3D stack<strong>in</strong>g. 

Difference between ‘fan-<strong>in</strong>’ and ‘fanout’ 

The well-established <strong>WLCSP</strong>s, 

commonly known as “fan-<strong>in</strong>,” are on a 

R&D track of their own. There are still 

<strong>in</strong>novations be<strong>in</strong>g made, such as try<strong>in</strong>g 

to extend the maximum array size of 

<strong>WLCSP</strong>s with reliability. “<strong>WLCSP</strong> is 

limited to small-sized devices because of reliability; 

the thermal mismatch between the device and PCB 

is a serious problem, s<strong>in</strong>ce the PCB contracts and 

expands 5x faster with temperature than silicon,” 

expla<strong>in</strong>s Yannou. “When you have a direct silicon 

bond<strong>in</strong>g on the PCB, such as with <strong>WLCSP</strong>, you 

want to keep the device as small as possible so the 

outer bumps won’t move too much. The greater the 

Jean-Marc Yannou, 

Project Manager, 

Advanced Packag<strong>in</strong>g 

& IPDs, 

Yole Développement 

maximum distance between two bumps, the more 

difficult it is to ensure reliability, because thermal 

cycl<strong>in</strong>g deforms the bumps. This is known as ‘solder 

fatigue.’ New dielectric materials and solder alloys 

and <strong>in</strong>creas<strong>in</strong>gly <strong>in</strong>novative structures are help<strong>in</strong>g to 

solve it, though.” 

<strong>Fan</strong>-out <strong>WLCSP</strong>s are relatively new, and based on 

the pr<strong>in</strong>ciples of wafer reconstitution with known good 

die, and then wafer mold<strong>in</strong>g and redistribution. No 

package substrate and, consequently, no so-called 

first-<strong>in</strong>terconnect bump<strong>in</strong>g are required because the 

package is essentially built on top of a reconstituted 

wafer. There’s a lot of <strong>in</strong>dustry <strong>in</strong>terest <strong>in</strong> this type of 

package, Yannou notes. 

Chip embedd<strong>in</strong>g <strong>in</strong> lam<strong>in</strong>ate 

substrates 

Due to observed packag<strong>in</strong>g yield issues, 

Yannou believes chip embedd<strong>in</strong>g or 

embedded ICs <strong>in</strong> lam<strong>in</strong>ated substrates 

won’t target <strong>in</strong>tegration of ICs <strong>in</strong> 

motherboards or <strong>in</strong> complex modules 

or system-<strong>in</strong>-packages (SiPs), although 

it’s now considered an alternative to 

provide “near CSP fan-out packages” 

with a wafer-level type of ball<strong>in</strong>g for 

s<strong>in</strong>gle packaged IC-while wait<strong>in</strong>g for 

assembly yields to stabilize. 

Many substrate manufacturers are 

pursu<strong>in</strong>g this new market opportunity to 

ga<strong>in</strong> even a small portion of the $30B semiconductor 

packag<strong>in</strong>g <strong>in</strong>dustry. This move isn’t an obvious one 

to make, Yannou says, because it completely shifts 

their bus<strong>in</strong>ess models. 

“Trust must be built for foundries and fabless 

semiconductor players to rely on PCB players to 

package their valuable ICs,” he notes. “A bridg<strong>in</strong>g 

<strong>in</strong>frastructure is also needed between the wafers and 

‘<strong>Fan</strong>-In’ WLP penetration rate <strong>in</strong>to overall IC Packag<strong>in</strong>g (In Units) 

PCBs to provide for redistribution and <strong>in</strong>terconnect 

between both. Also, a few high-volume lead 

applications are needed to prove the capabilities 

of this technology with good yields and acceptable 

reliability.” 

Silicon <strong>in</strong>terposers 

Many <strong>in</strong>dustry players are consider<strong>in</strong>g us<strong>in</strong>g silicon 

<strong>in</strong>terposers, which are substrates made of silicon 

with f<strong>in</strong>e-pitch geometries obta<strong>in</strong>ed with the usual 

silicon process<strong>in</strong>g techniques. And now, thanks to 

TSVs, these substrates can be made <strong>in</strong> 3D like any 

other PCB. But Yannou says that the cost is 5 to 10x 

per surface area more than a regular organic PCB. 

History/Timel<strong>in</strong>e 

Back <strong>in</strong> 2000, when <strong>WLCSP</strong> began production, it 

was almost exclusively used <strong>in</strong> <strong>in</strong>tegrated passive 

devices (IPDs) for EDS/EMI <strong>in</strong>terface condition<strong>in</strong>g on 

6-<strong>in</strong>. wafers, and most of its production has rema<strong>in</strong>ed 

on 6-<strong>in</strong>. wafers. “This is captive production,” notes 

Yannou. 

By around 2005, <strong>WLCSP</strong> spread to other analog 

functions such as DC/DC converters, driver ICs 

for displays, LEDs, audio codecs, amplifier, etc., 

ma<strong>in</strong>ly on 6-<strong>in</strong>. and 8-<strong>in</strong>. wafers. While some of it is 

packaged <strong>in</strong>ternally by IDMs, accord<strong>in</strong>g to Yannou, 

most of it is outsourced. 

More recently, CMOS production started us<strong>in</strong>g 

<strong>WLCSP</strong>. This is primarily for digital+RF systemon-chips 

(SoCs) used <strong>in</strong> connectivity <strong>in</strong> the form 

of Bluetooth, WiFi, GPS, etc. “These are 8-<strong>in</strong>. and 

12-<strong>in</strong>. wafers,” Yannou po<strong>in</strong>ts out. “This trend was 

driven by fabless companies like CSR, which weren’t 

bound to any production l<strong>in</strong>es and the need to 

amortize them as a way to differentiate themselves 

from the competition. Integrated companies such 

as STMicroelectronics kept lagg<strong>in</strong>g beh<strong>in</strong>d because 

they had broad TFBGA capacity.” Due to the grow<strong>in</strong>g 

demand, Yannou is already see<strong>in</strong>g what appears to 

be a capacity shortage on 12-<strong>in</strong>. <strong>WLCSP</strong> service 

production <strong>in</strong> 2010. 

Cost no longer a ‘roadblock’ 

Size and m<strong>in</strong>iaturization, as well as performance, are 

the historic market drivers for <strong>WLCSP</strong>, Yannou notes. 

But the cost of fan-<strong>in</strong> <strong>WLCSP</strong> is no longer a roadblock 

to high-volume applications. Nokia paved the way, 

but Tier 2 handset manufacturers recently started 

to buy and mount <strong>WLCSP</strong> solutions on their boards. 

Source: Yole Développement, WLP report, 2009 

Decreas<strong>in</strong>g costs are help<strong>in</strong>g make this a 

ma<strong>in</strong>stream platform now, he says. “It took about 10 

years to amortize the equipment,” he expla<strong>in</strong>s. “The 

first factories to get <strong>in</strong>to WLP have amortized their 

loans and are now see<strong>in</strong>g more competition than 

ever. Many companies are propos<strong>in</strong>g WL services 

they weren’t previously offer<strong>in</strong>g. This competition is 

16



Focus on WLP <strong>in</strong> Handset Application 

Source: Yole Développement, WLP report, 2009 

such that the marg<strong>in</strong>s are lower for OSATs. On the 

other hand, however, it benefits the IDMs and other 

customers, so it makes <strong>WLCSP</strong> truly competitive 

with respect to other packages like QFNs, SOTs, and 

smaller BGAs like TFBGA.” 

Yannou believes cost is com<strong>in</strong>g down for 6-<strong>in</strong>. and 

8-<strong>in</strong>. wafers, but not much yet for 12-<strong>in</strong>. wafers, which 

still have rather high marg<strong>in</strong>s. 

“The cost of a simple <strong>WLCSP</strong> (or fan-<strong>in</strong> package) is 

<strong>in</strong> the range of 15 to 40¢ per p<strong>in</strong>. This is the cost 

for high-volume manufactur<strong>in</strong>g of more than 100,000 

units per month,” he says. “And that price doesn’t 

<strong>in</strong>clude f<strong>in</strong>al test. The reason why this range is quite 

wide is based on several factors. One is that you 

can have different I/O densities. The most common 

one is 0.5mm, but it now goes down to 0.4mm, or 

even 0.3mm pitch, which means you can place 

more I/Os per surface area. And because this is 

a wafer batch type of operation, the price per p<strong>in</strong> 

will be lower with higher I/O density. On the other 

hand, the total cost of the package solution isn’t 

necessarily lower-that’s an important po<strong>in</strong>t. It’s not 

necessarily lower just because you shift to a smaller 

pitch, because this means a higher-cost PCB for the 

customer. So the cost per p<strong>in</strong> has been proposed by 

the OSAT because the range I mentioned is what 

an IDM will pay to get ICs packaged by the OSAT. 

It’s a cost marg<strong>in</strong>, a price basically. For an IDM with 

a smaller pitch, for example, it’ll be cheaper, but for 

the customer of the IDM (the OEM), go<strong>in</strong>g to smaller 

pitches isn’t cheaper because they have to pay more 

for higher-density PCBs, which are expensive.” 

Another parameter Yannou sees as very important 

<strong>in</strong> the cost structure of <strong>WLCSP</strong> is the number of 

layers <strong>in</strong> the redistribution. It’s usually one or two; <strong>in</strong> 

“… The cost of fan-<strong>in</strong> <strong>WLCSP</strong> is no longer a roadblock to 

high-volume applications… “ says Jean-Marc Yannou, Project 

Manager at Yole Développement 

more than 90% of cases it’s one. That’s why most 

packages are <strong>in</strong> the lower end of that cost range. The 

actual cost of fan-<strong>in</strong> WLP is more <strong>in</strong> the range of 15 to 

25¢ per p<strong>in</strong>, he says. There are other options that add 

to the cost structure, such as deposit<strong>in</strong>g a backside 

protection on the wafer so that after s<strong>in</strong>gulation it’s 

protected with an epoxy-type of res<strong>in</strong>. 

“And of course yields are very important too, because 

one of the biggest drawbacks of this package is 

that the work is done at wafer-level, so noth<strong>in</strong>g is 

tested before packag<strong>in</strong>g,” he expla<strong>in</strong>s. “For all other 

package platforms, the units are s<strong>in</strong>gulated prior to 

packag<strong>in</strong>g. With WLPs, you pay at the wafer-level 

whether the unit is good or scrap. So you need to get 

good yields on your device wafer to get a lower price 

per p<strong>in</strong> <strong>in</strong> the end.” 

Emerg<strong>in</strong>g applications 

WLP can address essentially all ICs with<strong>in</strong> handsets, 

except basebands, CPU/GPU module, and memories. 

Two key new applications are laptops and netbooks. 

“These use TSVs for CMOS image sensors, which is 

another form of WLP that’s becom<strong>in</strong>g very popular 

as well. And MEMS packag<strong>in</strong>g is encompass<strong>in</strong>g 

WLP more and more, and we’re see<strong>in</strong>g a more than 

40% compound annual growth rate (CAGR) for 

MEMS packag<strong>in</strong>g, so that’s another good growth 

area. New WLP devices <strong>in</strong> automotive and <strong>in</strong>dustrial 

applications for ICs are another strong growth area, 

as well as MEMS and sensors, and we’ll likely see 

others,” Yannou predicts. 

Yole plans to release dedicated reports on embedded 

WLP and fan-out WLP later this year, as well as one 

on silicon <strong>in</strong>terposers. 

Jean-Marc Yannou (yannou@yole.fr) 

Jean-Marc Yannou is a technology and market 

expert <strong>in</strong> the fields of advanced packag<strong>in</strong>g and 

IPDs at Yole Devéloppement. He has 15 years’ 

experience <strong>in</strong> the semiconductor <strong>in</strong>dustry, and has 

worked at TI and Philips (then NXP). 

17



T O P 3 

IPDiA opens multi-parties 3D TSV Silicon Interposer Program 

From page 1 

available with<strong>in</strong> a very short leadtime for applications 

such as: <strong>in</strong>terposer with System <strong>in</strong> Package 

(SiP), Wafer Level Package (WLP), <strong>in</strong>terposer for 

Submount, die stack<strong>in</strong>g for volume constra<strong>in</strong>ed 

applications, HB LED packag<strong>in</strong>g platform. 

Leader <strong>in</strong> 3D etch<strong>in</strong>g technology, IPDiA, a French 

company, has been develop<strong>in</strong>g TSV s<strong>in</strong>ce 2005 

with the follow<strong>in</strong>g key features: through silicon via 

with low series resistance (< 10 mOhm), <strong>in</strong>terposer 

with f<strong>in</strong>e pitch (125 µm), low ohmic substrate for 

silicon <strong>in</strong>terposer / High ohmic substrate for silicon 

<strong>in</strong>terposer with 3D passive <strong>in</strong>tegration, 2 Cu layers 

on front side and 1 Cu layer on back side with 

passivation, maximum allowed current / Via: 100 mA. 

There will be two opportunities to jo<strong>in</strong> and share the 

MPW: 

- The first before end February 2010 based on 

a Silicon Interposer specification (specification 

available on request) 

- The second based on a Silicon Interposer with 3D 

Passive <strong>in</strong>tegration before end May 2010. 

www.ipdia.com 

The new device features I2C compatibility and 

uses a small and highly reliable WL-CSP (Wafer 

Level-Chip Size Package). To ensure low power 

consumption this sensor <strong>in</strong>cludes an auto-sleep 

function that automatically switches the detector to 

standby after a detection event. Another attractive 

feature of these devices is the ability to use leadfree 

reflow solder<strong>in</strong>g, which improves the cost and 

speed of the manufactur<strong>in</strong>g process. 

The new devices compact size (1.18 x 1.68 x 0.58 

mm) and simplicity of <strong>in</strong>tegration with products 

Silicon <strong>in</strong>terposer with TSV 

(Source: Traviata project, IPDiA) 

Hamamatsu Photonics presents new Photo sensor <strong>in</strong> 3D WLP package 

Hamamatsu Photonics <strong>in</strong>troduce a new RGB colour sensor Photo IC component which is now packaged <strong>in</strong> a <strong>WLCSP</strong> 

package. To access to the electrical contact through the backside of the wafer, 3D TSV <strong>in</strong>terconnects have been realized. 

Hamamatsu - Photo sensor IC is now packaged 

<strong>in</strong> a <strong>WLCSP</strong> 

CMOS Image Sensors 

technologies & Markets - 2010 Report 

implement<strong>in</strong>g the I2C protocol makes them ideal for 

LCD backlight and RGB-LED brightness adjustment 

<strong>in</strong> flat panel televisions and mobile phones. 

Hamamatsu Photonics are a $1 billion photonics 

company supply<strong>in</strong>g numerous opto-electronic 

components <strong>in</strong>to the automotive market, ma<strong>in</strong>ly to 

Tier 1 vendors. The company production facilities 

are set-up to meet the specific quality requirements 

of the automotive <strong>in</strong>dustry, such as TS 16949. 

www.eetimes.eu 

MaRKEt tREnDs 

Disruptive technologies pave the way to the future of digital imag<strong>in</strong>g <strong>in</strong>dustry! 

“… the reason why we are now releas<strong>in</strong>g the first report on cMos 

image sensor <strong>in</strong>dustry is that we feel that we are at an historic 

turn<strong>in</strong>g po<strong>in</strong>t of this young, but still matur<strong>in</strong>g <strong>in</strong>dustry. …” says 

Jérôme Baron, technology & Market analyst, MEMs & advanced 

Packag<strong>in</strong>g. 

18 

KEY FEatuREs 

the objectives of this first report are to provide: 

• Market data on CMOS image sensor key market metrics & 

dynamics: cMos image sensor unit shipments, revenues and 

wafer production by application, market shares with detailed 

breakdown for each player… 

• Key technical <strong>in</strong>sight about future technology trends & challenges: 

from BsI and other front-end technologies evolution to WLc 

realization with wafer level optics, packag<strong>in</strong>g / assembly & test… 

• A deep understand<strong>in</strong>g of CIS value cha<strong>in</strong>, <strong>in</strong>frastructure & players 




CMOS Image Sensors Technology Drivers: 

New Challenges to face ! 

• BSI (Backside illum<strong>in</strong>ation) 

• New color filters, AR coat<strong>in</strong>gs 

• Pixel isolation, substrate techno 

Front-end 

Packag<strong>in</strong>g / Assembly 

• WLP (Wafer Level packag<strong>in</strong>g) 

• 3D TSV <strong>in</strong>terconnects 

• Wafer Level Camera & Mold<strong>in</strong>g 

• HDR (Hide Dynamic Range) 

• eDoF (Extended Depth of Focus) 

• NIR (Near IR Capability) 

Software / Design 

Optical module 

• WLO (Wafer Level Optics) 

• Image stabilization (MEMS Inertial) 

• Auto-focus (Piezo, liquid lense, MEMS…) 



Y O L E D É V E L O P P E M E N T



Samsung presents new 3D TSV Packag<strong>in</strong>g Roadmap 

It is not a secret that Samsung is actively prepar<strong>in</strong>g for 3D <strong>in</strong>tegration. The Korean electronic giant recently updated its 

packag<strong>in</strong>g roadmap, <strong>in</strong>clud<strong>in</strong>g recent advancements <strong>in</strong> the commercialization of 3D TSV <strong>in</strong>terconnects. 

Everyth<strong>in</strong>g really started on April 2006 and 

later on April 2007 when Dr Chang-Gyu - 

Samsung’s Hwang President & CEO - announced 

the company <strong>in</strong>tention to commercialize 3D TSV 

stacked NAND Flash memory and 3D TSV stacked 

DRAM memory. 

Talk<strong>in</strong>g about 3D silicon <strong>in</strong>tegration at that time, Dr 

Chang even said «we are at the doorstep of the 

largest shift <strong>in</strong> the semiconductor <strong>in</strong>dustry ever, 

one that will dwarf the PC and even the consumer 

electronics era». 

Dr Chang cont<strong>in</strong>ued say<strong>in</strong>g that «it is generally 

perceived that sub-25 nanometers is the limit to 

maximiz<strong>in</strong>g the efficiency of the silicon base». But, 

Dr. Hwang emphasized that alternate technologies 

can counter this apparent dead-end <strong>in</strong> ultraf<strong>in</strong>e 

process technology such as 3D structure 

technology and 3D stack<strong>in</strong>g technology 

Samsung 3D Packag<strong>in</strong>g roadmap 

S<strong>in</strong>ce then, much th<strong>in</strong>gs have happened as the 

lead<strong>in</strong>g semiconductor company re-organized and 

recentered around 3 major bus<strong>in</strong>esses: memories 

(DRAM, Flash, NVM ..), CMOS image sensors and 

Logic LSI division. And it considerely impacted 

the <strong>in</strong>ternal organization of the company’s R&D 

program and efforts to commercialize 3D TSV 

technology. 

F<strong>in</strong>ally, the company announced late 2008 that 

«Via Last» TSV / WLP manufactured at the 

backside of the chips will be implemented first <strong>in</strong>to 

CMOS image sensors, with similar approach that 

Omnivion, Toshiba, Micron Apt<strong>in</strong>a and STMicro 

did. 

On the new roadmap presented above, Samsung 

clearly show a strong <strong>in</strong>terest for <strong>in</strong>troduc<strong>in</strong>g 

3D <strong>in</strong>to logic+memory and logic+logic stack<strong>in</strong>g 

applications. These two last configurations are 

now the ma<strong>in</strong> driv<strong>in</strong>g forces to implement 3D <strong>in</strong>to 

<strong>next</strong> generation PoP (Package on Package) and 

SiP (System <strong>in</strong> Package) applications such as 

mobile processors, CPU and high performance 

ASICs. The ma<strong>in</strong> drivers for 3D here are cost and 

performance. 

If the company expect to ship <strong>next</strong> 3D products 

<strong>in</strong> the 2012-2013 time frame, challenges are still 

present and numerous: namely, they <strong>in</strong>clude 

300mm 3D TSV <strong>in</strong>frastructure availability, process 

flow strategy and scenarios selection (Via first 

/ Middle / Last / After Bond<strong>in</strong>g), Test (with the 

possibility to stack only KGD, build BIST and 

JTAG features, develop doble-side probe station 

or contact-less test technologies, use <strong>in</strong>terconnect 

redondancies) and I/O <strong>in</strong>terfaces specifications 

(such as design rules for electrical rout<strong>in</strong>g, 

mechanical bond<strong>in</strong>g and thermal dissipation). 

www.samsung.com 

19



HB LED & LED Packag<strong>in</strong>g 2009 

The HB LED & LED Packag<strong>in</strong>g market is a high-growth field <strong>in</strong> the semiconductor <strong>in</strong>dustry. 

HB LED & LED Packag<strong>in</strong>g 2009 highlights the ma<strong>in</strong> technical 

challenges, current solutions and future trends. It also <strong>in</strong>cludes 

market analysis on process, equipment, materials and services. 

COMPOUND SEMICONDUCTORS 

3 000 M$ 

2 500 M$ 

Cumulative market size for Die-attach, Interconnect, substrate 

and Phosphor <strong>in</strong> HB/UHB LED manufactur<strong>in</strong>g process 

KEY FEatuREs 

• Detailed process flow of LED packag<strong>in</strong>g (dic<strong>in</strong>g step, electrical 

<strong>in</strong>terconnect, Wafer Level Packag<strong>in</strong>g, encapsulation, substrates,…) 

• Market trends and figures for l<strong>in</strong>ked material and equipment 

(<strong>in</strong> million $, <strong>in</strong> number of units, ASP,…) 

• Key drivers for each technology & material <strong>in</strong> use 

• Supply cha<strong>in</strong> analysis: who is do<strong>in</strong>g what? 

Market size (M$) 

2 000 M$ 

1 500 M$ 

1 000 M$ 

500 M$ 

0 M$ 

2008 2009 2010 2011 2012 2013 2014 2015 

Who ShouLD buy thiS rEPort? 

• Equipment, material and chemical manufacturers to: 

- have a global view on ma<strong>in</strong> market metrics 

- identify new bus<strong>in</strong>ess opportunities 

- understand the value-proposition of your product <strong>in</strong> this market 

• LED makers: 

- Get an overview on the compet<strong>in</strong>g solutions 

- Learn and anticipate the future trends <strong>in</strong> LED packag<strong>in</strong>g 




(mm 3 ) 

10000 

1000 

100 

10 

0 

Volume of the © October 2009 

package 

Mold 

Top View 

Mold 

Side 

View 

Mold 

Top View 

+ heats<strong>in</strong>k 

Ceramic 

(AL 2 O 3 ) 

0.1 

0 1 10 

100 

Ceramic (AIN) 

+ heats<strong>in</strong>k 


Power 


(W) 


About Yole Développement 

Created <strong>in</strong> 1998, Yole Développement is a market research and strategy consult<strong>in</strong>g firm analyz<strong>in</strong>g emerg<strong>in</strong>g applications us<strong>in</strong>g silicon and micro 

manufactur<strong>in</strong>g. With 20 full time analysts track<strong>in</strong>g MEMS, Microfluidics, Compound Semiconductor, Power Electronics, Photovoltaic, Advanced 

Packag<strong>in</strong>g and Nanomaterials, Yole Développement supports companies and <strong>in</strong>vestors worldwide to help them understand markets and follow tech 

nology trends. 

SERVICES 

• Market research and market data 

• Technology analysis 

• Market workshop 

• Strategy consult<strong>in</strong>g 

• M&A support, fund rais<strong>in</strong>g and due diligence through Yole F<strong>in</strong>ance 

CONTACTS 

For more <strong>in</strong>formation about : 

• Yole Développement: Jean-Christophe Eloy (eloy@yole.fr) 

• Publications: David Jourdan (jourdan@yole.fr) 

• Media activities: Sandr<strong>in</strong>e Leroy (leroy@yole.fr) 

PUBLICATIONS 

• Collection of market & technology reports 

• Players & technology databases and market data 

• Manufactur<strong>in</strong>g cost simulation tools 

• Component reverse cost<strong>in</strong>g analysis 

More <strong>in</strong>formation on Yole.fr <strong>in</strong> reports section 

MEDIA 

• Critical news, Bi-weekly: Micronews, the magaz<strong>in</strong>e 

• In-depth analysis & Quarterly Technology Magaz<strong>in</strong>es: MEMS Trends Magaz<strong>in</strong>e – 3D Packag<strong>in</strong>g Magaz<strong>in</strong>e – PV Manufactur<strong>in</strong>g Magaz<strong>in</strong>e 

• Onl<strong>in</strong>e disruptive technologies website: www.i-micronews.com 

• Exclusive Webcasts 

• Live event with Market Brief<strong>in</strong>gs 

Editorial Staff 

Manag<strong>in</strong>g Editor: Jean-Christophe Eloy - Editor <strong>in</strong> chief: Dr Eric Mounier 

Editors: Jérôme Baron, Jean-Marc Yannou, Paula Doe 

PR & Media Manager: Sandr<strong>in</strong>e Leroy - Assistant: Camille Favre - Production: Rouge Amande 

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Fan-in WLCSP matures, what's next? IMT on the role ... - I-Micronews

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