3M & SUSS announce agreement on temporary wafer ... - I-Micronews

N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s 

I S S U E N ° 1 1 J U L Y 2 0 0 9 

E D I T O R I A L N E W S 

IPD, 

a new report 

from Yole 

Développement 

Packaging is today driving a lot of 

innovating developments. 

At Yole, we keep analyzing advanced 

packaging technologies since a few 

years now and we recently add a new 

report to our portfolio: IPD 2009, the 

first study on thin film integrated 

passive and active devices. 

2 

<strong>3M</strong> & <strong>SUSS</strong> <strong>announce</strong> <strong>agreement</strong> on temporary 

wafer bonding technology to enable 3-D IC 

semiconductors 

<strong>3M</strong>, a leading supplier of advanced materials to the semiconductor industry, and 

<strong>SUSS</strong> MicroTec, a leading supplier of semiconductor processing equipment, 

today <strong>announce</strong>d an <strong>agreement</strong> to expand access to <strong>3M</strong> Wafer Support System 

(WSS) equipment for temporary wafer bonding of ultrathin wafers required for 

3-D packaging 

As part of this non-exclusive <strong>agreement</strong>, 

<strong>SUSS</strong> MicroTec becomes an authorized 

equipment supplier for the <strong>3M</strong> WSS and will 

manufacture and sell XBC300 and CBC300 wafer 

bonders configured to use <strong>3M</strong>’s WSS materials 

including <strong>3M</strong> Liquid UV-Curable Adhesive and Light- 

To-Heat Conversion coating. Under the <strong>agreement</strong>, 

both companies will work closely to address 

customer demands for high-performance process 

solutions that support high-volume manufacturing 

with a competitive cost of ownership. <strong>3M</strong> WSS uses 

processes and materials for temporary wafer 

bonding to support wafer thinning and processing of 

ultra thin wafers for 3-D packaging. <strong>3M</strong>’s innovative 

use of a UV-curable adhesive for wafer bonding to 

glass carriers provides robust wafer 

support throughout wafer grinding. 

15 

N E W S 

Oki Semiconductor develops world’s smallest 

video decoder in a WL-CSP package 

The compact dimension of the LSI is achieved 

by using a single power supply (1.8V) and an 

ultra-compact 3.8 x 3.7mm W-CSP (Wafer 

Level Chip Scale Package), which is 60% smaller 

than conventional mold packages. This LSI is 

guaranteed to operate across a temperature range of 

-40 to +85°C, well beyond the requirements for 

typical household applications. 

The product helps reduce the number of parts 

required and reduces the size of PCBs used in 

security camera systems and vehicle-mounted 

camera systems, as well as decreasing costs. Sample 

shipments are scheduled for June 2009 and a fullscale 

product launch is scheduled for September 

2009. 

14 

N E W S 

Alchimer raises $10 million to expand global 

customer support and broaden new IP 

development 

Funding will help provider of innovative wet deposition processes for Through- 

Silicon Via 3D-Packaging 

eG ViaCoat gives 90% Step coverage of dense 5 x 50µm TSVs 

Alchimer S.A., a leading provider of costsaving 

wet deposition processes for 

interconnections in advanced 3D-packaging 

applications, <strong>announce</strong>d today that it has raised an 

additional $10 million in new financing to expand 

customer-support programs and pursue new IP 

development. Alchimer’s D round of funding includes 

both previous and new investors, including AGF, CEA 

Investissement and Emertec Gestion. 

15 

C O N T E N T S 

E V E N T S 2 

A N A L Y S I S 2 

• 3D Integration for wireless products: 

an industrial perspective 

C O M P A N Y P R O F I L E 6 

• The wafer level camera Juggernaut Novel 

technology, supply chain innovation and 

commercial pressures drive rapid adoption 

• IPD – 2009 Report - Technologies, Applications, 

Markets & Players 

• SET: Die/Flip chip Bonders able to align and 

bond fragile components at 0.5 μm post bond 

accuracy 

N E W S 1 3 

• IBM fellow predicts end of Moore’s Law: 3-D is 

next viable path! 

• Texas Instruments gets a WL-CSP IC design 

win in latest Apple’s iPod shuffle 

• R3Logic is awarded key patent for 3D EDA 

tools 

• NXP to sell French fab in Caen: Spin-out of new 

3-D IC Company ahead 

Printed on recycled paper 

45, rue Sainte Geneviève 

69006 Lyon, France

J U L Y 2 0 0 9 i s s u e n ° 1 1 



E D I T O R I A L 

As you will discover in the article 

in this last issue of 3D 

Packaging newsletter, 

Integrated Passive Devices (IPD’s) 

are growing industry trend. 

They can be used as wafer-level 

packaged single chip solutions for 

interface conditioning, or they can be 

assembled with active IC’s in 

Systems-in-a-Package, or they can 

be used as package substrates or as 

system sub mounts. 

IPDs are also a nice example of a mix 

of technologies as both IC and MEMS 

worlds meet here, to offer higher 

performance with high integration. 

Our report is the first covering technology 

review for thin film IPD, description 

of the applications, market forecasts, 

roadmaps & manufacturing 

challenges, description of the supply 

chain with players profiles. 

Enjoy reading our newsletter! 

Dr Eric MOUNIER 

Editor in chief 

mounier@yole.fr 

E V E N T S 

• Semicon West, 

July 14-17, San Francisco, CA, USA 

• Semicon Europa, 

October 6-8, Dresden, Germany 

• 3-D Architectures for 

Semiconductor Integration and 

Packaging, This is SEMICON Europa. 

December 9 – 11, 2009, San Francisco, CA, 

USA 

A N A L Y S I S 

3D Integration for wireless products: an 

industrial perspective 

The mobile phone and wireless industries have been growing at a very fast pace 

in the last 10 years. With more than 1.2 billion phones sold in 2008, the wireless 

market has been one of the main contributors in driving the development of the 

most advanced semiconductor technologies. The computing power for portable 

devices is becoming mandatory to enable mobile internet browsing, mobile 

TV, and all increasing multimedia features. In that context, miniaturization and 

performance are the driving forces for silicon technology development. 

Following the ITRS roadmap with CMOS 

downscaling is the traditional way to proceed. 

But the R&D expenses to sustain such a 

roadmap are extremely selective. Only a few 

companies or consortia can afford it. That’s why 

advanced CMOS technology could start to be seen 

as a kind of commodity and integration with new 

solutions appears as a much stronger differentiator 

element. Packaging contributions in the final product 

gained in importance. Major improvements and 

progresses have been done lately and a new 

solution is gaining more and more importance: 3D 

Integration. 

3D Packaging 

Despite the recent buzz in the industry for a couple 

of months, 3D configurations are not new at all. In 

effect, 3D configurations at the packaging level have 

been 6–8 around OctOber, for years. In 2009 many teardowns Dresden, of Germany 

handsets, lot of 3D packages can be found. A stack 

of dice connect with wire bonds with is something europe’s very common technology 

for memories. Package over Package (PoP) Leaders and expand Your Opportunities 

Package in Package (PiP) is a configuration 

widespread in Infinite to combine Ways. the stack of memories on top 

of an application processor or digital baseband. At 

SEMICON Europa is the only event in Europe focused on 

the same time, 3D package solutions such as 

embedded connecting die in people laminate and or rebuilt companies wafer with such the as technologies 

Fan-Out and innovations Wafer Level making Packaging advanced (FO-WLP) microelectronics are and 

emerging. FO-WLP goal is to construct a package as 

related technologies possible. From device design to final 

small as possible to enable all the BGA balls to fit on 

it. The manufacturing, packaging is built no around other the event individual Europe known brings CIS. you better 

good face-to-face die and provides contact a way with to make customers the laminate and technology 

substrate vanish. FO-WLP improves signal integrity, 

partners than SEMICON Europa. 

shortens interconnects, reduces line/space for 

rerouting, and as a consequence, allows a reduction 

in the package See footprint. You at Infineon SeMIcON and Freescale europa 2009 

developed reGISter their own NOW: FO-WLP WWW.SeMIcONeurOpa.OrG 

technology 

respectively called eWLB TM and RCP TM . Lately, 

STMicroelectronics partnered with Infineon and 

STATS Chip Pac to develop the 2nd generation of 

eWLB TM , 3D-eWLB TM , and enable 2-sided and 

consequently, 3D configurations. 

3D at IC level using TSV 

All the configurations mentioned above are 3D at the 

packaging level. None of them uses TSV, which 

could allow “real” 3D at the IC level in some 

configurations. TSVs are nothing more than a techno 

brick that allows dice to interconnect on the vertical 

axis at the IC level. The impact of TSV is that these 

short interconnections could enable a new split of 

functions and new product partitioning. However, it 

is important to notice that TSV interconnections can 

be done at different levels and the impact on final 

applications is not the same. Either the TSV is done 

at the bond pad level or at the global interconnect 

level. 

At the bond pad level, TSV is done in a via last 

process in a wafer level packaging fab environment. 

The pitch of TSV is in the range of a bond pad pitch. 

Typical values from 50 to 150µ in term of pitch can 

be considered. An aspect ratio can reach 5:1 and 

filling is conformal or full. RLC electrical performances 

are better than wire bonds, except for the capacitance 

that may remain high. This type of TSV can be based 

on an improvement of technologies developed for 

At the global interconnect level, we consider TSV 

with higher aspect ratio done in foundry environment, 

preferably via middle (after FEOL but before BEOL) 

or first (before FEOL). TSV pitch is in the 10-20µ 

range with the aspect ratio ranging from 5:1 to 10:1 

Fig1 - FOWLP 1 side (left) , 2 sides (called 3D-eWLB, right) 

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J U L Y 2 0 0 9 i s s u e n ° 1 1 


Fig2 - From design to packaging: demonstration achieved between STMicroelectronics and CEA-LETI 

or even a bit more. For this category of TSV, dice are 

not only connected at bond pad level but also at the 

IP block or memory bank levels for instance. This 

type of TSV enables the achievement of structures 

with very short interconnections and good electrical 

performances. True heterogeneous integration is 

made possible and SoC–like features can be 

realized but using the third dimension and not only 

the x-y directions. Dice interconnected with this type 

of TSV are closer to SoC than SiP. For these 

reasons, 3D SoC is a very good term for this 

configuration. Figure 1 shows key demonstration 

achieve in STMicroelectronics with CEA-LETI. 

Complementarity of 3D packaging and 3D IC 

Except for some wafer-level chip-scale packages 

(WLCSP) or silicon interposer with TSV directly 

mounted on Printed Wiring Board (PWB) with a BGA 

balls, TSV is not a packaging solution by itself. TSV 

uses only “back-end world” skills such as bonding, 

fine pitch bumping, back grinding and thin wafer 

handling, for instance. In effect, final packaging is 

required to connect the device to the PWB. And due to 

assembly constraints, the choice of the final package 

solution could impact the entire TSV process flow. 

Fig3 - 3D IC TSV stack in 3D-eWLB (Courtesy of ST-Ericsson) 

This final packaging could be a BGA package, a Fan- 

Out WLP type, an embedded die in laminate, or other. 

Here, it is interesting to notice how complementary 

3D IC configurations with TSV and 3D packaging 

can be. In effect, 3D eWLB TM can enable designs to 

fully benefit from the 3D IC integration, and for 

instance, reduce the package footprint with more 

aggressive design rules than BGA packages. TSV is 

a new technology and 3D eWLB TM a new packaging 

technology as well. Only considering BGA-type 

packages for structures with TSV might be a wrong 

reasoning. Some constraints can even be relaxed 

by coupling 3D IC TSV with 3D advanced packaging 

and then the full benefits of the TSV can emerge. 

Issues such as thin wafer handling can, for instance, 

be simplified. 

3D Integration: Convergence of 

Architecture with Silicon & Package and 

Out of the box thinking required. 

3D IC TSV is the convergence of silicon and 

packaging with the design. New architectures can in 

effect be considered and achieved. In fact, new 

architectures have to be considered if cost 

effectiveness is to be reached. 

In order to fully benefit from 3D TSV and make this 

technology cost effective, 3D architecture needs to 

be considered at a very early stage. However, 

designers are facing a gap between TSV technology 

process and TSV system design. This gap is due to 

the fact that there is no clear TSV technology 

roadmap in the industry. With a scaling-based 

approach and a classical follow-up of Moore’s law, it 

was easier to focus the R&D efforts and predict the 

size and performance of a new techno node. With 

3D TSV, the industry is facing a new paradigm. 

Designers’ mentalities have to be modified and the 

former constraints of 2D have to be partially 

forgotten. 

Roadmaps exist, but are not necessarily very 

relevant. For this reason, many options can be 

considered, and process technologists do not know 

by themselves where to go and on what to focus. 

The only solution is to reinforce collaborations and 

discussions between the design community and the 

hardware technology community. A holistic approach 

is necessary to find the technology / design sweet 

spot and the application needs to drive developments. 

Application roadmap 

Applications that could use TSV and 3D remain a hot 

question. Only a few people have clear views on 

products that could use such innovations. Many 

niche markets would exist, for sure. However, when 

we think about core chipset components in wireless, 

the scope of applications tends to reduce. The 

following roadmap is based on ST-Ericsson’s and 

STMicroelectronics’ view and portfolio for wireless 

products (fig 2). Memory stacks with TSV such as 

DRAM are not mentioned as they are not part of the 

company business area anymore. Combinations of 

3D IC TSV with advanced packaging such as 3D 

eWLB TM are not detailed on the schematics. 

The first CMOS Imaging Sensors are now on the 

market and ramping up. The possibility to substitute 


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beginning and much more will be discovered and 

understood in up-coming years. The only thing to 

avoid with 3D Integration is to continue thinking 

based on the past experiences of downscaling. 

Applying Moore’s law based on scaling to a More 

than Moore approach such as 3D Integration TSV is 

not necessary at all. The application should help in 

the roadmap definition. 


Fig 4 - Application Roadmap for 3D integration in wireless products (Courtesy of ST-Ericsson) 

wires by connections coming from the backside of 

the die would gain them a reduction in the camera 

volume and its cost. However, in this example, we 

can’t speak about TSV enabling 3D configuration 

because, in fact, no chips are connected along the 

vertical axis. The top layer is only a glass carrier, not 

an active die; this can be called 2.5D but definitively 

not 3D. 

Power Amplifiers (PA) built in SOI are likely to use 

TSV technology in the future in order to improve 

performance and reduce die size. For PA, TSV is 

only used for parasitic and each is connected to a 

common ground on the metallized backside of the 

chip. Wires remain for I/O. In that case, a very low 

cost TSV technology is compulsory. Thermal 

dissipation improvement is foreseen as well. 

The first true 3D ICs using TSV are forecasted for 

2012. New partitioning of chips with IP in the best 

techno node will appear. Logic dice would be from 

different techno node generations (N generation, 

N+1, N+2…). A smart split of functions will be done 

in order to achieve the right cost/performance tradeoff 

with TSV as the new enabler. An intermediate 

step based on a silicon interposer for the bottom die, 

containing only routing and few functions, is likely to 

happen. It will help in bridging the gap toward 3D 

SoC and a full readiness of design tools. With 3D IC 

and TSV, new topics will need to be considered. 

Numbers of options in silicon wafers, such as the 

type of ESD protection and test strategy are a few. A 

key advantage of 3D IC for this scheme of integration 

is clearly the time reduction of critical IP development 

in an advanced techno node. With a smart 

partitioning, complexity will be reduced and no 

longer on the critical path. 

A memory / logic stack using TSV is a type of 

application the industry often refers to. The main 

reason for this is the increased bandwidth required 

by the final applications (driven by video features 

such as 1080p30 playback, 1080p30, 60, 120 

Camcorder, 3D gaming…). With a new memory / 

logic interface architecture, based for instance on a 

wide I/O approach, this bandwidth challenge might 

be overcome. Furthermore, this new wide I/O 

interface with parallel access to the memory will 

enable lower power consumption in the memory bus. 

For cellular phones, this bandwidth bottleneck might 

come after the Low Power DDR2 memory 

generation. However, many challenges are rising. 

Thermal management is definitively a critical point in 

this approach. In effect, the power dissipation of the 

logic die, typically an application processor or a 

digital baseband, can heat the memory directly 

stacked on top. As memories have a lower Tj than 

logic die (85°C or 105°C), the memory will receive 

too much heat and won’t work correctly. Power 

dissipation of the bottom die will be range from 1 to 3 

W from low to high end 3G platforms. 

Another main issue with the wide I/O memory is the 

standardization and supply chain. Most of the time, 

the memory and logic die will come from different 

companies. Standardization will be required to 

enable the final OEM integrator to source different 

memory types or any double sourcing. 

Conclusions 

Roadmaps will mature during the next few years as 

people begin to understand all the capabilities of 3D 

Integration. As of today, only the emerging part of the 

iceberg is visible. 3D thinking is only at its early 

It is crucial to differentiate 3D packaging and 3D at 

the IC level using TSV. TSV by itself is not a 

packaging technology apart from some few 

exceptions. Consequently, 3D TSV and 3D 

packaging do not have to be considered as 

competitors but more as complementary areas. In 

recent years, the semiconductor industry has 

expressed some growing interest in these ideas and 

put some significant efforts in allowing the 

emergence of these new breakthrough technologies. 

Still, some challenges remain ahead for a wide 

adoption. Most of them are cost, a shift in the design 

method paradigm, system co-design, new CAD 

tools, new architectures, and more new challenges. 

The 3D IC TSV combined with the 3D eWLB TM 

appears as the next wave for future integration and 

should initiate some new integration schemes. We 

expect to expand the innovation landscape through 

lower cost and better electrical and thermal 

performances enabled by new partitioning and 

architectures, higher flexibility, better integration with 

easier software implementation and a shorter time to 

market. 

Yann Guillou 

New Technology Marketing - ST-Ericsson 

Yann.Guillou@stericsson.com 

+33 476 58 58 77 

Yann Guillou is currently 

in charge of New 

Technology Marketing 

activities for the Wireless 

Multimedia Group of ST- 

Ericsson. His main interest is in 3D Integration 

and Advanced Packaging. He started his 

career at CEA-LETI before joining 

STMicroelectronics and successively worked 

at ST-NXP Wireless and ST-Ericsson. He 

holds a MSc degree in Materials and 

NanoTechnology from INSA (National 

Institute of Applied Sciences, France) and a 

Specialized Master in Management of 

Technology and Innovation from Grenoble 

Business School (France). 

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C O M P A N Y P R O F I L E 

The wafer level camera Juggernaut Novel technology, 

supply chain innovation and commercial pressures 

drive rapid adoption 

Wafer level cameras represent a tantalising opportunity to substantially decrease the cost and form factor of solid state 

camera modules. After many years of endeavour, successful integration of the technologies necessary to manufacture 

true wafer level cameras was <strong>announce</strong>d in 2007. While there is great potential for these cameras on mobile platforms, 

OEMs are reluctant to design-in product that is not commercially available and camera module manufacturers will not 

invest in the necessary manufacturing facilities when there is no demand. This article discuses the technical, supply chain 

and commercial challenges of wafer level camera technology and explains the background behind analysts prediction that 

by 2012 reflowable wafer level cameras will account for 30% of the 2bn camera modules manufactured annually. For Yole 

Développement, Giles Humpston & Bents Kidron from Tessera has highlighted what the trends, markets and challenges 

for WLC are. 

Yole Développement: Could you define 

what a wafer level camera is? 

Giles Humpston & Bents Kidron: Wafer level 

camera is “wafer level manufacture of all parts of a 

solid state camera that are then combined at the 

wafer level”. The final step of manufacture is wafer 

dicing, which frees complete and individual camera 

modules. Recently the technical issues to make 

wafer level cameras have all been solved and 

product <strong>announce</strong>ments appeared in 2007. 

However these first generation wafer level cameras 

are not manufactured according to the methodology 

suggested by the definition above. This is because it 

is perceived as uneconomic to do so. The issue is 

that the optical area of an imager die is very much 

smaller than the die area because of the other 

electronics each chip contains. The result is a 

mismatch in population between the lens wafers and 

the semiconductor wafers; a 200m diameter lens 

wafer being able to accommodate about 4 times as 

many lenses as an imager wafer containing VGA 

resolution die. There is also the issue of compound 

yield when mating a stack of optical components 

fabricated at the wafer level with a wafer containing 

imager die. In both cases the number of good optical 

die is less than the total number of die. 

Consequently it is economically more favourable to 

make the optical train at the wafer level, dice it into 

individual optical stacks then conduct die-to-wafer 

assembly to build camera modules. Dicing the 

populated semiconductor wafer yields completed 

camera modules, an example of which is shown in 

Figure 1. A slightly less rigorous definition of a wafer 

level camera that takes this reality into account is, 

“wafer level manufacture of all parts of a solid state 

camera that are combined while at least one part is 

at the wafer level”. 

YD: What are the advantages of WLC approach? 

GH & BK: The attractive attributes for wafer level 

cameras can be listed as follows: 

• Compact form factor. A VGA resolution wafer level 

camera can fit comfortably in a cube less than 2mm 

on a side and mega pixel cameras are insignificantly 

larger. 

Bents Kidron: at Tessera, Bents Kidron assumes ownership for all marketing and business 

development for all wafer level technologies in Tessera, including WLP (TSV), WLO (Wafer Level 

Optics), WLC (Wafer Level Camera). 

Fig 1 - Multi-level stack of optical parts manufactured at the wafer level using OptiML WLO technology and attached to an imager die housed in a SHELLCASE 

MVP wafer-level package that uses through silicon via interconnects. The result is a highly compact camera module with performance tailored for camera phones. 

Source: Tessera. 

• Low cost. Mechanical integration of a camera 

module in a cell phone costs several dollars. 

Reflowable wafer level cameras can be integrated 

at the same time as all the other surface mount 

components, making the sub-$1 VGA camera 

module a distinct possibility. 

• Improved reliability. Traditional camera modules 

are connected to the main PCB by a flexible circuit 

and miniature connector. Failure of these 

components is the primary cause of field returns of 

cell phones exhibiting camera faults. 

• Repeatable performance. Because all the parts of 

a wafer level camera are fabricated in parallel, they 

are virtually identical. The piece part variability is 

therefore reduced to a wafer basis and with many 

thousands of parts on a single wafer the distribution 

over the volume of the production run is much 

tighter than for discrete assembly. 

• Superior performance. Wafer level optics can be 

fabricated with lens profiles unachievable by other 

means. This means the lens designer has many 

more degrees of freedom to achieve the desired 

image quality (see Figure 2). 


Giles Humpston: Director, Research and Development, Tessera. Giles 

Humpston, Ph.D., serves as Director, Research and Development of Tessera. 

Dr. Humpston has spent his professional career working in the field of 

semiconductor packaging, initially for military applications and, more recently, 

for high volume consumer products. He is a metallurgist by profession and has 

a doctorate in alloy phase equilibria. Humpston is a cited inventor on more than 

75 patents and has co-authored several text books on metallic joining processes. 

His work and technical publications have been recognized by five international 

awards. Humpston’s current interests are packaging of solid state camera modules and product 

miniaturization through wafer level technologies. 

Combined, these benefits provided impetus to the 

endeavour necessary to convert the long held dream 

of the reflowable wafer level camera into a 

commercial reality. At the outset three barriers to 

widespread adoption of wafer level cameras were 

identified. They are: 

• Technology 

• Supply chain 

• Cost and competition 

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J U L Y 2 0 0 9 i s s u e n ° 1 1 



Fig 2 - Pictures of fruit taken, left, with a VGA resolution wafer level camera 

having a single optical element and, right, the 5MP camera on a production 

model N95 cell phone. The cost differential between these two cameras, 

which is larger than an order of magnitude, is not immediately apparent in 

the image quality. 

YD: What are the main technical 

challenges to make WLC today? Can you 

comment where the pain points are? 

GH & BK: The principal technical challenges to 

making wafer level cameras are how to manufacture 

suitable lenses, combine these with other essential 

parts like apertures and filters, and then align and 

assemble these in a manner that yields an integrated 

optical component. 

Wafer level lenses are all made by replication 

processes. While these are well known and 

understood and suitable equipment is available 

commercially, there is a major issue in that traditional 

optical polymers are wholly inadequate for wafer 

level camera optics. Key attributes are optical 

performance, mouldability and compatibility with the 

thermal excursion of the lead-free solder reflow 

cycle, typically 265°C for 2 minutes, x3 cycles. Wafer 

level cameras currently suffer from the problem that 

the volume of optical polymer required is insufficient 

for the chemical companies to justify investing in the 

development of new formulations. Consequently the 

companies that have developed successful wafer 

level optics technology have paid for the polymer 

development privately and all details about their 

chemistry properties and useage remain closely 

guarded trade secrets. This is clearly demonstrated 

by the lens slopes and sags. The optical design of 

wafer level cameras is limited by the achievable lens 

sag, which for commercial optical polymers and 

mastering techniques is around 200um [SSEC 

2009]. Higher values allow a camera module to 

maintain the same form factor but grow progressively 

in resolution. More than one company is 

demonstrating lenses with >500um sag and >50 

degree slopes on pre-production samples for ><strong>3M</strong>P 

reflowable wafer level cameras. 

Early wafer level cameras were built to mirror 

discrete counterparts on a piece by piece basis. Now 

the optical trains are extremely complex, exhibiting 

double-sided lenses where each surface can be a 

different material and size with different profiles and 

coatings . To achieve this degree of sophistication 

required a number of technical problems to be 

solved, including wafer bow after replication, lens 

figure error and lens dicing (the two key issues here 

being to ensuring the polymer lenses have adequate 

adhesion to the substrate and the avoiding 

contamination of the lens surface). As with the lens 

materials, there is little published information on the 

solutions, but that they have been solved is 

evidenced by product availability from more than one 

source at pricing that is aggressively competitive 

with discrete manufacturing and assembly. 

Similarly, the technology for mastering of lenses for 

wafer level cameras has advanced to the point 

where can be done directly for a fully populated 

200mm wafer to the slope and sag specification 

listed above. Previously masters had to be built 

using step-and-repeat or stitching methods, both of 

which give rise to alignment errors that are difficult to 

control. Clearly, direct mastering is a far superior 

approach. Although the equipment to make large 

masters is commercially available, it is sold without 

the know-how to achieve the placement accuracy, 

profile deviation and surface roughness necessary 

for camera lenses. This information is hard won and 

closely guarded by the companies that specialise in 

making lens masters. 

The optical train of a camera module consists of 

more than just lenses. To function correctly it must 

also contain, apertures, baffles, pupils and antireflection 

coatings to name a few. All of these 

components can be realised with semiconductor 

processing techniques at the wafer level. 

Assembly of optical components in a stack requires 

precise alignment in plane, rotation and tilt. The 

alignment accuracy is limited to the equipment 

capability, which is barely adequate for optical 

applications. The requirement is for front-to-back 

alignment of lenses fabricated on each side of a 

single substrate and wafer-to-wafer alignment to 

fabricate the camera module at the wafer level. Two 

complementary approaches are used to solve this 

problem. The first is good optics design, which takes 

into account the limitations of the equipment. For 

example good practice is to set the focus depth 

between the lens stack and imager to larger than the 

equipment 3 sigma metric. However this imposes 

constraints on other aspects of the optical 

performance of the design, which is not always 

desirable. Accordingly, great attention is being paid 

to techniques for getting the best possible 

performance from the assembly equipment. One 

exhibiting great promise is innovation in optical 

alignment marks, which are, of course, easily 

integrated with a wafer of optical elements. Another 

approach is active alignment. Commercial equipment 

capable of active alignment is too slow and too 

expensive to be used for assembly of wafer level 

cameras. The contract assembly companies have 

invested heavily in proprietary active alignment tools 

to the extent that a complete lens stack can be built 

and integrated with an imager using active alignment 

for each level of assembly including full-field 

measurement of MTF, taking only seconds per part. 

Fig 3 – Breakdown of cost for a discrete and a wafer level VGA camera module, normalised to the cost of the discrete imager die. The wafer level camera module 

is not only cheaper but there are further considerable savings to be gained when the module is integrated in the product by a simple solder reflow cycle, together 

with all the other surface mount components. 


7

J U L Y 2 0 0 9 i s s u e n ° 1 1 




YD: WLC manufacturing involves new 

technologies to be mastered. How the 

“traditional” camera module supply chain 

will be impacted by the introduction of 

WLC? 

GH & BK: The camera module supply chain is 

currently built around the premise of component-tocomponent 

assembly. Lenses and other optical 

components are obtained as discrete items, and 

assembled in to a barrel. Meanwhile, the imager die 

is attached and interconnected to a substrate using 

chip-on-board processes. A housing that goes over 

the die is attached to the substrate and the barrel 

screwed into the housing. Once the camera focus is 

correct the lens barrel is set in position. 

However this is not the entire picture. Camera 

modules manufactured from discrete parts are not 

compatible with solder reflow assembly. 

Consequently, the camera module has to be 

mounted on a flexible circuit that has an expensive 

connector at one end. Then, in yet another unique 

and serial process the camera module has to be 

aligned, attached and integrated into the cell phone 

housing or digital still camera body and the connector 

mated with its socket on the main PCB. The net 

result is that it can costs the cell phone manufacturer 

upto $4 to incorporate a $2 camera module (see 

Figure 3). The value proposition of the wafer level 

camera is that not only is the camera module 

cheaper per se, but it is reflow compatible so can be 

mounted on the main PCB at the same time as all 

the other surface mount components. In other words, 

at zero incremental cost to the cell phone 

manufacturer. 

One of the difficulties of any disruptive technology is 

that it is difficult to adapt the existing supply chain to 

start production, no matter how compelling the 

economic case. This is true in the case of reflowable 

wafer level cameras and thus far the majority of 

companies servicing this product are new entrants to 

the field of camera modules. New companies can 

afford to enter this space as they have no legacy 

contracts to fulfil, or equipment to write-off and the 

first adopters always get the highest value, which is 

sufficient to offset their investment costs. The 

emergence of wafer level cameras will either force 

the remainder of the supply chain to adopt to this 

technology or the new entrants simply grow until the 

volume demand is satisfied. 

In evaluating the impact wafer level cameras will 

have on the supply chain it is important to recognise 

that this innovation merely addresses cost and form 

factor. Wafer level cameras do not yet have any 

significant impact on performance. Performance 

improvements are likely to follow from the 

incorporation of technologies like Smart Optics, 

which give rise to features like continuous depth of 

field, ultra fast lenses and optical zoom with no 

moving parts. These developments can all be easily 

integrated into wafer level camera modules, but are 

either difficult or impossible to integrate with discrete 

assembly techniques. This will eventually lead to 

camera modules built using discrete assembly in the 

unhappy position of being physically larger, costing 

more and offering inferior performance. Based on 

this understanding, it is perhaps not surprising that 

market analysts predict that wafer level cameras will 

take more than 30% market share by 2012 [TSR, 

2008]. 

YD: What are the benefits for camera 

module manufacturers to invest into new 

equipment and facilities for WLC? 

GH & BK: Although the raw cost benefits of wafer 

level camera technology may appear compelling, to 

enter this market still requires substantial investment 

in new equipment and facilities. Once this investment 

is made it provides the camera module manufacturer 

with great flexibility in terms of the product range and 

mix they can offer. This arises because the much of 

the equipment is common, irrespective of whether 

the manufacturing company wants to pursue a 

strategy of wafer level packaging of imagers, 

manufacturing wafer level optical assemblies or 

building complete camera modules. A combined 

product line maximises the return from the 

investment as the capacity of most equipment 

exceeds the requirements of relatively high volume 

manufacture, enabling multiple product types to be 

run simultaneously. Even better is that the same 

equipment set is used for camera modules ranging 

from QCIF to multi-mega pixel resolution so no 

additional investment will be required until the 

transition to 300mm diameter wafers occurs, towards 

which there are not yet any obvious moves. 

The current supply chain for camera modules 

fabricated from discrete parts is long with many entities 

involved, each adding margin. Wafer level camera 

assembly is done as a one-stop endeavour making it 

simultaneously a more profitable venture for the 

camera module manufacturer and reduced cost 

component for the system integrator. It is therefore 

unsurprising that the production of reflowable camera 

References: 

modules has ballooned from less than 1,000 per year 

in 2006 to 10,000 per month in 2008 [TSR 2008]. 

YD: Do WLC necessitate specific 

packaging, in particular with through Si 

vias? 

GH & BK: As might be expected, there are several 

competing wafer level optics technologies 

commercially available. To manufacture a camera 

module entails not just lens technology, but also the 

ability to package the imager at the wafer level and 

provide the package with a ball grid array interface. 

Connection of the bond pads on the die to the 

package lands requires a through silicon via (TSV) 

technology. The problem with TSVs is that they are 

bedevilled by high cost and questionable reliability. 

Several companies now offer TSV technology for 

image sensors, although only one meets the base 

cost necessary to achieve the sub-$1 VGA camera 

module and has published reliability data 

demonstrating the package will not only surpass by 

a wide margin the cell phone specification for 

reliability but also the more arduous automotive 

specification as well [IEEE 2008]. 

YD: To conclude, what is your future 

vision for WLC? 

GH & BK: Wafer level cameras are manufactured by 

combining, parts that are fabricated and assembled 

at the wafer level. Their value proposition is based 

on substantial savings in cost, much smaller form 

factor and a manufacturing line that is product 

agnostic. Realising this value entailed solving many 

technical issues. Wafer level camera technology is 

still in its infancy but so compelling are the benefits 

that fully reflow compatible, wafer-level cameras with 

VGA resolution have been developed, designed in 

product and manufacturing volume is ramping fast. 

Multi megapixel variants are not far behind. It is 

forecast that within 4 years reflowable wafer level 

cameras will account for more than 30% of the 2bn 

camera modules manufactured annually. 

Contact : 

Sales@tessera.com 

• SSEC 2009 Semiconductor International, 6th February 2009, “Inside wafer-level Cameras” 

• TSR 2008 Techo Systems Research Company Ltd, December 2008 Researching Report, “Market 

breakdown of camera phone – 1st half 2008 & 2nd half 2008 forecast” 

• IEEE 2008 G Humpston, “Novel and low cost through silicon via solution for wafer scale packaging of 

image sensors”, Proceedings IEEE Electrical Design of Advanced Packaging and Systems 

Symposium, Seoul, 10-12 December, 2008 

8

J U N E 2 0 0 9 i s s u e n ° 1 1 


FROM INSPIRATION TO SOLUTION WITH LEADINGMEMS FABRICATION 

In MEMS fabrication the pioneering ASE® process from STS still 

dominates. Today, we continue to maintain our lead with 

unrivalled manufacturing experience and quality performance in 

MEMS fabrication. 

STS has the know-how to meet increasing demand for volume 

manufacture of MEMS devices, continually refining processes to 

turn advanced concepts into reality. For today and tomorrow, 

where STS leads others follow. 

To find out more visit: www.stsystems.com 

Courtesy of Sercalo Microtechnolgy Ltd 

MEMS COMPOUND SEMICONDUCTOR PHOTONICS ADVANCED PACKAGING DATA STORAGE 

Memory Applications 

Packaging & Integration Trends 

The new Yole studies will help you to understand how 3-D integration will challenge and reshape 

the memory industry? 

The memory semiconductor industry is about to go through 

a period of major technological changes as new integration 

trends and disruptive packaging technologies pave the way 

to the future growth of this industry … 

Report’s feature 

• Up-to-date Key metrics of the memory market: 

- Per application (more than 30 products screened) 

- Per type of memory (DRAM / SRAM / NOR / NAND 

Flash) 

- In Munits shipment and in 300mm wafer equivalent 

• Impact of 3-D integration on the memory market and 

applications 

• Key players strategy for 3DIC integration with memories 

• Cost analysis & challenges for TSV manufacturing: 

- How to make TSV interconnects happen in high 

volume/ low cost memory markets? 

Source: Yole Développement’s report 

For more information, please enter in contact with David Jourdan 

(jourdan@yole.fr - +33 472 83 01 90) 

9

Thin Wafer Processing 

for 3D TSV Applications 

Workshop 

Latest Thin Wafer Support Systems & Backside Processing 

<strong>SUSS</strong> MicroTec invites you to join us as industry leading experts explore the challenging process of temporary 

bonding and debonding for 3D integration schemes. 

Materials companies and industry manufacturers will address the following topics: 

+ Multiple temporary bond materials and processes 

+ Advances in processing on thin wafers on carriers 

+ Universal bonder platforms 

Free workshop during SEMICON West 

Wednesday, July 15-09 

St. Regis Hotel, San Francisco, California 

2pm – 5pm Workshop 

5pm – 6pm Reception 

Click here to register for this FREE workshop 

www.suss.com 

E-Mail: info@suss.com

J U L Y 2 0 0 9 i s s u e n ° 1 1 



IPD – 2009 Report - Technologies, Applications, Markets & Players 

The first complete study on Thin Film Integrated Passive & Active Devices 

Market trends 

From a commodity technology initially developed to 

replace bulky discrete passive components, thinfilm 

Integrated Passive Devices (IPD’s) are now a 

growing industry trend. 

They compete with discrete passive components on 

the one hand, and with organic or ceramic-based 

thick-film integrated passive devices on the other. 

They can be used as wafer-level packaged single 

chip solutions for interface conditioning, or they can 

be assembled with active IC’s in Systems-in-a- 

Package (SiP), or they can be used as package 

substrates or as system sub mounts. Based on IC 

and MEMS manufacturing technology, IPD’s offer 

designers miniature integration while maintaining 

high performance levels. 

Wireless SiP Module Technology Trend 

Logic 

eFlash 

eDRAM 

Analog 

RF + I/Os 

Interposer 

Whether it is to reduce space on the application 

board, to enhance performance or to reduce cost at 

the system level, IPD’s are spreading to most 

electronic sectors, from low volume to mass market 

businesses in aerospace, military, medical, industrial, 

lighting, communications, and PC applications. 

Over just a few years, IPD’s have become an 

essential enabler of System-in-Package (SiP) and 

heterogeneous integration in general. They greatly 

contribute to bridging the increasing gap between 

the ever-shrinking geometries of CMOS IC’s and the 

lagging packaging technologies, while allowing the 

integration of such diverse electronic functions as 

sensors, MEMS, RF receivers, transmitters, power 

amplifiers, power management units and digital 

Courtesy of ASE 


processors together into increasingly complete and 

autonomous systems. 

More than just a new packaging technique, and quite 

different from regular Integrated Circuit technologies, 

thin-film IPD’s truly import packaging into the clean 

room and are about to extend the use of Wafer-Level 

Packaging (WLP) not only to most IC package 

platforms but to the industry of discrete passive 

components as well. As a bridging technology, IPD’s 

involve the complete semiconductor value chain: 

from equipment and material suppliers to fabless 

IDMs to foundries to substrate suppliers to OSATs 

and OEMs. Yole estimates the total IPD market to 

represent more than $600M this year and we expect 

it to reach $1B by 2013. 

In this report, you will find comprehensive links 

between the technologies and their applications, as 

well as the market sizes by application and the 

market share and strategies of the major players. 

The technology trends and the challenges to be 

addressed are detailed, and market segment 

forecasts up to 2015 are given. 

Applications / Market windows for IPDs 

Network & 

Server 

Equipments 

Next Gen. Gaming 

Devices / Stations 

LED lighting 

Set-Top Box 

Industrial & 

Home Automotive 

Networking Car Electronic 

> 10M 

units 

HDTV 

Lower Volumes 

Medical 

Electronic 

MOTIVATIONS: 

• Smaller Size & Lighter Weight 

• Innovative Function & Flexible Design 

• Integrated System 

• High Electrical Performance 

• Low Cost & Time to Market 

> 100M units 

DSC 

> 1M units 

Netbook 

& MID 

Mil & 

Aerospace 

> 1B units 

High Volume 

PMP 

Mobile phones 

This report not only describes the market 

and the associated technologies deep 

inside the applications, but it also provides a 

broad overview of the thin-film IPD market and 

forthcoming growth opportunities. 

Who should buy this report? 

IPD manufacturers 

Foundries - 

Integrated semiconductor Device 

Manufacturers 

Assembly and Test Service companies 

Electronic module makers and Original 

Equipment Makers 

Equipment and Material manufacturers 

PCB manufacturers 

Discrete component makers 

Financial and strategic investors 

For more information, please contact 

Davi Jourdan at jourdan@yole.fr 



11

J U L Y 2 0 0 9 i s s u e n ° 1 1 



SET: Die/Flip chip Bonders able to align and bond 

fragile components at 0.5 μm post bond accuracy 

SET, Smart Equipment Technology, based in Saint-Jeoire, France, is a world leading 

supplier of High Accuracy Die-to-Die and Die-to-Wafer Bonders and versatile Nanoimprint Lithography (NIL) solutions. 

Company backgrounder 

In the early 1980s, SET has pioneered in 

the development of flip chip bonders for the 

hybridization of infrared imagers and the assembly 

of optoelectronics devices, by delivering the first 

commercially available Flip Chip Bonder on the 

market and introducing an image superimposing 

microscope which established 

SET as the industry leader for high accuracy 

placement. Supplier of semiconductor equipment 

dedicated to highend applications for over 30 years 

and with around 300 Device Bonders installed 

worldwide, SET is globally renowned for the 

unsurpassed accuracy and the flexibility of its flip 

chip bonders. SET encompasses a structure in 

North America and offers a comprehensive product 

portfolio of die/flip chip bonders for fast growing 

markets, serving clients through a global network 

of representatives and in-depth customer trainings. 

Since 2008, SET is a wholly owned subsidiary of 

Replisaurus Technologies. 

Product lines & technologies 

SET, employing 57 persons in France, has a long 

history in the development and production of high 

precision tools. This includes Chip-to-Chip or 

Chip-to-Wafer die bonders for 3D-IC integration, 

versatile Nanoimprinting Lithography Steppers and 

the Process Module for the innovative Replisaurus' 

ECPR technology. 

- Device Bonding 

SET develops and manufactures pieces of equipment 

addressing future challenges and fine pitch 

applications for high density integration. Primarily 

targeting low-volume and R&D applications, the 

current SET bonder portfolio covers a wide range 

of bonding applications with the ability to handle 

and bond fragile and small components onto large 

substrate or wafer. As the industry is poised to move 

3D packaging technology from labs to production, 

SET is actively engaged in European Programs 

including the development of High Accuracy, 

High Precision placement tools addressing the 

3D-IC integration with Through Silicon Via (TSV) 

technology. 

The recent introduction on the market of their 

SETFC300 has offered a timely response to the 

current research activities in this area. 

Products developpements & Current 

R&D projects 

Interview with Gilbert Lecarpentier, 

Business Development Manager at SET 

Yole Développement: What is historically the 

key bonding application for SET bonders? 

Gilbert Lecarpentier: SET bonders have been 

used successfully for over three decades to 

hybridize Infrared Imagers which consists of 

bonding a compound semiconductor on silicon 

CMOS readout. Thanks to their unrivalled 

accuracy and versatility, SET tools are now used 

by all major IR-FPA providers. 

YD: What represents 3D applications for SET 

in its short, medium and long term strategy? 

GL: High-end IR-FPA and 3D applications is the 

current market for our FC300, mainly because 

3D-IC is still in R&D. In longer term, 3D-IC is the 

opportunity for SET to enter into the production 

market; it is the driver for the development of 

a High Accuracy, High Speed platform. 3D-IC 

with its increasing demand of High Accuracy 

production C2W bonder is likely to become the 

main market for SET bonders. 

YD: Wafer-to-wafer is perceived as a cost 

effective technology for some 3D applications; 

what are the 3D applications likely to require 

die-to-die or die-towafer assembly? 

GL: Except for the memory market which can be 

addressed by wafer to wafer bonding because of 

the high yield and the same die size, most of the 

other 3D applications such as Memory on Logic or 

heterogeneous integration are candidates for the 

Chip to Wafer approach. SET bonders are wellsuited 

for heterogeneous integration; the bonding 

of GaAs epitaxial layer to Silicon substrate has 

been successfully demonstrated for a LED printer 

application. SET bonders have already been used 

for memory stack; the SAMSUNG memory stack 

shown by everybody in every 3D conference 

was performed on the SET-FC250 platform and 

the LETI has performed memory stack on SET- 

FC150 as early as 1997. 

YD: What is SET involvement in research 

programs for 3D integration? 

GL: SET has recently joined the IMEC’s Industrial 

Affiliation Program (IIAP) on 3D integration. The 

High Accuracy (0.5μm), High Force (400kgf) Die 

Bonder SET-FC300 is installed at IMEC and 

is used for developing processes with scaling 

capability for high throughput machine. In this 

3-Year JDP, SET supports the tool and the 

eventual modifications required for achieving the 

program, and collaborates with IMEC to develop 

high alignment accuracy pick-and-place as well as 

low Temperature bonding processes as required 

by advanced 3D integration schemes. SET and its 

mother company Replisaurus are partners of the 

European Project JEMSiP_3D. SET contributes 

in this 3-Year program with the development and 

the validation of a High Speed, High Accuracy Die 

Bonder required for the high volume production of 

3D devices using the TSV technology. 

Some other R&D projects, focusing on the 

development of alternative bonding methods 

enabling higher throughput are also in discussion. 

YD: SET also proposes Nanoimprinting 

Tools; what do you foresee as the main 

market drivers for this technology; is SET 

involved in research programs dedicated to 

Nanoimprinting Lithography? 

GL: After a big push few years ago of the 

semiconductor market, it seems that the main 

markets short and mid terms are the pattern media 

and the optoelectronics or optics; photonic crystal, 

light extraction enhancement, antireflective layer, 

etc. 

The SET-NPS300, a versatile Nanoimprinting 

tool using a step and repeat approach has been 

developed in the frame of the completed 4-Year 

European program NaPa. SET is currently partner 

of another 4-Year European project NaPANIL, 

targeting scalable nanomanufacturing processes 

for arbitrary 3-dimensional surfaces in the fields 

of optical components and life sciences. For SET, 

the key outcome of this framework is an alignment 

capability below 50nm. 

12 


- Nano Imprinting 

Its experience in high accuracy placement has 

enabled SET to bring to the market the cuttingedge 

Nanoimprinting Stepper (NPS300) at proven 

submicron alignment capabilities combined with 

superior flexibility. Nanoimprinting lithography 

consists of transferring the pattern of a stamp into a 

thermoplastic or UV-Cured material. This innovative 

technology is a very promising solution for replacing 

standard UVlithography systems at nano scale 

and reasonable cost. Applications include photonic 

crystal, antireflective or functionalized layer as well 

as 3-dimensional replication. 

Gilbert Lecarpentier, Business Development Manager 

After studying electronics in Caen, Calvados (France), Gilbert worked at Philips 

for 4 years designing special equipment for use in semiconductor production lines. 

In 1977, he joined Sulzer Electro Technique (S.E.T.) for developing equipment for 

semiconductor processing, such as Mask Aligner, Spinner, Prober, Laser Marker, 

Laser Scriber and Flip Chip Bonder. When <strong>SUSS</strong> MicroTec acquired SET in 1993, 

Gilbert took the product management responsibility of the device bonder product 

line. After the Management Buy Out of the <strong>SUSS</strong> MicroTec Device Bonder Division 

in July 2007, he assumes the role of business development manager for this product line and the 

newly developed Nano imprinting Stepper within the new company renamed SET, Smart Equipment 

Technology.

J U L Y 2 0 0 9 i s s u e n ° 1 1 


N E W S 

IBM fellow predicts end of Moore's Law: 3-D is next viable path! 

IBM Fellow Carl Anderson, who oversees physical design and tools in server division, predicted during the recent 

International Symposium on Physical Design 2009 conference the end of continued exponential scaling down of the size 

and cost of semiconductors. 

The end of the era of Moore's Law, Anderson 

declared, is at hand. Carl observed that like the 

railroad, automotive and aviation industries before it, 

the semiconductor industry has matured to the point 

that the pace of continued innovation is slowing. A 

generation or two of continued exponential growth 

will likely continue only for leading-edge chips 

such as multicore microprocessors, but more 

designers are finding that everyday applications do 

not require the latest physical designs, Anderson 

said. Consequently, Moore's Law--halving of the 

dimensions and doubling of speed of chips every 18 

months--will run out of steam very soon. 

Only a few high-end chip makers today can even 

afford the exorbitant cost of next-generation 

research and design, much less the fabs to build 

them. Anderson cited three next-generation 

technologies that were still on the fast track for 

exponential growth: optical interconnects, 3-D chips 

and accelerator-based processing. He predicted 

that rack-to-rack optical interconnects will become 

commonplace, with chip-to-chip optical connections 

on the same board coming soon. But Anderson said 

on-chip optical signaling remains years away. He 

predicted that stacked DRAM dies would be the first 

to go 3-D. 

Texas Instruments gets a WL-CSP IC design win in latest Apple's iPod 

shuffle 

Chipworks Inc. recently had the chance to open Apple new iPod's shuffle device and revealed that TI got a high volume 

design win with a WLCSP packaged controller IC located in the headphone cable. 

The new iPod shuffle has caused quite the 

“tempest in a teapot” over the last couple of 

weeks with the knowledge that the iPod contains 

no controls in the main body, only in the headphone 

cable. And standard headphones will not work with 

the iPod. Early speculation suggested that it was a 

DRM chip, which clearly would be a very, very bad 

thing. Fortunately this has been refuted by Apple, 

and it is just a proprietary control chip. Apparently 

part of a “made for iPod” licensing program that will 

incur additional charge to manufacturers wanting 

to make headphones for the iPod. So, it’s just a 

bad thing. Obviously some circuitry is required to 

control the iPod, and if you have no interface with 

the iPod, it has to be in the cable somewhere. One 

long-shot rumour is that the chip actually contains 

a microphone. As Apple does sell headphones with 

microphones, it’s just possible that they are using the 

same device and activating the microphone through 

software. So I thought I would throw our labs at this 

part and take a peek at what is inside this chip. 

The packaging is actually pretty unusual. It is a 

wafer level chip-scale bare die assembly, where 

the die has an RDL (metal redistribution layer) and 

solder balls directly flip chipped to the board. The 

die marking is a laser marking on the back of the 

silicon die. Here is the die “undressed.” . It’s a small, 

1.35 mm x 0.85 mm, die made by Texas Instruments 

with die markings of CDPS3271C. The die markings 

clarify the part number, which is actually a typical TI 

TI's controller IC die “undressed” in a WLCSP package (Pictures courtesy of Chipworks Inc.) 

date code. The 8x represents the year and month, 

and the next four characters are the lot code. 

Therefore, our three parts were made in September 

’08 (89), October ’08 (8A), and December ’08 (8C). 

Taking a peek at it down the microscope, it looks like 

it is fabricated with a three metal BiCMOS process, 

likely 0.25 µm or 0.18 µm. There is not really a lot 

of circuitry on the die, but then again how much is 

really needed to relay the button commands to the 

processor chip – just the volume controller and the 

interface for the capacitive sensors on the back of 

the board. 

www.chipworks.com 

R3Logic is awarded key patent for 3D EDA tools 

R3Logic, world leader in design tools for 3D integrated circuits <strong>announce</strong>s that it has been granted US patent #7,526,739 

for “Methods and systems for computer aided design of 3D integrated circuits”. 

The patented invention comprises both the 

method of defining a 3D technology file that 

can incorporate one or more 2D wafer technologies 

corresponding to different tiers in a 3D stack, and that 

of defining a 3D hierarchical structure for functional 

blocks within a 3D system. A key advantage to the 

3D technology file structure is that design kits and 

libraries for existing 2D processes do not have to be 

modified in any way to be used in a 3D design. It 

has been a fundamental assumption for the last 25 

years in EDA tools that one chip corresponds to one 

technology. As a result, designers who have tried to 

use existing 2D EDA tools to build 3D circuits have 

been forced to resort to gimmicks such as renaming 

design layers or creating multiple copies of standard 

cell libraries. Another drawback to current 2D tools 

is that there is no notion of a 3D hierarchy and thus 

no way to build IP libraries for 3D. An example of a 

stand-alone 3D functional unit would be an address 

decoder for a stacked memory device. These 

patented methods are fundamental to all of the 3D 

design tools developed by R3Logic. Being able to 

manage multiple design libraries and to properly 

handle IP blocks that reside on more than one tier 

is crucial to 3D system design, whether at the circuit 

layout or at the system architecture level. 

www.r3logic.com 


13

3-D Architectures for Semiconductor 

Integration and Packaging 

The Practical and Competitive Landscape on the Path to Implementation 

9–11 December 2009 

Hyatt Regency San Francisco Airport Hotel 

Burlingame, California 

For more information visit: 

http://techventure.rti.org 

Industry leaders have been speaking at and attending RTI’s conference, 3-D Architectures for Semiconductor Integration and 

Packaging, since 2004 and have benefited from the unique opportunity offered by this conference to explore the technology 

and business implications of the trend toward 3-D integration and packaging. This conference series has helped define this 

new facet of the semiconductor industry. It offers a unique perspective of the techno-business aspects of this emerging 

commercial opportunity, combining technology with business, research developments with practical insights, to offer 

industry leaders the information needed to plan and move forward with confidence. This conference targets senior-level 

technologists, managers, and business executives from the world’s leading companies and research institutions, 

and offers attendees the opportunity to learn from the presentations given by invited industry leaders, from the ample 

networking opportunities during the conference, and from the expanded exhibit offerings of this year’s event. 

6–8 OctOber, 2009 Dresden, Germany 

connect with europe’s technology 

Leaders and expand Your Opportunities 

in Infinite Ways. 

SEMICON Europa is the only event in Europe focused on 

connecting people and companies with the technologies 

and innovations making advanced microelectronics and 

related technologies possible. From device design to final 

manufacturing, no other event in Europe brings you better 

face-to-face contact with customers and technology 

partners than SEMICON Europa. 


This is SEMICON Europa. 

See You at SeMIcON europa 2009 

reGISter NOW: WWW.SeMIcONeurOpa.OrG 

14

J U L Y 2 0 0 9 i s s u e n ° 1 1 


NXP to sell French fab in Caen: Spin-out of new 3-D IC Company ahead 

Dutch semiconductor specialist NXP Semiconductors <strong>announce</strong>d plans to sell its French production unit in Caen to a 

group of unnamed investors, ADP News reported on 22 April 2009. 

The new owners will set up a new company to 

engage in the 3-D technology sector and employ 

a staff of 90 people. The company did not disclose 

financial details, but said that it hopes to close the 

deal by the end of April, and the new company will 

start activity by mid-May. Some of the plant's assets 

will be purchased by the new shareholders. NXP 

<strong>announce</strong>d its first intentions to sell the French plant 

in September 2008, but met with protests of trade 

unions and local institutions. 

www.nxp.com 

Rudolph Technologies & SEMATECH extend 

collaboration on 3D TSV process control 

Rudolph Technologies and SEMATECH 

<strong>announce</strong>d today that Rudolph has joined 

SEMATECH’s 3D Interconnect Program at the 

College of Nanoscale Science and Engineering 

(CNSE) of the University at Albany. The joint 

partnership is a continuation of collaborative efforts 

in process characterization, with a new focus on 3D 

IC (three-dimensional integrated circuits) processing 

and enhancing process control of TSV (throughsilicon 

vias) manufacturing. This is the second year 

that Rudolph will serve as a Member of SEMATECH. 

As a member of SEMATECH's 3D program, 

Rudolph's inspection and metrology technologies 

will be applied to various projects including via depth 

and CD metrology, metallization void detection, 

stacked wafer via alignment, wafer edge defect 

detection and bump height coplanarity. 

www.rudolphtech.com 

Rudolph NSX inspection tool for 3-D structures 

Rudolph <strong>announce</strong>s new 3D IC metrology tool for copper thickness 

measurements 

Rudolph Technologies <strong>announce</strong>d the availability 

of its new MetaPULSE(R)-G thin film 

measurement tool optimized specifically for copper 

damascene processes at 45nm through 22nm 

technology nodes and copper via fill in new 3D IC 

applications. Copper thickness and overburden 

measurements are critical in optimizing the CMP 

process that follows deposition during through-silicon 

via (TSV) manufacturing. The new tool measures 

60-80 product wafers per hour with gauge-capable 

precision and reduced cost of ownership. Rudolph is 

accepting orders now with initial shipments planned 

for the fourth quarter of 2009. 

www.rudolphtech.com 

<strong>3M</strong> & <strong>SUSS</strong> <strong>announce</strong> <strong>agreement</strong> on temporary wafer bonding 

technology to enable 3-D IC semiconductors 

from page 1 

This is particularly important in the multiple hightemperature 

cycles required in subsequent wafer 

processing steps. After processing, <strong>3M</strong>’s unique 

Light-To-Heat Conversion layer allows low stress, 

room temperature debonding of the thinned wafer 

directly to the tape carrier. 

The thinned wafer is supported throughout the entire 

process reducing warpage, stress and process 

complexity compared to other processes that require 

high-temperature exposure and stress to the thinned 

wafer, or solvents to release the temporary bonding 

material. <strong>3M</strong>’s WSS enables wafer processing 

currently in high-volume production at multiple 

semiconductor sites worldwide. “<strong>SUSS</strong> MicroTec is a 

recognized leader in wafer bonding and applications 

for 3-D and MEMS markets. Working with an industry 

leader, like <strong>SUSS</strong>, allows <strong>3M</strong> to focus on advanced 

materials development. The joint efforts of both 

companies provide <strong>3M</strong> customers with improved 

support, lower overall costs and faster access 

to more advanced solutions for their demanding 

3-D packaging requirements,” commented Mike 

Bowman, marketing development manager for <strong>3M</strong> 

Electronics Markets Materials Division. “We are 

pleased to collaborate with a leading material expert 

like <strong>3M</strong> to offer customers a leading edge temporary 

bonding process with superior performance 

compared to current materials and processes on the 

market,” said Wilfried Bair, general manager, Wafer 

Bonder Division, <strong>SUSS</strong> MicroTec. “This relationship 

and process offering fits nicely with <strong>SUSS</strong> MicroTec’s 

3-D strategy to provide a flexible and modular 

bonding platform that can be configured to meet 

customers’ needs.” 

www.<strong>3M</strong>.com 

Alchimer raises $10 million to expand global customer support and 

broaden new IP development 

from page 1 

e expect Alchimer to make a significant 

“Wcontribution to 3D-packaging technology, 

which will play an important role in the development 

of next-generation devices,” said Jean-Philippe 

Stefanini, general partner of Grenoble, Francebased 

Emertec Gestion. “Alchimer is an ideal fit for 

our portfolio, and we have great confidence in its 

experienced management team.” 

“The continued support of investors, especially 

in this difficult economic environment, is a solid 

endorsement of Alchimer’s innovative technology,” 

said Alchimer CEO Steve Lerner. “It also underscores 

the impact of Alchimer’s electrografting technology in 

enabling the emerging 3D market through process 

enhancement and cost reduction.” 

Alchimer recently <strong>announce</strong>d an enhancement of its 

eG ViaCoat process for the copper seed metallization 

of through-silicon vias (TSVs), which are used to 

create interconnections in advanced 3D-packaging 

applications. These structures are typically very 

narrow in comparison to their depth; this high 

aspect ratio creates a number of challenges to the 

deposition of uniform films. The eG ViaCoat process 

uses chemicals to deposit these films at levels of 

uniformity that meet or exceed standard industry 

quality metrics. In addition to having a number of 

process advantages, this “wet” approach allows the 

eG ViaCoat to be implemented on legacy plating 

equipment without retrofits or modifications. 

In further evidence of the company’s increasing 

acceptance as a low-cost alternative for TSV copper 

seed and related films, Alchimer <strong>announce</strong>d that it 

has signed an <strong>agreement</strong> with Nagase & Co. Ltd., 

a Tokyo-based technology-marketing company with 

an extensive background in chemicals, plastics and 

electronics. Nagase will help Alchimer meet rapidly 

increasing demand from key Japanese customers. 

www.alchimer.com 


15

Logic 

eFlash 

eDRAM 

Analog 

RF + I/Os 

Interposer 

TO BE 

RELEASED IN 

AUGUST 2009 

IPD – 2009 Report 

Technologies, Applications, Markets & Players 

The first complete study on Thin Film Integrated Passive & Active Devices 

IPD can be used as wafer-level 

packaged single chip solutions for 

interface conditioning, or they can 

be assembled with active IC’s in 

Systems-in-a-Package, or they can be 

used as package substrates or as 

system sub mounts. 


IPDs are also a nice example of a mix of 

technologies as both IC and MEMS worlds 

meet here, to offer higher performance 

with high integration. 

Our report is the first covering technology 

review for thin film IPD, description of the 

applications, market forecasts, roadmaps 

& manufacturing challenges, description 

of the supply chain with players profiles. 

Courtesy of ASE 

Devices / Stations 


Network & 

Server 

Equipments 

Next Gen. Gaming 

LED lighting 

Set-Top Box 

Industrial & 

Home 

Networking 

> 10M 

units 

HDTV 

Automotive 

Car Electronic 

Lower Volumes 

MOTIVATIONS: 

• Smaller Size & Lighter Weight 

• Innovative Function & Flexible Design 

• Integrated System 

• High Electrical Performance 

• Low Cost & Time to Market 

> 100M units 

DSC 

Medical 

Electronic 

Mil & 

Aerospace 

> 1M units 

> 1B units 

High Volume 

PMP 

Netbook 

& MID 

Mobile phones 

For more information, please enter in contact with David Jourdan 

(jourdan@yole.fr - +33 472 83 01 90) 

Editorial Staff 

- Managing Editor : Jean-Christophe Eloy - Editor in chief : Dr Eric Mounier - 

Editor: Jérôme Baron 

- Advertising: Sandrine Leroy 

- Graphic design engineer: Flora Courtin 


For more information on: 

- This newsletter, please ask our 3D IC project team: Jérôme Baron (baron@yole.fr) and Dr Eric 

Mounier (mounier@yole.fr) 

- Advanced packaging reports & Database at Yole Développement, please ask David Jourdan 

(jourdan@yole.fr) 

Read us on line at 

www.i-micronews.com

3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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