3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s C O M P A N Y P R O F I L E SET: Die/Flip chip Bonders able to align and bond fragile components at 0.5 μm post bond accuracy SET, Smart Equipment Technology, based in Saint-Jeoire, France, is a world leading supplier of High Accuracy Die-to-Die and Die-to-Wafer Bonders and versatile Nanoimprint Lithography (NIL) solutions. Company backgrounder In the early 1980s, SET has pioneered in the development of flip chip bonders for the hybridization of infrared imagers and the assembly of optoelectronics devices, by delivering the first commercially available Flip Chip Bonder on the market and introducing an image superimposing microscope which established SET as the industry leader for high accuracy placement. Supplier of semiconductor equipment dedicated to highend applications for over 30 years and with around 300 Device Bonders installed worldwide, SET is globally renowned for the unsurpassed accuracy and the flexibility of its flip chip bonders. SET encompasses a structure in North America and offers a comprehensive product portfolio of die/flip chip bonders for fast growing markets, serving clients through a global network of representatives and in-depth customer trainings. Since 2008, SET is a wholly owned subsidiary of Replisaurus Technologies. Product lines & technologies SET, employing 57 persons in France, has a long history in the development and production of high precision tools. This includes Chip-to-Chip or Chip-to-Wafer die bonders for 3D-IC integration, versatile Nanoimprinting Lithography Steppers and the Process Module for the innovative Replisaurus' ECPR technology. - Device Bonding SET develops and manufactures pieces of equipment addressing future challenges and fine pitch applications for high density integration. Primarily targeting low-volume and R&D applications, the current SET bonder portfolio covers a wide range of bonding applications with the ability to handle and bond fragile and small components onto large substrate or wafer. As the industry is poised to move 3D packaging technology from labs to production, SET is actively engaged in European Programs including the development of High Accuracy, High Precision placement tools addressing the 3D-IC integration with Through Silicon Via (TSV) technology. The recent introduction on the market of their SETFC300 has offered a timely response to the current research activities in this area. Products developpements & Current R&D projects Interview with Gilbert Lecarpentier, Business Development Manager at SET Yole Développement: What is historically the key bonding application for SET bonders? Gilbert Lecarpentier: SET bonders have been used successfully for over three decades to hybridize Infrared Imagers which consists of bonding a compound semiconductor on silicon CMOS readout. Thanks to their unrivalled accuracy and versatility, SET tools are now used by all major IR-FPA providers. YD: What represents 3D applications for SET in its short, medium and long term strategy? GL: High-end IR-FPA and 3D applications is the current market for our FC300, mainly because 3D-IC is still in R&D. In longer term, 3D-IC is the opportunity for SET to enter into the production market; it is the driver for the development of a High Accuracy, High Speed platform. 3D-IC with its increasing demand of High Accuracy production C2W bonder is likely to become the main market for SET bonders. YD: Wafer-to-wafer is perceived as a cost effective technology for some 3D applications; what are the 3D applications likely to require die-to-die or die-towafer assembly? GL: Except for the memory market which can be addressed by wafer to wafer bonding because of the high yield and the same die size, most of the other 3D applications such as Memory on Logic or heterogeneous integration are candidates for the Chip to Wafer approach. SET bonders are wellsuited for heterogeneous integration; the bonding of GaAs epitaxial layer to Silicon substrate has been successfully demonstrated for a LED printer application. SET bonders have already been used for memory stack; the SAMSUNG memory stack shown by everybody in every 3D conference was performed on the SET-FC250 platform and the LETI has performed memory stack on SET- FC150 as early as 1997. YD: What is SET involvement in research programs for 3D integration? GL: SET has recently joined the IMEC’s Industrial Affiliation Program (IIAP) on 3D integration. The High Accuracy (0.5μm), High Force (400kgf) Die Bonder SET-FC300 is installed at IMEC and is used for developing processes with scaling capability for high throughput machine. In this 3-Year JDP, SET supports the tool and the eventual modifications required for achieving the program, and collaborates with IMEC to develop high alignment accuracy pick-and-place as well as low Temperature bonding processes as required by advanced 3D integration schemes. SET and its mother company Replisaurus are partners of the European Project JEMSiP_3D. SET contributes in this 3-Year program with the development and the validation of a High Speed, High Accuracy Die Bonder required for the high volume production of 3D devices using the TSV technology. Some other R&D projects, focusing on the development of alternative bonding methods enabling higher throughput are also in discussion. YD: SET also proposes Nanoimprinting Tools; what do you foresee as the main market drivers for this technology; is SET involved in research programs dedicated to Nanoimprinting Lithography? GL: After a big push few years ago of the semiconductor market, it seems that the main markets short and mid terms are the pattern media and the optoelectronics or optics; photonic crystal, light extraction enhancement, antireflective layer, etc. The SET-NPS300, a versatile Nanoimprinting tool using a step and repeat approach has been developed in the frame of the completed 4-Year European program NaPa. SET is currently partner of another 4-Year European project NaPANIL, targeting scalable nanomanufacturing processes for arbitrary 3-dimensional surfaces in the fields of optical components and life sciences. For SET, the key outcome of this framework is an alignment capability below 50nm. 12 Printed on recycled paper - Nano Imprinting Its experience in high accuracy placement has enabled SET to bring to the market the cuttingedge Nanoimprinting Stepper (NPS300) at proven submicron alignment capabilities combined with superior flexibility. Nanoimprinting lithography consists of transferring the pattern of a stamp into a thermoplastic or UV-Cured material. This innovative technology is a very promising solution for replacing standard UVlithography systems at nano scale and reasonable cost. Applications include photonic crystal, antireflective or functionalized layer as well as 3-dimensional replication. Gilbert Lecarpentier, Business Development Manager After studying electronics in Caen, Calvados (France), Gilbert worked at Philips for 4 years designing special equipment for use in semiconductor production lines. In 1977, he joined Sulzer Electro Technique (S.E.T.) for developing equipment for semiconductor processing, such as Mask Aligner, Spinner, Prober, Laser Marker, Laser Scriber and Flip Chip Bonder. When <strong>SUSS</strong> MicroTec acquired SET in 1993, Gilbert took the product management responsibility of the device bonder product line. After the Management Buy Out of the <strong>SUSS</strong> MicroTec Device Bonder Division in July 2007, he assumes the role of business development manager for this product line and the newly developed Nano imprinting Stepper within the new company renamed SET, Smart Equipment Technology.
J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s N E W S IBM fellow predicts end of Moore's Law: 3-D is next viable path! IBM Fellow Carl Anderson, who oversees physical design and tools in server division, predicted during the recent International Symposium on Physical Design 2009 conference the end of continued exponential scaling down of the size and cost of semiconductors. The end of the era of Moore's Law, Anderson declared, is at hand. Carl observed that like the railroad, automotive and aviation industries before it, the semiconductor industry has matured to the point that the pace of continued innovation is slowing. A generation or two of continued exponential growth will likely continue only for leading-edge chips such as multicore microprocessors, but more designers are finding that everyday applications do not require the latest physical designs, Anderson said. Consequently, Moore's Law--halving of the dimensions and doubling of speed of chips every 18 months--will run out of steam very soon. Only a few high-end chip makers today can even afford the exorbitant cost of next-generation research and design, much less the fabs to build them. Anderson cited three next-generation technologies that were still on the fast track for exponential growth: optical interconnects, 3-D chips and accelerator-based processing. He predicted that rack-to-rack optical interconnects will become commonplace, with chip-to-chip optical connections on the same board coming soon. But Anderson said on-chip optical signaling remains years away. He predicted that stacked DRAM dies would be the first to go 3-D. Texas Instruments gets a WL-CSP IC design win in latest Apple's iPod shuffle Chipworks Inc. recently had the chance to open Apple new iPod's shuffle device and revealed that TI got a high volume design win with a WLCSP packaged controller IC located in the headphone cable. The new iPod shuffle has caused quite the “tempest in a teapot” over the last couple of weeks with the knowledge that the iPod contains no controls in the main body, only in the headphone cable. And standard headphones will not work with the iPod. Early speculation suggested that it was a DRM chip, which clearly would be a very, very bad thing. Fortunately this has been refuted by Apple, and it is just a proprietary control chip. Apparently part of a “made for iPod” licensing program that will incur additional charge to manufacturers wanting to make headphones for the iPod. So, it’s just a bad thing. Obviously some circuitry is required to control the iPod, and if you have no interface with the iPod, it has to be in the cable somewhere. One long-shot rumour is that the chip actually contains a microphone. As Apple does sell headphones with microphones, it’s just possible that they are using the same device and activating the microphone through software. So I thought I would throw our labs at this part and take a peek at what is inside this chip. The packaging is actually pretty unusual. It is a wafer level chip-scale bare die assembly, where the die has an RDL (metal redistribution layer) and solder balls directly flip chipped to the board. The die marking is a laser marking on the back of the silicon die. Here is the die “undressed.” . It’s a small, 1.35 mm x 0.85 mm, die made by Texas Instruments with die markings of CDPS3271C. The die markings clarify the part number, which is actually a typical TI TI's controller IC die “undressed” in a WLCSP package (Pictures courtesy of Chipworks Inc.) date code. The 8x represents the year and month, and the next four characters are the lot code. Therefore, our three parts were made in September ’08 (89), October ’08 (8A), and December ’08 (8C). Taking a peek at it down the microscope, it looks like it is fabricated with a three metal BiCMOS process, likely 0.25 µm or 0.18 µm. There is not really a lot of circuitry on the die, but then again how much is really needed to relay the button commands to the processor chip – just the volume controller and the interface for the capacitive sensors on the back of the board. www.chipworks.com R3Logic is awarded key patent for 3D EDA tools R3Logic, world leader in design tools for 3D integrated circuits <strong>announce</strong>s that it has been granted US patent #7,526,739 for “Methods and systems for computer aided design of 3D integrated circuits”. The patented invention comprises both the method of defining a 3D technology file that can incorporate one or more 2D wafer technologies corresponding to different tiers in a 3D stack, and that of defining a 3D hierarchical structure for functional blocks within a 3D system. A key advantage to the 3D technology file structure is that design kits and libraries for existing 2D processes do not have to be modified in any way to be used in a 3D design. It has been a fundamental assumption for the last 25 years in EDA tools that one chip corresponds to one technology. As a result, designers who have tried to use existing 2D EDA tools to build 3D circuits have been forced to resort to gimmicks such as renaming design layers or creating multiple copies of standard cell libraries. Another drawback to current 2D tools is that there is no notion of a 3D hierarchy and thus no way to build IP libraries for 3D. An example of a stand-alone 3D functional unit would be an address decoder for a stacked memory device. These patented methods are fundamental to all of the 3D design tools developed by R3Logic. Being able to manage multiple design libraries and to properly handle IP blocks that reside on more than one tier is crucial to 3D system design, whether at the circuit layout or at the system architecture level. www.r3logic.com Printed on recycled paper 13
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3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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