3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s
N E W S
IBM fellow predicts end of Moore's Law: 3-D is next viable path!
IBM Fellow Carl Anderson, who oversees physical design and tools in server division, predicted during the recent
International Symposium on Physical Design 2009 conference the end of continued exponential scaling down of the size
and cost of semiconductors.
The end of the era of Moore's Law, Anderson
declared, is at hand. Carl observed that like the
railroad, automotive and aviation industries before it,
the semiconductor industry has matured to the point
that the pace of continued innovation is slowing. A
generation or two of continued exponential growth
will likely continue only for leading-edge chips
such as multicore microprocessors, but more
designers are finding that everyday applications do
not require the latest physical designs, Anderson
said. Consequently, Moore's Law--halving of the
dimensions and doubling of speed of chips every 18
months--will run out of steam very soon.
Only a few high-end chip makers today can even
afford the exorbitant cost of next-generation
research and design, much less the fabs to build
them. Anderson cited three next-generation
technologies that were still on the fast track for
exponential growth: optical interconnects, 3-D chips
and accelerator-based processing. He predicted
that rack-to-rack optical interconnects will become
commonplace, with chip-to-chip optical connections
on the same board coming soon. But Anderson said
on-chip optical signaling remains years away. He
predicted that stacked DRAM dies would be the first
to go 3-D.
Texas Instruments gets a WL-CSP IC design win in latest Apple's iPod
shuffle
Chipworks Inc. recently had the chance to open Apple new iPod's shuffle device and revealed that TI got a high volume
design win with a WLCSP packaged controller IC located in the headphone cable.
The new iPod shuffle has caused quite the
“tempest in a teapot” over the last couple of
weeks with the knowledge that the iPod contains
no controls in the main body, only in the headphone
cable. And standard headphones will not work with
the iPod. Early speculation suggested that it was a
DRM chip, which clearly would be a very, very bad
thing. Fortunately this has been refuted by Apple,
and it is just a proprietary control chip. Apparently
part of a “made for iPod” licensing program that will
incur additional charge to manufacturers wanting
to make headphones for the iPod. So, it’s just a
bad thing. Obviously some circuitry is required to
control the iPod, and if you have no interface with
the iPod, it has to be in the cable somewhere. One
long-shot rumour is that the chip actually contains
a microphone. As Apple does sell headphones with
microphones, it’s just possible that they are using the
same device and activating the microphone through
software. So I thought I would throw our labs at this
part and take a peek at what is inside this chip.
The packaging is actually pretty unusual. It is a
wafer level chip-scale bare die assembly, where
the die has an RDL (metal redistribution layer) and
solder balls directly flip chipped to the board. The
die marking is a laser marking on the back of the
silicon die. Here is the die “undressed.” . It’s a small,
1.35 mm x 0.85 mm, die made by Texas Instruments
with die markings of CDPS3271C. The die markings
clarify the part number, which is actually a typical TI
TI's controller IC die “undressed” in a WLCSP package (Pictures courtesy of Chipworks Inc.)
date code. The 8x represents the year and month,
and the next four characters are the lot code.
Therefore, our three parts were made in September
’08 (89), October ’08 (8A), and December ’08 (8C).
Taking a peek at it down the microscope, it looks like
it is fabricated with a three metal BiCMOS process,
likely 0.25 µm or 0.18 µm. There is not really a lot
of circuitry on the die, but then again how much is
really needed to relay the button commands to the
processor chip – just the volume controller and the
interface for the capacitive sensors on the back of
the board.
www.chipworks.com
R3Logic is awarded key patent for 3D EDA tools
R3Logic, world leader in design tools for 3D integrated circuits <strong>announce</strong>s that it has been granted US patent #7,526,739
for “Methods and systems for computer aided design of 3D integrated circuits”.
The patented invention comprises both the
method of defining a 3D technology file that
can incorporate one or more 2D wafer technologies
corresponding to different tiers in a 3D stack, and that
of defining a 3D hierarchical structure for functional
blocks within a 3D system. A key advantage to the
3D technology file structure is that design kits and
libraries for existing 2D processes do not have to be
modified in any way to be used in a 3D design. It
has been a fundamental assumption for the last 25
years in EDA tools that one chip corresponds to one
technology. As a result, designers who have tried to
use existing 2D EDA tools to build 3D circuits have
been forced to resort to gimmicks such as renaming
design layers or creating multiple copies of standard
cell libraries. Another drawback to current 2D tools
is that there is no notion of a 3D hierarchy and thus
no way to build IP libraries for 3D. An example of a
stand-alone 3D functional unit would be an address
decoder for a stacked memory device. These
patented methods are fundamental to all of the 3D
design tools developed by R3Logic. Being able to
manage multiple design libraries and to properly
handle IP blocks that reside on more than one tier
is crucial to 3D system design, whether at the circuit
layout or at the system architecture level.
www.r3logic.com
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