3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s Printed on recycled paper E D I T O R I A L As you will discover in the article in this last issue of 3D Packaging newsletter, Integrated Passive Devices (IPD’s) are growing industry trend. They can be used as wafer-level packaged single chip solutions for interface conditioning, or they can be assembled with active IC’s in Systems-in-a-Package, or they can be used as package substrates or as system sub mounts. IPDs are also a nice example of a mix of technologies as both IC and MEMS worlds meet here, to offer higher performance with high integration. Our report is the first covering technology review for thin film IPD, description of the applications, market forecasts, roadmaps & manufacturing challenges, description of the supply chain with players profiles. Enjoy reading our newsletter! Dr Eric MOUNIER Editor in chief mounier@yole.fr E V E N T S • Semicon West, July 14-17, San Francisco, CA, USA • Semicon Europa, October 6-8, Dresden, Germany • 3-D Architectures for Semiconductor Integration and Packaging, This is SEMICON Europa. December 9 – 11, 2009, San Francisco, CA, USA A N A L Y S I S 3D Integration for wireless products: an industrial perspective The mobile phone and wireless industries have been growing at a very fast pace in the last 10 years. With more than 1.2 billion phones sold in 2008, the wireless market has been one of the main contributors in driving the development of the most advanced semiconductor technologies. The computing power for portable devices is becoming mandatory to enable mobile internet browsing, mobile TV, and all increasing multimedia features. In that context, miniaturization and performance are the driving forces for silicon technology development. Following the ITRS roadmap with CMOS downscaling is the traditional way to proceed. But the R&D expenses to sustain such a roadmap are extremely selective. Only a few companies or consortia can afford it. That’s why advanced CMOS technology could start to be seen as a kind of commodity and integration with new solutions appears as a much stronger differentiator element. Packaging contributions in the final product gained in importance. Major improvements and progresses have been done lately and a new solution is gaining more and more importance: 3D Integration. 3D Packaging Despite the recent buzz in the industry for a couple of months, 3D configurations are not new at all. In effect, 3D configurations at the packaging level have been 6–8 around OctOber, for years. In 2009 many teardowns Dresden, of Germany handsets, lot of 3D packages can be found. A stack of dice connect with wire bonds with is something europe’s very common technology for memories. Package over Package (PoP) Leaders and expand Your Opportunities Package in Package (PiP) is a configuration widespread in Infinite to combine Ways. the stack of memories on top of an application processor or digital baseband. At SEMICON Europa is the only event in Europe focused on the same time, 3D package solutions such as embedded connecting die in people laminate and or rebuilt companies wafer with such the as technologies Fan-Out and innovations Wafer Level making Packaging advanced (FO-WLP) microelectronics are and emerging. FO-WLP goal is to construct a package as related technologies possible. From device design to final small as possible to enable all the BGA balls to fit on it. The manufacturing, packaging is built no around other the event individual Europe known brings CIS. you better good face-to-face die and provides contact a way with to make customers the laminate and technology substrate vanish. FO-WLP improves signal integrity, partners than SEMICON Europa. shortens interconnects, reduces line/space for rerouting, and as a consequence, allows a reduction in the package See footprint. You at Infineon SeMIcON and Freescale europa 2009 developed reGISter their own NOW: FO-WLP WWW.SeMIcONeurOpa.OrG technology respectively called eWLB TM and RCP TM . Lately, STMicroelectronics partnered with Infineon and STATS Chip Pac to develop the 2nd generation of eWLB TM , 3D-eWLB TM , and enable 2-sided and consequently, 3D configurations. 3D at IC level using TSV All the configurations mentioned above are 3D at the packaging level. None of them uses TSV, which could allow “real” 3D at the IC level in some configurations. TSVs are nothing more than a techno brick that allows dice to interconnect on the vertical axis at the IC level. The impact of TSV is that these short interconnections could enable a new split of functions and new product partitioning. However, it is important to notice that TSV interconnections can be done at different levels and the impact on final applications is not the same. Either the TSV is done at the bond pad level or at the global interconnect level. At the bond pad level, TSV is done in a via last process in a wafer level packaging fab environment. The pitch of TSV is in the range of a bond pad pitch. Typical values from 50 to 150µ in term of pitch can be considered. An aspect ratio can reach 5:1 and filling is conformal or full. RLC electrical performances are better than wire bonds, except for the capacitance that may remain high. This type of TSV can be based on an improvement of technologies developed for At the global interconnect level, we consider TSV with higher aspect ratio done in foundry environment, preferably via middle (after FEOL but before BEOL) or first (before FEOL). TSV pitch is in the 10-20µ range with the aspect ratio ranging from 5:1 to 10:1 Fig1 - FOWLP 1 side (left) , 2 sides (called 3D-eWLB, right) 2
J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s Fig2 - From design to packaging: demonstration achieved between STMicroelectronics and CEA-LETI or even a bit more. For this category of TSV, dice are not only connected at bond pad level but also at the IP block or memory bank levels for instance. This type of TSV enables the achievement of structures with very short interconnections and good electrical performances. True heterogeneous integration is made possible and SoC–like features can be realized but using the third dimension and not only the x-y directions. Dice interconnected with this type of TSV are closer to SoC than SiP. For these reasons, 3D SoC is a very good term for this configuration. Figure 1 shows key demonstration achieve in STMicroelectronics with CEA-LETI. Complementarity of 3D packaging and 3D IC Except for some wafer-level chip-scale packages (WLCSP) or silicon interposer with TSV directly mounted on Printed Wiring Board (PWB) with a BGA balls, TSV is not a packaging solution by itself. TSV uses only “back-end world” skills such as bonding, fine pitch bumping, back grinding and thin wafer handling, for instance. In effect, final packaging is required to connect the device to the PWB. And due to assembly constraints, the choice of the final package solution could impact the entire TSV process flow. Fig3 - 3D IC TSV stack in 3D-eWLB (Courtesy of ST-Ericsson) This final packaging could be a BGA package, a Fan- Out WLP type, an embedded die in laminate, or other. Here, it is interesting to notice how complementary 3D IC configurations with TSV and 3D packaging can be. In effect, 3D eWLB TM can enable designs to fully benefit from the 3D IC integration, and for instance, reduce the package footprint with more aggressive design rules than BGA packages. TSV is a new technology and 3D eWLB TM a new packaging technology as well. Only considering BGA-type packages for structures with TSV might be a wrong reasoning. Some constraints can even be relaxed by coupling 3D IC TSV with 3D advanced packaging and then the full benefits of the TSV can emerge. Issues such as thin wafer handling can, for instance, be simplified. 3D Integration: Convergence of Architecture with Silicon & Package and Out of the box thinking required. 3D IC TSV is the convergence of silicon and packaging with the design. New architectures can in effect be considered and achieved. In fact, new architectures have to be considered if cost effectiveness is to be reached. In order to fully benefit from 3D TSV and make this technology cost effective, 3D architecture needs to be considered at a very early stage. However, designers are facing a gap between TSV technology process and TSV system design. This gap is due to the fact that there is no clear TSV technology roadmap in the industry. With a scaling-based approach and a classical follow-up of Moore’s law, it was easier to focus the R&D efforts and predict the size and performance of a new techno node. With 3D TSV, the industry is facing a new paradigm. Designers’ mentalities have to be modified and the former constraints of 2D have to be partially forgotten. Roadmaps exist, but are not necessarily very relevant. For this reason, many options can be considered, and process technologists do not know by themselves where to go and on what to focus. The only solution is to reinforce collaborations and discussions between the design community and the hardware technology community. A holistic approach is necessary to find the technology / design sweet spot and the application needs to drive developments. Application roadmap Applications that could use TSV and 3D remain a hot question. Only a few people have clear views on products that could use such innovations. Many niche markets would exist, for sure. However, when we think about core chipset components in wireless, the scope of applications tends to reduce. The following roadmap is based on ST-Ericsson’s and STMicroelectronics’ view and portfolio for wireless products (fig 2). Memory stacks with TSV such as DRAM are not mentioned as they are not part of the company business area anymore. Combinations of 3D IC TSV with advanced packaging such as 3D eWLB TM are not detailed on the schematics. The first CMOS Imaging Sensors are now on the market and ramping up. The possibility to substitute Printed on recycled paper 3
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3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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