3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s C O M P A N Y P R O F I L E The wafer level camera Juggernaut Novel technology, supply chain innovation and commercial pressures drive rapid adoption Wafer level cameras represent a tantalising opportunity to substantially decrease the cost and form factor of solid state camera modules. After many years of endeavour, successful integration of the technologies necessary to manufacture true wafer level cameras was <strong>announce</strong>d in 2007. While there is great potential for these cameras on mobile platforms, OEMs are reluctant to design-in product that is not commercially available and camera module manufacturers will not invest in the necessary manufacturing facilities when there is no demand. This article discuses the technical, supply chain and commercial challenges of wafer level camera technology and explains the background behind analysts prediction that by 2012 reflowable wafer level cameras will account for 30% of the 2bn camera modules manufactured annually. For Yole Développement, Giles Humpston & Bents Kidron from Tessera has highlighted what the trends, markets and challenges for WLC are. Yole Développement: Could you define what a wafer level camera is? Giles Humpston & Bents Kidron: Wafer level camera is “wafer level manufacture of all parts of a solid state camera that are then combined at the wafer level”. The final step of manufacture is wafer dicing, which frees complete and individual camera modules. Recently the technical issues to make wafer level cameras have all been solved and product <strong>announce</strong>ments appeared in 2007. However these first generation wafer level cameras are not manufactured according to the methodology suggested by the definition above. This is because it is perceived as uneconomic to do so. The issue is that the optical area of an imager die is very much smaller than the die area because of the other electronics each chip contains. The result is a mismatch in population between the lens wafers and the semiconductor wafers; a 200m diameter lens wafer being able to accommodate about 4 times as many lenses as an imager wafer containing VGA resolution die. There is also the issue of compound yield when mating a stack of optical components fabricated at the wafer level with a wafer containing imager die. In both cases the number of good optical die is less than the total number of die. Consequently it is economically more favourable to make the optical train at the wafer level, dice it into individual optical stacks then conduct die-to-wafer assembly to build camera modules. Dicing the populated semiconductor wafer yields completed camera modules, an example of which is shown in Figure 1. A slightly less rigorous definition of a wafer level camera that takes this reality into account is, “wafer level manufacture of all parts of a solid state camera that are combined while at least one part is at the wafer level”. YD: What are the advantages of WLC approach? GH & BK: The attractive attributes for wafer level cameras can be listed as follows: • Compact form factor. A VGA resolution wafer level camera can fit comfortably in a cube less than 2mm on a side and mega pixel cameras are insignificantly larger. Bents Kidron: at Tessera, Bents Kidron assumes ownership for all marketing and business development for all wafer level technologies in Tessera, including WLP (TSV), WLO (Wafer Level Optics), WLC (Wafer Level Camera). Fig 1 - Multi-level stack of optical parts manufactured at the wafer level using OptiML WLO technology and attached to an imager die housed in a SHELLCASE MVP wafer-level package that uses through silicon via interconnects. The result is a highly compact camera module with performance tailored for camera phones. Source: Tessera. • Low cost. Mechanical integration of a camera module in a cell phone costs several dollars. Reflowable wafer level cameras can be integrated at the same time as all the other surface mount components, making the sub-$1 VGA camera module a distinct possibility. • Improved reliability. Traditional camera modules are connected to the main PCB by a flexible circuit and miniature connector. Failure of these components is the primary cause of field returns of cell phones exhibiting camera faults. • Repeatable performance. Because all the parts of a wafer level camera are fabricated in parallel, they are virtually identical. The piece part variability is therefore reduced to a wafer basis and with many thousands of parts on a single wafer the distribution over the volume of the production run is much tighter than for discrete assembly. • Superior performance. Wafer level optics can be fabricated with lens profiles unachievable by other means. This means the lens designer has many more degrees of freedom to achieve the desired image quality (see Figure 2). Printed on recycled paper Giles Humpston: Director, Research and Development, Tessera. Giles Humpston, Ph.D., serves as Director, Research and Development of Tessera. Dr. Humpston has spent his professional career working in the field of semiconductor packaging, initially for military applications and, more recently, for high volume consumer products. He is a metallurgist by profession and has a doctorate in alloy phase equilibria. Humpston is a cited inventor on more than 75 patents and has co-authored several text books on metallic joining processes. His work and technical publications have been recognized by five international awards. Humpston’s current interests are packaging of solid state camera modules and product miniaturization through wafer level technologies. Combined, these benefits provided impetus to the endeavour necessary to convert the long held dream of the reflowable wafer level camera into a commercial reality. At the outset three barriers to widespread adoption of wafer level cameras were identified. They are: • Technology • Supply chain • Cost and competition 6
J U L Y 2 0 0 9 i s s u e n ° 1 1 N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s C O M P A N Y P R O F I L E Fig 2 - Pictures of fruit taken, left, with a VGA resolution wafer level camera having a single optical element and, right, the 5MP camera on a production model N95 cell phone. The cost differential between these two cameras, which is larger than an order of magnitude, is not immediately apparent in the image quality. YD: What are the main technical challenges to make WLC today? Can you comment where the pain points are? GH & BK: The principal technical challenges to making wafer level cameras are how to manufacture suitable lenses, combine these with other essential parts like apertures and filters, and then align and assemble these in a manner that yields an integrated optical component. Wafer level lenses are all made by replication processes. While these are well known and understood and suitable equipment is available commercially, there is a major issue in that traditional optical polymers are wholly inadequate for wafer level camera optics. Key attributes are optical performance, mouldability and compatibility with the thermal excursion of the lead-free solder reflow cycle, typically 265°C for 2 minutes, x3 cycles. Wafer level cameras currently suffer from the problem that the volume of optical polymer required is insufficient for the chemical companies to justify investing in the development of new formulations. Consequently the companies that have developed successful wafer level optics technology have paid for the polymer development privately and all details about their chemistry properties and useage remain closely guarded trade secrets. This is clearly demonstrated by the lens slopes and sags. The optical design of wafer level cameras is limited by the achievable lens sag, which for commercial optical polymers and mastering techniques is around 200um [SSEC 2009]. Higher values allow a camera module to maintain the same form factor but grow progressively in resolution. More than one company is demonstrating lenses with >500um sag and >50 degree slopes on pre-production samples for ><strong>3M</strong>P reflowable wafer level cameras. Early wafer level cameras were built to mirror discrete counterparts on a piece by piece basis. Now the optical trains are extremely complex, exhibiting double-sided lenses where each surface can be a different material and size with different profiles and coatings . To achieve this degree of sophistication required a number of technical problems to be solved, including wafer bow after replication, lens figure error and lens dicing (the two key issues here being to ensuring the polymer lenses have adequate adhesion to the substrate and the avoiding contamination of the lens surface). As with the lens materials, there is little published information on the solutions, but that they have been solved is evidenced by product availability from more than one source at pricing that is aggressively competitive with discrete manufacturing and assembly. Similarly, the technology for mastering of lenses for wafer level cameras has advanced to the point where can be done directly for a fully populated 200mm wafer to the slope and sag specification listed above. Previously masters had to be built using step-and-repeat or stitching methods, both of which give rise to alignment errors that are difficult to control. Clearly, direct mastering is a far superior approach. Although the equipment to make large masters is commercially available, it is sold without the know-how to achieve the placement accuracy, profile deviation and surface roughness necessary for camera lenses. This information is hard won and closely guarded by the companies that specialise in making lens masters. The optical train of a camera module consists of more than just lenses. To function correctly it must also contain, apertures, baffles, pupils and antireflection coatings to name a few. All of these components can be realised with semiconductor processing techniques at the wafer level. Assembly of optical components in a stack requires precise alignment in plane, rotation and tilt. The alignment accuracy is limited to the equipment capability, which is barely adequate for optical applications. The requirement is for front-to-back alignment of lenses fabricated on each side of a single substrate and wafer-to-wafer alignment to fabricate the camera module at the wafer level. Two complementary approaches are used to solve this problem. The first is good optics design, which takes into account the limitations of the equipment. For example good practice is to set the focus depth between the lens stack and imager to larger than the equipment 3 sigma metric. However this imposes constraints on other aspects of the optical performance of the design, which is not always desirable. Accordingly, great attention is being paid to techniques for getting the best possible performance from the assembly equipment. One exhibiting great promise is innovation in optical alignment marks, which are, of course, easily integrated with a wafer of optical elements. Another approach is active alignment. Commercial equipment capable of active alignment is too slow and too expensive to be used for assembly of wafer level cameras. The contract assembly companies have invested heavily in proprietary active alignment tools to the extent that a complete lens stack can be built and integrated with an imager using active alignment for each level of assembly including full-field measurement of MTF, taking only seconds per part. Fig 3 – Breakdown of cost for a discrete and a wafer level VGA camera module, normalised to the cost of the discrete imager die. The wafer level camera module is not only cheaper but there are further considerable savings to be gained when the module is integrated in the product by a simple solder reflow cycle, together with all the other surface mount components. Printed on recycled paper 7
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3M & SUSS announce agreement on temporary wafer ... - I-Micronews

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