Fan-in WLCSP matures, what's next? IMT on the role ... - I-Micronews

F E B R U A R Y 2 0 1 0 i s s u e n ° 1 4
N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s
C O M P A N Y V I S I O N
Packag<strong>in</strong>g challenges <strong>in</strong> high performance comput<strong>in</strong>g
Over the past half century, the semiconductor <strong>in</strong>dustry has been at the forefront of technological progress as demonstrated
by its own products and what they have made possible. The ma<strong>in</strong> areas of improvement <strong>in</strong>clude functionality per unit
volume, speed of performance, power consumed per unit performance, cost per function, etc. The bulk of the credit goes
to the m<strong>in</strong>iaturization and <strong>in</strong>tegration at the chip/wafer level as predicted by Moore’s Law, and made possible through
advancements <strong>in</strong> manufactur<strong>in</strong>g, design, simulation and materials.
Even less than twenty years back, packag<strong>in</strong>g
was considered an afterthought by
most of the <strong>in</strong>dustry, though the high
performance comput<strong>in</strong>g segment was the first
to devote significant resources for optimiz<strong>in</strong>g
the package performance. Start<strong>in</strong>g with the
C4 flip-chip package, there have been steady
improvements <strong>in</strong> high performance packag<strong>in</strong>g
<strong>in</strong>clud<strong>in</strong>g hav<strong>in</strong>g <strong>in</strong>terconnects greater than
10,000, pitch less than 200 µm, migration from
ceramic to organic substrates, and from highlead
to lead-free <strong>in</strong>terconnects. But fundamental
challenges rema<strong>in</strong>, and the ones that impact
packag<strong>in</strong>g are: (i) cost-effective manufactur<strong>in</strong>g
with <strong>in</strong>terconnects at f<strong>in</strong>er pitch than 150 µm, (ii)
mitigat<strong>in</strong>g the failures <strong>in</strong>duced by high currents
due to the phenomenon termed electromigration,
(iii) reliability of low-k dielectrics and <strong>in</strong>terconnects
under thermo-mechanical loads, and (iv) materials
and assembly issues. The <strong>in</strong>dustry is address<strong>in</strong>g
these issues through (i) substrate development
<strong>in</strong>clud<strong>in</strong>g solder on pad application improvements,
(ii) <strong>in</strong>terconnect modifications to avoid Copper
depletion and creation of voids, (iii) optimiz<strong>in</strong>g the
underfill properties to balance the stresses <strong>in</strong> the
low-k dielectric and <strong>in</strong>terconnects, and (iv) underfill
process improvements us<strong>in</strong>g jet or vacuum
dispense.
The one feature that has the most impact on
the above mentioned issues is the <strong>in</strong>terconnect
structure. The current ones <strong>in</strong> the <strong>in</strong>dustry
<strong>in</strong>clude high-lead solder bump, lead-free bump,
copper core, copper post, etc. In this article, an
<strong>in</strong>terconnect structure called µPILR TM <strong>in</strong>terconnect
is presented <strong>in</strong> detail as it addresses each of
the four challenges identified above. It consists
of a substrate manufactur<strong>in</strong>g technique that
results <strong>in</strong> a copper structure on a substrate pad.
This elim<strong>in</strong>ates the need for apply<strong>in</strong>g solder on
substrate, which is an issue at f<strong>in</strong>er pitches. Due
to the presence of copper structure, the failure due
to electromigration phenomenon is significantly
delayed on the substrate side due to the fact
that there is enough copper to eventually form a
relatively stable <strong>in</strong>termetallic, which has much
lower migration rate compared to copper <strong>in</strong> t<strong>in</strong>.
This retards the void growth and hence improves
reliability. Due to the 3D nature of the µPILR
<strong>in</strong>terconnect, the aspect ratio (height to diameter)
is higher than a solder bump; which eases the
package assembly issues such as <strong>in</strong>terconnect
jo<strong>in</strong>ts yield, underfill voids, etc. F<strong>in</strong>ally, the reliability
is improved because the fracture toughness of the
µPILR <strong>in</strong>terconnect is higher than solder bump
as the µPILR structure acts as a fatigue crack
growth <strong>in</strong>hibiter. It also offers better low-k dielectric
reliability as the lead-free solder <strong>in</strong>terface on the
chip side exerts lower stress than the copper post
on chip. This article presents design, simulation,
substrate manufactur<strong>in</strong>g, package assembly,
electromigration and reliability results for a test
vehicle represent<strong>in</strong>g CPU applications.
Flip-chip <strong>in</strong>terconnects
There are three ma<strong>in</strong> types of flip-chip <strong>in</strong>terconnect
be<strong>in</strong>g used <strong>in</strong> the <strong>in</strong>dustry: high-lead bump, leadfree
bump and copper post. The high-lead bump
is be<strong>in</strong>g phased out due to ROHS requirements.
The lead-free bump has f<strong>in</strong>e-pitch limitations due
to solder collapse and has low electromigration
performance. The copper post is emerg<strong>in</strong>g as
an option for high performance packag<strong>in</strong>g as
it offers f<strong>in</strong>e pitch capabilities and has good
electromigration performance. Some of the issues
with copper post on chip are lower reliability
with extreme low-k dielectrics and relatively
higher cost. In this paper, a new type of flip-chip
<strong>in</strong>terconnect called µPILR is presented that offers
the advantages of copper post on chip (f<strong>in</strong>e pitch
and good electromigration performance) while
offer<strong>in</strong>g good reliability and lower cost.
The typical failure modes seen <strong>in</strong> <strong>in</strong>terconnects
are related to <strong>in</strong>terconnect reliability (solder jo<strong>in</strong>t
fatigue life), package reliability (low-k dielectric
crack<strong>in</strong>g) and package performance (void<strong>in</strong>g
due to electromigration phenomemon from high
Figure 1: µPILR substrate with <strong>in</strong>terconnects that are highly co-planar
current densities). A new <strong>in</strong>terconnect design has
to address these issues while offer<strong>in</strong>g a roadmap
to f<strong>in</strong>e-pitch well below 100 µm and be able to
be manufactured us<strong>in</strong>g conventional <strong>in</strong>dustry
equipment and materials. The µPILR <strong>in</strong>terconnects
consist of an array of solid copper pillars that are
part of the substrate. Depend<strong>in</strong>g on the method of
manufactur<strong>in</strong>g, these <strong>in</strong>terconnects have different
sizes and shapes, and can be jo<strong>in</strong>ed to chips with
or without copper posts. Some of the different
configurations.
µPILR substrate
The µPILR substrate can be manufactured with
or without lam<strong>in</strong>ate core. The coreless method
consists of start<strong>in</strong>g with a copper sheet as the
base layer, carry<strong>in</strong>g out the build-up process to
the required number of layers and then process<strong>in</strong>g
the copper sheet to form µPILR <strong>in</strong>terconnects. The
core-based substrate approach consists of start<strong>in</strong>g
with a conventional substrate and then attach<strong>in</strong>g
a copper sheet and form<strong>in</strong>g µPILR <strong>in</strong>terconnects.
The ma<strong>in</strong> technical challenges <strong>in</strong> this process are:
• Uniformity of jo<strong>in</strong><strong>in</strong>g layer and its surface
properties • Formation of µPILRs through various
techniques
• Remov<strong>in</strong>g of jo<strong>in</strong><strong>in</strong>g layer and <strong>in</strong>termetallics
without damag<strong>in</strong>g the top circuit layer and
Uniformity of solder mask and alignment
Figure 1 shows the µPILR <strong>in</strong>terconnects on the
substrate. As they are formed from a copper sheet,
the measured co-planarity was excellent (± 2 µm).
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