Fan-in WLCSP matures, what's next? IMT on the role ... - I-Micronews

F E B R U A R Y 2 0 1 0 i s s u e n ° 1 4
N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s
Samsung presents new 3D TSV Packag<strong>in</strong>g Roadmap
It is not a secret that Samsung is actively prepar<strong>in</strong>g for 3D <strong>in</strong>tegration. The Korean electronic giant recently updated its
packag<strong>in</strong>g roadmap, <strong>in</strong>clud<strong>in</strong>g recent advancements <strong>in</strong> the commercialization of 3D TSV <strong>in</strong>terconnects.
Everyth<strong>in</strong>g really started on April 2006 and
later on April 2007 when Dr Chang-Gyu -
Samsung’s Hwang President & CEO - announced
the company <strong>in</strong>tention to commercialize 3D TSV
stacked NAND Flash memory and 3D TSV stacked
DRAM memory.
Talk<strong>in</strong>g about 3D silicon <strong>in</strong>tegration at that time, Dr
Chang even said «we are at the doorstep of the
largest shift <strong>in</strong> the semiconductor <strong>in</strong>dustry ever,
one that will dwarf the PC and even the consumer
electronics era».
Dr Chang cont<strong>in</strong>ued say<strong>in</strong>g that «it is generally
perceived that sub-25 nanometers is the limit to
maximiz<strong>in</strong>g the efficiency of the silicon base». But,
Dr. Hwang emphasized that alternate technologies
can counter this apparent dead-end <strong>in</strong> ultraf<strong>in</strong>e
process technology such as 3D structure
technology and 3D stack<strong>in</strong>g technology
Samsung 3D Packag<strong>in</strong>g roadmap
S<strong>in</strong>ce then, much th<strong>in</strong>gs have happened as the
lead<strong>in</strong>g semiconductor company re-organized and
recentered around 3 major bus<strong>in</strong>esses: memories
(DRAM, Flash, NVM ..), CMOS image sensors and
Logic LSI division. And it considerely impacted
the <strong>in</strong>ternal organization of the company’s R&D
program and efforts to commercialize 3D TSV
technology.
F<strong>in</strong>ally, the company announced late 2008 that
«Via Last» TSV / WLP manufactured at the
backside of the chips will be implemented first <strong>in</strong>to
CMOS image sensors, with similar approach that
Omnivion, Toshiba, Micron Apt<strong>in</strong>a and STMicro
did.
On the new roadmap presented above, Samsung
clearly show a strong <strong>in</strong>terest for <strong>in</strong>troduc<strong>in</strong>g
3D <strong>in</strong>to logic+memory and logic+logic stack<strong>in</strong>g
applications. These two last configurations are
now the ma<strong>in</strong> driv<strong>in</strong>g forces to implement 3D <strong>in</strong>to
<strong>next</strong> generation PoP (Package on Package) and
SiP (System <strong>in</strong> Package) applications such as
mobile processors, CPU and high performance
ASICs. The ma<strong>in</strong> drivers for 3D here are cost and
performance.
If the company expect to ship <strong>next</strong> 3D products
<strong>in</strong> the 2012-2013 time frame, challenges are still
present and numerous: namely, they <strong>in</strong>clude
300mm 3D TSV <strong>in</strong>frastructure availability, process
flow strategy and scenarios selection (Via first
/ Middle / Last / After Bond<strong>in</strong>g), Test (with the
possibility to stack only KGD, build BIST and
JTAG features, develop doble-side probe station
or contact-less test technologies, use <strong>in</strong>terconnect
redondancies) and I/O <strong>in</strong>terfaces specifications
(such as design rules for electrical rout<strong>in</strong>g,
mechanical bond<strong>in</strong>g and thermal dissipation).
www.samsung.com
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