The holy bible of SWEB - Institute of Applied Information Processing ...

3.3. BASIC CONCEPTS CHAPTER 3. VM, PROTECTION AND PAGING
but contains only Descriptors specific to one program. Usually there is one LDT for
each separate program. The running program can then choose between segments
by writing the corresponding index into one of the segment registers (CS for Code
Segment Register ,DS for Data Segment Register ,SS for Stack Segment Register)
Privilege Level
Four degrees between 0 and 3 of privileges exist on the IA32 Platform. The privilege
level determines how large a part of the instruction set a piece of code can use without
triggering a Protection Fault. The highest privilege is 0 and usually held only by the
operating system since everything is allowed here. In Sweb, the Kernel has Level
0 while user programs have Level 3. The Privilege Level is defined by setting the
DPL field of the Segment Descriptor in which a programs code runs. When changing
Segments (by loading a different Descriptor Index into a Segment Register) a program
may only decrease or hold its present privilege level. A program can however, access
privileged code through a Call Gate or asking the Operation System to increase its
Privilege Level.
3.3.3 Paging
Paging is the other protection mechanism and instead of Segmentation, was newly
introduced with Protected Mode. (Of course, the principle did exist long before the
IA32 platform adopted the concept).
Paging works by separating the physical memory into Pages of variable size and
mapping Pages in linear memory to Pages in physical memory. A Page can be 4 KiB,
2 MiB or 4MiB in size. It is also possible to mix 4KiB and 4MiB Pages. In Sweb we
mainly concern ourselves with 4KiB Pages. Physical Memory is the range of addresses
which translate directly into a memory register on the hardware. A linear memory
address however, does not necessarily correspond to an address in physical hardware
(see Figure 3.2). Rather the CPU translates a linear address into a physical address
according to the mapping that was set up by the operating system. Separation works
by assigning each program its own linear address space starting from 0 to 4 GiB.
In Sweb however, a user thread is not allowed to access an address beyond 2GiB.
Translation happens transparently and usually only the operating system knows what
the mapping looks like. Should an unmapped linear address be referenced, the CPU
causes a Page-Fault (Fault is a type of Exception) and calls Sweb’s Page-Fault-Handler
(as defined in the IDT) to deal with the problem.
Page-Directory and Page-Tables
The Mapping of Linear Memory to Physical Memory is defined in a Page-Directory
and its Page-Tables. A Page-Directory has 1024 entries. Each Entry has 32 bits.
A Page-Directory-Entry can either map a 4MiB Page or hold the physical address
of a Page-Table. (Actually it holds only the most significant 20 bits of the physical
address, which equal the physical 4KiB page number). A Page-Table again has 1024
Entries, each 32 bit in size. A Page-Table-Entry maps to a 4KiB Page in physical
memory. The structure of the Page-Directory-Entries and Page-Table-Entries is shown
in the following listing of paging-definitions.h. Note that the least significant 20 bits
in a Page-Directory-Entry can have different interpretations depending on the state
28 of 151