DC/DC Konverter – Grundstrukturen - Power Electronics Systems ...

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Solution – Control of a Three-Phase PWM Rectifier System
for the DC Link of a Drive System
The converter system in modern AC drives consists of a DC link between a three-phase inverter on the machine
side and a three-phase PWM rectifier (see Fig. 1) on the mains side. The PWM rectifier is there to provide a constant,
load-independent, DC link bus voltage, to ensure the sinusoidal input current that the drive system requires,
and to avoid reactive power from the grid. The task of this Exercise is to design, using the rotating coordinate
system, a controller for such a three-phase PWM rectifier and to test it through simulation. To simplify
this process, the aforementioned inverter is represented, considering a worst-case stability scenario, as a constant
power source. As a first approximation, the losses of the rectifier may be neglected. A purely sinusoidal, symmetric
(balanced) mains can also be assumed. The controller is to have a cascaded structure, i.e. with an inner
current and outer voltage control loop.
System specifications:
Input voltage:
Output voltage:
Output power:
Switching frequency:
Output capacitance:
Input inductance:
U N = 400 V rms (line-to-line voltage)
U 0 = 700 V
P = 6.8 kW
f S = 20 kHz
C = 2.2 mF
L = 1.2 mH
Figure 1: Three-phase PWM rectifier for supplying the input of the PWM inverter (represented here as a constant
power source) of a variable-speed three-phase machine drive.

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Part A – Calculation & Controller Design
In general, the lengths of the space vectors correspond to the amplitudes of the phase voltages and currents.
1) In order to have the inductor L conduct the required current, the converter must have a certain minimum voltage
vector . This can be determined by looking at the maximum modulation depth at the minimum DC
link voltage. Consider the steady-state vector diagram:
The voltage across the inductor L is
Figure 2: PWM Rectifier vector diagram
The mains current
power P:
is sinusoidal and in phase with the mains voltage. Knowing this, we can calculate the
| |
⁄ | |
The minimum converter voltage
can be calculated as
| | √| | | |
For the space vector modulation and the fundamental frequency modulation it follows that
| |
√
| |
From this we can calculate the minimum DC link voltage:
| | √
| |

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
2) The block diagram of the controller, including the feed-forward, is given below.
Figure 3: Controller structure including the decoupled current control and feed-forward
3) In dq-coordinates the circuit equations are
If we take into account the cross-coupling and the voltage feed-forward (
controller)
is the control variable of the current
and applying the Laplace transform we obtain the transfer functions:
In addition, there are time delays in the system due to the current measurement and the pulse pattern generation,
as shown in Fig. 4 for the d-component of the mains current ( ).
Figure 4: The d current control loop (i q =0)

Magnitude (dB)
Phase (deg)
Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
These two delay times can be represented as a single additional time constant T 1 =0.1 ms and their combined effect
can be approximated by a 1 st -order low-pass filter (Fig. 5).
The current transfer functions is therefore
Figure 5: Approximation of the total delay time
( )
( )
( )
Since the system has a linear behaviour, linearizing around an operating point can be omitted. The large and
small signal models are identical. If we want to, using a PI Controller, make the crossover frequency 1/20 of the
switching frequency and give the system a phase margin of at least 50°, then
and taking into account the PI controller‟s transfer function,
( )
we get the open-loop transfer function:
( ) ( ) ( )
The desired behaviour of the loop is achieved with the following parameters:
The resulting phase margin is about 55°, which results in stable operation.
100
50
Bode Diagram
G i
G PI
G openl
0
-50
-100
-150
0
-45
-90
-135
-180
10 1 10 2 10 3 10 4 10 5 10 6
Frequency (rad/sec)
Figure 6: Bode plots of the current control system

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
From the perspective of the significantly slower voltage controller, the closed current control loop can be approximated
as a 1 st -order low-pass filter. The equivalent time constant corresponds to the current control loop‟s
bandwidth:
( )
4) The voltage vectors and the fundamental of the input voltage are shown in Fig. 7 and Fig. 8.
Figure 7: Available space vectors at the converter input
Figure 8: Path of the voltage vector of the fundamental of the input voltage
The maximum converter voltage is limited by the circle inscribed on the hexagon (Fig. 8). Therefore, a limit
should be introduced at the output of the current controller.
| |
√
√

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Figure 9: Block diagram of the voltage control loop
5) First, the voltage control transfer function must be determined. Assuming , we can derive the following
circuit equations:
Additionally, the following holds,
( )
and substituting that into the second circuit equation above we get
Now we can perturb and linearize the circuit equations:
̃ ̇
̃
̃
̃
̃ ̇
̃

Phase (deg)
Magnitude (dB)
Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
The perturbation variable ̃
function:
is neglected. Applying the Laplace transform, we arrive at the voltage transfer
( ) ( ) ( )
( )
( )
( )
Adding in the approximation of the control loop (see 3) above), the plant is defined to be
( ) ( ) ( )
( )( )
From the above, the poles and zeros can be clearly seen to be
Since the output starting from a zero in the right half-plane moves first in the „wrong‟ direction, the controller
cannot be too fast – otherwise the system becomes unstable. That is, the closer to the origin the right half-plane
zero is, the slower the controller must be. Therefore, the critical operating point is at maximum power, i.e.
P = 6.8 kW. However, in this case, even for that point the zero is at z 1 = 19.6 kHz, which is quite far from the
required crossover frequency of 50 Hz. Therefore the right half-plane zero has practically no influence on the
design of the controller. The PI controller is of the form:
( )
The controller parameters can be derived mathematically (by solving the phase and magnitude equations for k pu
und T nu ) or by using MATLAB:
100
50
Bode Diagram
G str
R
G openl
0
-50
-100
180
90
0
-90
-180
10 0 10 1 10 2 10 3 10 4 10 5
Frequency (rad/sec)
Figure 10: Bode plots of the voltage control system

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
6) The transfer function of the voltage control loop is, in general, equivalent to the transfer function of a DC/DC
boost converter. To demonstrate this, the boost transfer function is derived below. The circuit equations are
( )( )
( ) ( )( )
Perturbing and linearizing around an operating point we get
̃ ̇
( )
̃
̃ ( ) ̃
( ) ̃ ( ) ̃ ̇
( )
̃
Neglecting the perturbations ̃ and ̃ and simplifying the equations, we get, after a Laplace transform:
( ) ( ) ( )
( ) ( ) ( ) ( )
Finally we get a transfer function that looks the same as that of the voltage loop derived in 5) (see
( ) above):
( )
( )
( )

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Part B – Simulation
The simulation model of the diode bridge rectifier can be found in the file solution_partB_8.ipes.
7) Phase voltages, phase currents, instantaneous, active, and reactive power, and the compensation currents of
the three-phase system, and the resulting mains currents:

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
After power factor correction, the resulting active power of the mains phase current is almost unchanged, while
the resulting reactive power is almost all gone. Please note that that for a correct calculation of the reactive power
Q, the circuit must be in steady-state.
The following code is in the JAVA block:
double u_nAlpha = xIN[0];
double u_nBeta = (xIN[1] - xIN[2]) / sqrt(3);
double i_nAlpha = xIN[3];
double i_nBeta = ( xIN[4] - xIN[5] ) / ( sqrt(3) );
// active power:
double P = yOUT[0] = 3.0 / 2.0 * (u_nAlpha * i_nAlpha + u_nBeta * i_nBeta);
// reactive power:
double Q = yOUT[1] = 3.0 / 2.0 * (u_nBeta * i_nAlpha - u_nAlpha * i_nBeta);
// compensating current in alpha-beta-coordinates:
double i_alphaRef = 2.0 / 3.0 * u_nBeta / (u_nAlpha * u_nAlpha + u_nBeta * u_nBeta) * Q;
double i_betaRef = -2.0 / 3.0 * u_nAlpha / (u_nAlpha * u_nAlpha + u_nBeta * u_nBeta) * Q;
// compensating phase currents (r,s,t):
double i_refR = yOUT[2] = i_alphaRef;
double i_refS = yOUT[3] = -0.5 * i_alphaRef + sqrt(3)/2 * i_betaRef;
double i_refT = yOUT[4] = -0.5 * i_alphaRef - sqrt(3)/2 * i_betaRef;
// resulting total phase current:
double i_nAlphaTot = i_nAlpha - i_alphaRef;
double i_nBetaTot = i_nBeta - i_betaRef;
// resulting phase currents (r,s,t):
double i_totR = yOUT[5] = i_nAlphaTot;
double i_totS = yOUT[6] = -0.5 * i_nAlphaTot + sqrt(3)/2 * i_nBetaTot;
double i_totT = yOUT[7] = -0.5 * i_nAlphaTot - sqrt(3)/2 * i_nBetaTot;
// compensated active power:
yOUT[8] = 3.0 / 2.0 * (u_nAlpha * i_nAlphaTot + u_nBeta * i_nBetaTot);
// compensated reactive power:
yOUT[9] = 3.0 / 2.0 * (u_nBeta * i_nAlphaTot - u_nAlpha * i_nBetaTot);

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
8) a) Plot 1: Input voltage (red), (uncompensated) input current (blue), compensation current (green). Notice here
that the compensation current vector (green) is perpendicular to the voltage space vector lines (red), and is the
vector projection of the current (blue) onto the voltage space vector.
b) Plot 2: die Input voltage (red), compensation current (green), compensated mains current (blue). It can be
seen here that the space vector of the resulting compensated mains current is in phase with the voltage space vector.
9) Transforming the mains voltage and current from coordinates into rotating dq-coordinates:
// Java-Code:
double epsilon = 2*Math.PI * time * 50;
double i_nd = yOUT[12] = sin(epsilon) * i_nBeta + cos(epsilon) * i_nAlpha;
double i_nq = yOUT[13] = cos(epsilon) * i_nBeta - sin(epsilon) * i_nAlpha;
double u_nd = yOUT[14] = u_nAlpha * cos(epsilon) + u_nBeta * sin(epsilon);
double u_nq = yOUT[15] = u_nBeta * cos(epsilon) - u_nAlpha * sin(epsilon);
double Pnd = yOUT[10] = 3.0 / 2.0 * (u_nd * i_nd + u_nq * i_nq);
double Qnd = yOUT[11] = 3.0 / 2.0 * (u_nq * i_nd - u_nd * i_nq);

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
10) GeckoCIRCUITS model of the three-phase PWM rectifier:
11) The GeckoCIRCUITS implementation of the current controller, with the output capacitor replaced by a constant
voltage source, can be found in the model file solution_partB_11.ipes.
12) The GeckoCIRCUITS implementation of the voltage controller is given in the model file solution_partB_12-
14.ipes:

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Space vector diagrams: Left: Transient, the current in the inductor starts at zero. Right: Steady-state.
Blue: mains voltage; red: converter input voltage; green: input voltage averaged over a switching period.

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
13) If the initial voltage of the output capacitor is too small, e.g. 450 V, the controller cannot stabilize the system
(see simulation results below). This happens because the output voltage is too low for the inductor to conduct the
required current (see the solution for 1) and the calculated there).
This problem can be solved by defining a “start-up” procedure for the system, which would make sure that the
output is pre-charged to the minimum required voltage, and only then allowing the voltage and current controllers
to operate.
14) Java code for discrete sampling:
// ------------ Exercise 13 - discrete output ----------------
if(xIN[6] < 1) { // calculate discrete, sampled output:
return yOUT;
}
double i_ndTrig = yOUT[12] = i_nd;
double i_nqTrig = yOUT[13] = i_nq;
double u_ndTrig = yOUT[14] = u_nd;
double u_nqTrig = yOUT[15] = u_nq;
return yOUT;
xIN[6] above is the “trigger” input, and if it is low (i.e. off), the JAVA block function returns immediately, returning
the old, previously stored value of the output. The current and voltage values sent to the output of the
JAVA block are therefore only updated when the trigger signal is high (i.e. on – greater than or equal to 1). In
the following simulation results you can see the difference between the continuous (left) and the discrete (sampled)
signal (right):

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
The advantage of discrete sampling is that the switching ripple is completely filtered out, since the sampling rate
is equal to the switching frequency. The controller therefore receives a much more stable signal.
The disadvantage is that the discrete sampling introduces a delay of T S / 2.
With each increase in delay, there is more instability in the current waveforms. The instability is a result of the
increased phase-shift introduced into the system by the increased delay. A delay longer than approximately
125 sec (+ 50 sec sampling delay) causes the voltage controller to become completely unstable, and the converter
no longer operates properly (see simulation results below).
Delay: 110 sec

Power Electronic Systems Laboratory Power Electronic Systems 2
Prof. Dr. J.W. Kolar Solution for Exercise No. 4
Delay: 125 sec