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Introduction 1.1 INTEGER UNIT USER PROGRAMMING MODEL Figure 1-1 illustrates the integer portion of the user programming model. It consists of the following registers: • 16 General-Purpose 32-Bit Registers (D7 – D0, A7 – A0) • 32-Bit Program Counter (PC) • 8-Bit Condition Code Register (CCR) . 31 15 0 D0 D1 D2 D3 D4 D5 D6 D7 DATA REGISTERS 31 15 0 A0 A1 A2 A3 A4 A5 A6 ADDRESS REGISTERS 31 31 15 15 7 0 0 0 A7 (USP) PC CCR USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER Figure 1-1. M68000 Family User Programming Model 1.1.1 Data Registers (D7 – D0) These registers are for bit and bit field (1 – 32 bits), byte (8 bits), word (16 bits), long-word (32 bits), and quad-word (64 bits) operations. They also can be used as index registers. 1.1.2 Address Registers (A7 – A0) These registers can be used as software stack pointers, index registers, or base address registers. The base address registers can be used for word and long-word operations. Register A7 is used as a hardware stack pointer during stacking for subroutine calls and exception handling. In the user programming model, A7 refers to the user stack pointer (USP). 1-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction 1.1.3 Program Counter The PC contains the address of the instruction currently executing. During instruction execution and exception processing, the processor automatically increments the contents or places a new value in the PC. For some addressing modes, the PC can be used as a pointer for PC relative addressing. 1.1.4 Condition Code Register Consisting of five bits, the CCR, the status register’s lower byte, is the only portion of the status register (SR) available in the user mode. Many integer instructions affect the CCR, indicating the instruction’s result. Program and system control instructions also use certain combinations of these bits to control program and system flow. The condition codes meet two criteria: consistency across instructions, uses, and instances and meaningful results with no change unless it provides useful information. Consistency across instructions means that all instructions that are special cases of more general instructions affect the condition codes in the same way. Consistency across uses means that conditional instructions test the condition codes similarly and provide the same results whether a compare, test, or move instruction sets the condition codes. Consistency across instances means that all instances of an instruction affect the condition codes in the same way. The first four bits represent a condition of the result generated by an operation. The fifth bit or the extend bit (X-bit) is an operand for multiprecision computations. The carry bit (C-bit) and the X-bit are separate in the M68000 family to simplify programming techniques that use them (refer to Table 3-18 as an example). In the instruction set definitions, the CCR is illustrated as follows: X N Z V C X—Extend Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result. N—Negative Set if the most significant bit of the result is set; otherwise clear. Z—Zero Set if the result equals zero; otherwise clear. V—Overflow Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise clear. MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-3
Page 1: MOTOROLA M68000 FAMILY Programmer
Page 5 and 6: Introduction 1.7 ORGANIZATION OF DA
Page 7 and 8: Introduction Control registers vary
Page 9 and 10: Addressing Capabilities An instruct
Page 11 and 12: Addressing Capabilities Table 2-2.
Page 13 and 14: Addressing Capabilities 2.2.4 Addre
Page 19 and 20: Addressing Capabilities 2.2.10 Memo
Page 21 and 22: Addressing Capabilities 2.2.12 Prog
Page 23 and 24: Addressing Capabilities 2.2.14 Prog
Page 25 and 26: Addressing Capabilities 2.2.16 Abso
Page 27 and 28: Addressing Capabilities Addressing
Page 29 and 30: Addressing Capabilities To implemen
Page 31 and 32: SECTION 3 INSTRUCTION SET SUMMARY T
Page 33 and 34: Instruction Set Summary Table 3-1.
Page 35 and 36: Instruction Set Summary 3.1.1 Data
Page 37 and 38: Instruction Set Summary A set of ex
Page 43 and 44: Instruction Set Summary 3.7 INSTRUC
Page 45 and 46: Integer Instructions ADD Add ADD (M
Page 47 and 48: Integer Instructions ADD Add ADD (M
Page 49 and 50: Integer Instructions ADDA Add Addre
Page 51 and 52: Integer Instructions ADDI Add Immed
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Integer Instructions ADDQ Add Quick
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Integer Instructions ADDX Add Exten
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Integer Instructions AND AND Logica
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Integer Instructions ANDI AND Immed
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Integer Instructions ANDI ANDI to C
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Integer Instructions ASL, ASR Arith
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Integer Instructions ASL, ASR Arith
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Integer Instructions Bcc Branch Con
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Integer Instructions CMP Compare CM
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Integer Instructions CMPA Compare A
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Integer Instructions CMPI Compare I
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Integer Instructions DBcc Test Cond
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Integer Instructions JSR Jump to Su
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Integer Instructions LSL, LSR Logic
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Integer Instructions LSL, LSR Logic
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Integer Instructions MOVE Move Data
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Integer Instructions MOVEA Move Add
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Integer Instructions RTR Return and
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Processor Instruction Summary A.1 M
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S-Record Output Format Table C-2. A
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