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SECTION 2 ADDRESSING CAPABILITIES Most operations take asource operand and destination operand, compute them, and store the result in the destination location. Single-operand operations take a destination operand, compute it, and store the result in the destination location. External microprocessor references to memory are either program references that refer to program space or data references that refer to data space. They access either instruction words or operands (data items) for an instruction. Program space is the section of memory that contains the program instructions and any immediate data operands residing in the instruction stream. Data space is the section of memory that contains the program data. Data items in the instruction stream can be accessed with the program counter relative addressing modes; these accesses classify as program references. 2.1 INSTRUCTION FORMAT M68000 family instructions consist of at least one word; some have as many as 11 words. Figure 2-1 illustrates the general composition of an instruction. The first word of the instruction, called the simple effective address operation word, specifies the length of the instruction, the effective addressing mode, and the operation to be performed. The remaining words, called brief and full extension words, further specify the instruction and operands. These words can be floating-point command words, conditional predicates, immediate operands, extensions to the effective addressing mode specified in the simple effective address operation word, branch displacements, bit number or bit field specifications, special register specifications, trap operands, pack/unpack constants, or argument counts. 15 0 SINGLE EFFECTIVE ADDRESS OPERATION WORD (ONE WORD, SPECIFIES OPERATION AND MODES) SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS) DESTINATION EFFECTIVE ADDRESS EXTENSION (IF ANY, ONE TO SIX WORDS) Figure 2-1. Instruction Word General Format MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-1
Addressing Capabilities An instruction specifies the function to be performed with an operation code and defines the location of every operand. Instructions specify an operand location by register specification, the instruction’s register field holds the register’s number; by effective address, the instruction’s effective address field contains addressing mode information; or by implicit reference, the definition of the instruction implies the use of specific registers. The single effective address operation word format is the basic instruction word (see Figure 2-2). The encoding of the mode field selects the addressing mode. The register field contains the general register number or a value that selects the addressing mode when the mode field contains opcode 111. Some indexed or indirect addressing modes use a combination of the simple effective address operation word followed by a brief extension word. Other indexed or indirect addressing modes consist of the simple effective address operation word and a full extension word. The longest instruction is a MOVE instruction with a full extension word for both the source and destination effective addresses and eight other extension words. It also contains 32-bit base displacements and 32-bit outer displacements for both source and destination addresses. Figure 2-2 illustrates the three formats used in an instruction word; Table 2-1 lists the field definitions for these three formats. SINGLE EFFECTIVE ADDRESS OPERATION WORD FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EFFECTIVE ADDRESS X X X X X X X X X X MODE REGISTER BRIEF EXTENSION WORD FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D/A REGISTER W/L SCALE 0 DISPLACEMENT FULL EXTENSION WORD FORMAT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D/A REGISTER W/L SCALE 1 BS IS BD SIZE 0 I/IS BASE DISPLACEMENT (0, 1, OR 2 WORDS) OUTER DISPLACEMENT (0, 1, OR 2 WORDS) Figure 2-2. Instruction Word Specification Formats 2-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Page 1 and 2: MOTOROLA M68000 FAMILY Programmer
Page 3 and 4: Introduction 1.1.3 Program Counter
Page 5 and 6: Introduction 1.7 ORGANIZATION OF DA
Page 7: Introduction Control registers vary
Page 11 and 12: Addressing Capabilities Table 2-2.
Page 13 and 14: Addressing Capabilities 2.2.4 Addre
Page 19 and 20: Addressing Capabilities 2.2.10 Memo
Page 21 and 22: Addressing Capabilities 2.2.12 Prog
Page 23 and 24: Addressing Capabilities 2.2.14 Prog
Page 25 and 26: Addressing Capabilities 2.2.16 Abso
Page 27 and 28: Addressing Capabilities Addressing
Page 29 and 30: Addressing Capabilities To implemen
Page 31 and 32: SECTION 3 INSTRUCTION SET SUMMARY T
Page 33 and 34: Instruction Set Summary Table 3-1.
Page 35 and 36: Instruction Set Summary 3.1.1 Data
Page 37 and 38: Instruction Set Summary A set of ex
Page 43 and 44: Instruction Set Summary 3.7 INSTRUC
Page 45 and 46: Integer Instructions ADD Add ADD (M
Page 47 and 48: Integer Instructions ADD Add ADD (M
Page 49 and 50: Integer Instructions ADDA Add Addre
Page 51 and 52: Integer Instructions ADDI Add Immed
Page 53 and 54: Integer Instructions ADDQ Add Quick
Page 55 and 56: Integer Instructions ADDX Add Exten
Page 57 and 58: Integer Instructions AND AND Logica
Page 59 and 60:
Integer Instructions ANDI AND Immed
Page 61 and 62:
Integer Instructions ANDI ANDI to C
Page 63 and 64:
Integer Instructions ASL, ASR Arith
Page 65 and 66:
Integer Instructions ASL, ASR Arith
Page 67 and 68:
Integer Instructions Bcc Branch Con
Page 69 and 70:
Integer Instructions CMP Compare CM
Page 71 and 72:
Integer Instructions CMPA Compare A
Page 73 and 74:
Integer Instructions CMPI Compare I
Page 75 and 76:
Integer Instructions DBcc Test Cond
Page 77 and 78:
Integer Instructions JSR Jump to Su
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Integer Instructions LSL, LSR Logic
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Integer Instructions LSL, LSR Logic
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Integer Instructions MOVE Move Data
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Integer Instructions MOVEA Move Add
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Integer Instructions RTR Return and
Page 89 and 90:
Processor Instruction Summary A.1 M
Page 91 and 92:
S-Record Output Format Table C-2. A
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