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Introduction . 31 30 MSB 1 0 LSB BIT (0
Introduction Control registers vary in size according to function. Some control registers have undefined bits reserved for future definition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility. All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, despite privilege mode. The alternate function code registers, supervisor function code (SFC) and data function code (DFC), are 32-bit registers with only bits 0P2 implemented. These bits contain the address space values for the read or write operands of MOVES, PFLUSH, and PTEST instructions. Values transfer to and from the SFC and DFC by using the MOVEC instruction. These are long-word transfers; the upper 29 bits are read as zeros and are ignored when written. 1.7.2 Organization of Integer Data Formats in Memory The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a long-word data item corresponds to the address of the highest order wordUs MSB. The lower order word is located at address N + 2, leaving the LSB at address N + 3 (see Figure 1-20). Organization of data formats in memory is consistent with the M68000 family data organization. The lowest address (nearest $00000000) is the location of the MSB, with each successive LSB located at the next address (N + 1, N + 2, etc.). The highest address (nearest $FFFFFFFF) is the location of the LSB. . 31 23 15 7 0 LONG WORD $00000000 WORD $00000000 WORD $00000002 BYTE $00000000 BYTE $00000001 BYTE $00000002 BYTE $00000003 LONG WORD $00000004 WORD $00000004 WORD $00000006 BYTE $00000004 BYTE $00000005 BYTE $00000006 BYTE $00000007 LONG WORD $FFFFFFFC WORD $FFFFFFFC WORD $FFFFFFFE BYTE $FFFFFFFC BYTE $FFFFFFFD BYTE $FFFFFFFE BYTE $FFFFFFFF Figure 1-20. Memory Operand Addressing MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-27
Page 1 and 2: MOTOROLA M68000 FAMILY Programmer
Page 3 and 4: Introduction 1.1.3 Program Counter
Page 5: Introduction 1.7 ORGANIZATION OF DA
Page 9 and 10: Addressing Capabilities An instruct
Page 11 and 12: Addressing Capabilities Table 2-2.
Page 13 and 14: Addressing Capabilities 2.2.4 Addre
Page 19 and 20: Addressing Capabilities 2.2.10 Memo
Page 21 and 22: Addressing Capabilities 2.2.12 Prog
Page 23 and 24: Addressing Capabilities 2.2.14 Prog
Page 25 and 26: Addressing Capabilities 2.2.16 Abso
Page 27 and 28: Addressing Capabilities Addressing
Page 29 and 30: Addressing Capabilities To implemen
Page 31 and 32: SECTION 3 INSTRUCTION SET SUMMARY T
Page 33 and 34: Instruction Set Summary Table 3-1.
Page 35 and 36: Instruction Set Summary 3.1.1 Data
Page 37 and 38: Instruction Set Summary A set of ex
Page 43 and 44: Instruction Set Summary 3.7 INSTRUC
Page 45 and 46: Integer Instructions ADD Add ADD (M
Page 47 and 48: Integer Instructions ADD Add ADD (M
Page 49 and 50: Integer Instructions ADDA Add Addre
Page 51 and 52: Integer Instructions ADDI Add Immed
Page 53 and 54: Integer Instructions ADDQ Add Quick
Page 55 and 56: Integer Instructions ADDX Add Exten
Page 57 and 58:
Integer Instructions AND AND Logica
Page 59 and 60:
Integer Instructions ANDI AND Immed
Page 61 and 62:
Integer Instructions ANDI ANDI to C
Page 63 and 64:
Integer Instructions ASL, ASR Arith
Page 65 and 66:
Integer Instructions ASL, ASR Arith
Page 67 and 68:
Integer Instructions Bcc Branch Con
Page 69 and 70:
Integer Instructions CMP Compare CM
Page 71 and 72:
Integer Instructions CMPA Compare A
Page 73 and 74:
Integer Instructions CMPI Compare I
Page 75 and 76:
Integer Instructions DBcc Test Cond
Page 77 and 78:
Integer Instructions JSR Jump to Su
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Integer Instructions LSL, LSR Logic
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Integer Instructions LSL, LSR Logic
Page 83 and 84:
Integer Instructions MOVE Move Data
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Integer Instructions MOVEA Move Add
Page 87 and 88:
Integer Instructions RTR Return and
Page 89 and 90:
Processor Instruction Summary A.1 M
Page 91 and 92:
S-Record Output Format Table C-2. A
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