V54C3128(16/80/40)4VC 128Mbit SDRAM 3.3 VOLT, TSOP II / BGA ...
V54C3128(16/80/40)4VC 128Mbit SDRAM 3.3 VOLT, TSOP II / BGA ...
V54C3128(16/80/40)4VC 128Mbit SDRAM 3.3 VOLT, TSOP II / BGA ...
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ProMOS TECHNOLOGIES<br />
<strong>V54C3128</strong>(<strong>16</strong>/<strong>80</strong>/<strong>40</strong>)<strong>4VC</strong><br />
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11. Power on Sequence and Auto Refresh (CBR)<br />
T0 T T T T T T T T T T1 T T T T T T T TT T T T<br />
CLK<br />
CKE<br />
High level<br />
is required<br />
Minimum of 2 Refresh Cycles are required<br />
2 Clock min.<br />
tMRD<br />
CS<br />
RAS<br />
CAS<br />
WE<br />
BA<br />
AP<br />
Address Key<br />
Addr<br />
DQM<br />
Hi-Z<br />
I/O<br />
tRP<br />
tRFC<br />
t RC<br />
Precharge<br />
Command<br />
All Banks<br />
1st Auto Refresh<br />
Command<br />
2nd Auto Refresh<br />
Command<br />
Mode Register<br />
Set Command<br />
Low Power Mode Register<br />
Set Command<br />
Inputs must be<br />
stable for 200 s<br />
<strong>V54C3128</strong>(<strong>16</strong>/<strong>80</strong>/<strong>40</strong>)<strong>4VC</strong> Rev. 1.3 November 2008<br />
32
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