RC5T583S PCB LAYOUT GUIDE - Ricoh

RC5T583S PCB LAYOUT GUIDE
RC5T583S
PCB Layout Guide
Version 1.0
September 28, 2012
RICOH COMPANY, LTD.
Electronic Devices Company
©2012

RC5T583S PCB LAYOUT GUIDE
Abstract
This document describes the constraints and points when designing the PCB layout with RC5T583S.
This guide provides examples to explain of how it can be done.
The PCB layout example is helpful to achieve optimal RC5T583S performance.
Contents
1. Basic Policy and Examples of Board Pattern ............................................................................................. 3
1.1 ................................................................................................................................. 3
1.1.1 DCDC1, DCDC2 and DCDC3 .....................................................................................................................3
1.1.2 DCDC0 (High current type) .........................................................................................................................8
1.2 RTC Block...................................................................................................................................... 12
2. Recommended External Parts List (*Maximum height: 3.0mm)......................................................... 14
3 Parts Place Example ......................................................................................................................... 15
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RC5T583S PCB LAYOUT GUIDE
1. Basic Policy and Examples of Board Pattern
1.1
1.1.1 DCDC1, DCDC2 and DCDC3
Current Loop
Cin_A
Analog
Power
Supply
RCT583S
Buffer
Power
Supply
Cin_B
(Input capacitance)
VFB
Control
and
Analog
BUF
LX
L
Vout
Cout
(Output capacitance)
Analog
GND
Buffer
GND
Fig.1-1 Simplified Schematic for DCDC
DCDC1 DCDC2 DCDC3
Analog Power Supply
VIN3
Buffer Power Supply VIN2, 5 VIN4 VIN6, 7
Buffer GND GND 2, 3 GND 4, 5 GND 6, 7
Analog GND
GND8
VFB FB1 FB2 FB3
LX LX11, 12 LX21, 22 LX31, 32
Table1-1: RC5T583S Pin Names
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RC5T583S PCB LAYOUT GUIDE
(4)
(1)
Vout
Cout
L
(3)
(2)
LX
(5)
(5)
Fig.1-2 DCDC Block Evaluation Board Pattern (Top Layer)
(1) Place the parts to minimize the switching current loop (Figure 1-1: blue line, Figure 1-2: red line).
(2) Route the LX line as short and wide as possible between RC5T583S and an inductor and prohibit
adding other redundant lines to the LX line.
(3) Connect the GND line of “Cout” directly to the internal GND plane with multiple vias, in order to reduce
impedance as small as possible. (Target: 50mΩ or less)
(4) Begin to route the VOUT line from near not “L” but “Cout”.
(5) Place inductors for neighboring DCDC without becoming too close between them, in order to avoid the
electromagnetic interference.
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RC5T583S PCB LAYOUT GUIDE
Vout
Cout
L
VFB
LX
(6)
Fig.1-3: DCDC Block Evaluation Board Pattern (Top Layer (Lx) + 3rd Layer (VFB))
(6) Route the VFB line not to become in parallel with lines, which may be a source of noise, such as the LX
line. If possible, route the VGB line at other layer.
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RC5T583S PCB LAYOUT GUIDE
(8)
Analog GND
(7)
Buffer GND
Fig.1-4: DCDC Block Evaluation Board Pattern (6th Layer)
(7) Provide the ground plane for Analog-GND and Buffer-GND to the inner layer and multiple vias, in order
to minimize impedance.
(8) Divide Analog-GND from Buffer-GND in order to give impedance and avoid mutual interference.
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RC5T583S PCB LAYOUT GUIDE
Buffer power supply
(9)
Cin_B
Fig.1-5: DCDC Block Evaluation Board Pattern (5th Layer (Vin_b) + Bottom Layer (Cin_b))
(9) Place “Cin” as close as possible to RC5T583S. (Higher priority level is “Cin” < L < “Cout” in the close
distance order with RC5T583S)
In the case of the “Cin” as one example; Place “Cin” on the underside, in order to close to RC5T583S.
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RC5T583S PCB LAYOUT GUIDE
1.1.2 DCDC0 (High current type)
less than 5mΩ
Analog
Power
Supply
Buffer
Power
Supply
VIN0
Cin_A
FBP
RCT583S
Control
and BUF
Analog
LH0
LL0
Cin_B1
LX
Cin_B2
L
Vout
Cout
RSO0
FBM
Analog
GND
Buffer
GND
less than 5mΩ
GND0
Fig.1-6: Simplified Schematic for DCDC0
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RC5T583S PCB LAYOUT GUIDE
VIN0 GND VOUT
(1) (1)
(2)
FET
(N)
L
FET
(P)
LX
RSCO0
Fig.1-7: Peripheral DCDC0 Evaluation Board Pattern 1
(1) Route the power supply for FET and GND at the lower resistance (RC5T583S: 5mΩ or less,
Figure 1-6: Blue line).
(2) Place the bypass capacitor of VIN0 for external FET as close as possible to the external FET.
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RC5T583S PCB LAYOUT GUIDE
VIN0 GND VOUT
LL0
L
LX
FBP
(4)
LH0
(3)
Fig.1-8: Peripheral DCDC0 Evaluation Board Pattern 2
(3) Route the LH0/LL0 gate signal lines to FET to become the low resistance and not to become in parallel
with a source of noise, such as a LX line.
In the case of the LX line as one example; Connect the Lx line to FET at the 8 th layer of the evaluation
board.
(4) Route the VFB (FBP) line not to become in parallel with the LX line and under the coil pattern.
In the case of the VFB line as one example; Route the VFB line for a feedback from output at the 5 th layer
of the evaluation board.
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RC5T583S PCB LAYOUT GUIDE
VIN0
(5)
Fig.1-9: Peripheral DCDC0 Evaluation Board Pattern 3
(5) Place a bypass capacitor as close as possible to the power supply pin (VIN0) for the internal buffer.
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RC5T583S PCB LAYOUT GUIDE
1.2 RTC Block
XIN
RC5T583S
XOUT
Rd
X'tal
Rx
C
1
C2
Fig.1-10: Simplified Schematic around crystal
(1)
(3)
(2)
(4)
Fig.1-11: Evaluation board pattern example. (Top Layer)
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RC5T583S PCB LAYOUT GUIDE
(1) Place the crystal unit as close as possible to the RC5T583S, the route the line on the single layer without
via as short as possible, and not add a redundant line like Monitoring Line.
(2) Place the input and output capacitors (C1 and C2 shown in Fig.1-11) as close as possible to the crystal
unit, in order to reduce the extra parasitic resistance and capacitance.
(3) Draw Land Patterns for Rx and Rd previously, because an adjustment by adding Rx and Rd is required
when the using oscillator exceeds its "Drive Level" specs.
(4) Connect the GND of the oscillation circuit with special GND plane on the component layer (Refer to the
Fig.1-11), and then connect with the internal GND plane by via or through hole. (Refer to the Fig.1-12)
Don’t route the sensitive line on the layer just under the oscillation circuit.
Also, do not place GND between pads of the oscillator to prevent a parasitic resistance.
(4)
Fig.1-12: Evaluation board pattern example (2nd Layer)
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RC5T583S PCB LAYOUT GUIDE
2. Recommended External Parts List
(*Maximum height: 3.0mm)
RC5T583S External Parts
Block Pin Name
Parts Size [mm]
Parts
Model No
Vender Num
X Size Y Size Z Size [mm2]
PMU - - RC5T583S RICOH 1 5.00 5.00 1.00 25.00
VBAT 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
Power VDDIO 0.1uF C0603JB0J104K TDK 1 0.60 0.30 0.30 0.18
VDDGP 0.1uF C0603JB0J104K TDK 1 0.60 0.30 0.30 0.18
ADC ADCVDD 0.1uF C0603JB0J104K TDK 1 0.60 0.30 0.30 0.18
VSB
1kohm P-RMC1/20-102FPA KAMAYA 1 0.60 0.30 0.23 0.18
1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
RTC
32K X'tal Q13FC135(32.768kHz, 9pF) EPSON 1 3.20 1.50 0.90 4.80
XOUT
13pF Anything - 1 0.60 0.30 0.30 0.18
XIN 13pF Anything - 1 0.60 0.30 0.30 0.18
VIN0
47uF C2012X5R0J476M TDK 2 2.00 1.20 1.25 4.80
2.2uF C1608X5R1A225K TDK 1 1.60 0.80 0.80 1.28
DCDC0
LH0 P-MOS CSD25401Q3 TI 1 3.30 3.30 1.00 10.89
LL0 N-MOS FDMA410NZ Fairchild 1 2.00 2.00 0.80 4.00
FBP 2.2uH SPM6530T-2R2M TDK 1 7.10 6.50 3.00 46.15
FBM 100uF AMK316ABJ107ML Taiyo Yuden 3 3.20 1.60 1.60 15.36
VIN2,VIN5 22uF GRM21BB30J226ME38 Murata 1 2.00 1.25 1.25 2.50
DCDC1 LX11,LX12 2.2uH LTF5022T-2R2N3R2-LC TDK 1 5.00 5.20 2.20 26.00
FB1 47uF C2012X5R0J476M TDK 1 2.00 1.20 1.25 2.40
VIN4 10uF GRM21BB31A106KE18 Murata 1 2.00 1.25 1.25 2.50
DCDC2 LX21,LX22 2.2uH VLS252015ET-2R2M TDK 1 2.50 2.00 1.50 5.00
FB2 22uF AMK107BJ226MA Taiyo Yuden 1 1.60 0.80 0.80 1.28
VIN6,VIN7 22uF GRM21BB30J226ME38 Murata 1 2.00 1.25 1.25 2.50
DCDC3 LX31,LX32 2.2uH VLF5014ST-2R2M2R3 TDK 1 4.80 4.60 1.40 22.08
FB3 47uF C2012X5R0J476M TDK 1 2.00 1.20 1.25 2.40
VIN8 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VIN9 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VIN10 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VIN11 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO0 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO1 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO2 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
LDO
VO3 4.7uF JMK105BBJ475MV-F Taiyo Yuden 1 1.00 0.50 0.50 0.50
VO4 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO5 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO6 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
VO7 4.7uF JMK105BBJ475MV-F Taiyo Yuden 1 1.00 0.50 0.50 0.50
VO8 4.7uF JMK105BBJ475MV-F Taiyo Yuden 1 1.00 0.50 0.50 0.50
VO9 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
REG18V 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
REFO 1uF GRM155B31A105KE15 Murata 1 1.00 0.50 0.50 0.50
TOTAL 189
Table2-1: External Parts list
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RC5T583S PCB LAYOUT GUIDE
Size IDC1(A) IDC2(A) DCR(mΩ) IOUTMAX
Item Maker L(mm) W(mm) T(mm) S(mm2) Typ typ typ Total (A)
SPM6530 TDK 7.1 6.5 3 46.15 8.4 8.2 17.3 17 9
SPM4012(1.0uH)×2 TDK 4.4 4.1 1.2 36.08 6 4.1 38 76 4
DCDC0 IHLP2525AHER(1.0uH+0.47u Vishay 6.47 6.86 1.8 88.77 14 7 17.5 26 11
IHLP2525AHER(1.0uH)×2 Vishay 6.47 6.86 1.8 88.77 14 7 17.5 35 11
IHLP2525AHER(0.47uH)×4 Vishay 6.47 6.86 1.8 177.54 18 11 8.4 34 20(AC)
LTF5022T-2R2N3R2-LC TDK 5 5.2 2.2 26.00 3.2 2.4 36 36 3
DCDC1 SPM4012T-2R2M TDK 4.4 4.1 1.2 18.04 4.4 2.7 82 82 3
DFE252012C TOKO 2.5 2 1.2 5.00 2.7 2.3 90 90 3
VLS252012MN-2R2M TDK 2.5 2 1.2 5.00 1.7 1.6 96 96 1.2
DCDC2 SPM4012T-2R2M TDK 4.4 4.1 1.2 18.04 4.4 2.7 82 82 1.2
DFE252012C TOKO 2.5 2 1.2 5.00 2.7 2.3 90 90 1.2
VLF5014ST-2R2M2R3 TDK 4.8 4.6 1.4 22.08 3 2.3 59 59 2
DCDC3 SPM4012T-2R2M TDK 4.4 4.1 1.2 18.04 4.4 2.7 82 82 2
DFE252012C TOKO 2.5 2 1.2 5.00 2.7 2.3 90 90 2
Table2-2: External Parts list
*IDC1…-30% Reduction from Normal L Value
*IDC2…self temperature rise(+40degC typ).
The following are guidelines to the select the inductor.
・"IDC1" is larger than Max Current(DC).
・It is better that "IDC2" is over the Max Current.
-> It is necessary to care the increasing temperature if load current is over IDC2.
・It is better that "DCR" is small.
-> In case of serial connection, the efficiency is dropping because DCR is increase.
3 Parts Place Example
This layout is one example of parts layout with RC5T583S
20.5 mm
L
L
7 mm
p-mos
C
C
C
C
C
C
C
C
L
C
n-
mos
C
C
C
C
11.2 mm
17.5 mm
RC5T583S
L
Xtal
L
3.4 mm
12.1 mm
5.1 mm
*PKG: BGA 5.0mm×5.0mm、0.5mmpitch、81pins
Fig3-1: Example of parts place
©2012 Page 15