Chip Scale Review - July 2007

ChipScale 

www.ChipScaleReview.com 

® 

r e v i e w 

July 2007 

• Lead-Free One Year After 

• Wafer Bumping

See us at SEMICON West, Booth #7358

CONTENTS 

The International Magazine of Chip-Scale 

Electronics, Flip-Chip Technology, Optoelectronics 

Interconnection and Wafer-Level Packaging 

July 2007 

Volume 11, Number 5 

THE COVER 

It’s time again for your humble cover scribe to apply 

his flying fingers to the keyboard and tell you about our 

magnificent July issue. By now, you have correctly identified 

the Golden Gate Bridge on our cover, (opened in 1937), 

which has become an icon for San Francisco, current home 

of SEMICON West. At the time, it was painted with a red 

lead primer and a lead-based topcoat. Far ahead of RoHS, 

the bridge scraped the lead off in 1965 and applied a zinc 

silicate primer and an acrylic topcoat of Sherwin Williams’ 

“International Orange.” The bridge’s conversion from lead 

to lead-free provides an outstanding segue into mention of 

the article by my favorite editor, Ron Iscoff. I just peeked at 

his article that looks at RoHS one year after. You don’t want 

to miss it! If you don’t know what RoHS is by this time, 

please confine your reading in future to Sports Illustrated 

or Playboy! Is RoHS merely an exercise in futility by a 

bunch of silly, frustrated Europeans with nothing better to 

do than munch on their braunschweigers and pate de fois 

gras, while hoisting a Heineken? La plume de ma tante—I 

don’t know! But I am pleased to refer you to Terry 

Thompson’s article and column. Terry is our senior editor 

and our “go-to” guy for MEMS. Don’t miss “MEMS the 

Word!” or his article on wafer-bumping tools and services. 

There is so much good stuff in this issue to tell you about, 

and so little space, that I’m beside myself with angst! 

See you at SEMICON West! 

(Illustration for Chip Scale Review by 

Design 2 Market) [design2marketinc.com] 

Chip Scale Review, at 7291 Coronado Dr., Suite 8, San Jose, CA 95129 

(ISSN 1526-1344), is published eight times a year, with issues in 

January-February, March, April, May-June, July, August-September, 

October and November-December. 

Periodical postage paid at San Jose, Calif., and additional offices. 

POSTMASTER: Send address changes to Chip Scale Review magazine, 

7291 Coronado Dr., Suite 8, San Jose, CA 95129. 

COVER FEATURES 

RoHS a Year After: Too Little, Too Late; 36 

Too Much, Too Soon—or Just Right? 

Ron Iscoff, Editor 

It’s been a year since RoHS became the hottest electronics industry buzzword 

since Chlorofluorocarbons. Although the European Union earmarked 

six hazardous substances for elimination in electronics, clearly the removal 

of lead from electronics was closest to the hearts of the EU commission. 

Where has RoHS gone? We’ll tackle that subject now. 

Wafer-Bumping Processes, Tools and Trends 

Terrence E. Thompson, Senior Editor 

Wafer bumping continues to make inroads into the IC packaging 

mainstream. As it does, the technology opens Pandora’s box: Should I 

bump my own wafers or send them to an experienced contractor? 

What technology should I use for bumping? This article might help 

you decide. 

International Directory of Wafer-Bumping Services 

Chip Scale Review Staff 

Single Device Tracking: A Cost-Benefit Analysis 

Dave Huntley, KINESYS Software 

42 

50 

55 

The acceptance and implementation of single device tracking has been 

made much easier with the release of SEMI standard E142. This article 

discusses how, when and why to implement this new standard on the 

assembly floor. 

Advances in Wafer Plating: Meeting the Next 61 

Challenge of Through-Silicon-Via Processing 

Bob Forman, Rohm and Haas Electronic Materials 

Copper electroplating has become a standard in electronics for making 

electrical interconnects between devices. A new packaging technology, 

using through-silicon-vias employs copper plating for high-density 

packaging at wafer level through chip stacking. 

Handling and Processing Technologies Utilized 69 

In a High-Volume Manufacturing Environment 

Stefan Pargfrieder, Paul Lindner, Steven Dwyer 

and Thorsten Matthias, EV Group 

As semiconductor manufacturers continue to squeeze the thickness 

of devices and wafers down, new and disruptive methods to meet the 

manufacturing challenges associated with new products and processes 

have to be utilized. 

CONTINUED >> 

Chip Scale Review ■ July 2007 ■ [ChipScaleReview.com] 1

The roadmap to opportunity 

starts here 

Electrolytic Wafer Bumping 

Electrolytic Copper 

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CONTENTS 

FEATURE ARTICLES 

Projection Scanning: Not a New Kid on the Block 

Jim Sooy 

75 

What’s the best photolithography tool for 

your wafer-level packaging applications? In 

this article we’ll take a close look at projection 

scanning and compare it to 1:1 wafer 

steppers and proximity alignment systems. 

From Cow Chips to Silicon Chips: Setting-Up a WLP 87 

Microfabrication Facility Far from the Infrastructure 

Fred Haring, Bernd Scholz, Syed Sajid Ahmad and Aaron 

Reinholz, Center for Nanoscale Science and Engineering, 

North Dakota State University 

Setting up a modern facility for wafer-level 

fabrication, chip-scale packaging and 

surface mount technology far from the center 

of semiconductor activity entails tough 

challenges and careful planning. This article 

relates some of the good, the bad and the 

Quasimodo-ugly experiences faced by the 

NDSU staff. 

Did You Know? Chip Scale Review is now offered in a 

digital format with a powerful search engine! 

DEPARTMENTS 

Publisher’s Letter Gene Selven 

Another great year For SEMICON and us! 

Assembly Lines Ron Iscoff 

Software radio: can you hear me now? 

MEMS the Word! Terrence E. Thompson 

What packaging hurdles do MEMS face? 

Electronic Trends Steve Berry and Sandra Winkler 

Wafer-level packaging with a twist 

Industry News 

Profile: TTS Group (Advertorial) 

Product Showcase (Advertisement) 

What’s New! 

Inside Patents A. Jason Mirabito and Carol Peters 

How to file patents (and fight patents) without tears! 

Calendar 

Ad Index/More News/Sales Offices 

4 

7 

9 

13 

15 

80 

81 

82 

85 

99 

104 


PUBLISHER’S LETTER 

Another Great Year 

For SEMICON and Us! 

By Gene Selven, Publisher [gselven@aol.com] 

The SEMICON West exposition in San Francisco this year will feature 1300 

exhibitors—including Chip Scale Review. During the show, we’ll distribute 

thousands of extra copies of this magazine to show visitors from our booth, 

W2-8717, and from racks in Moscone Center’s West Hall. 

Forgive us for tooting our own horn, but our SEMICON West issue—the one you’re 

reading right now—has about 25 percent more advertisers than we carried in last 

year’s show issue! 

We’ve mailed about 26,000 copies, and our digital edition will be read by an estimated 

additional 10,000 people worldwide. 

By the way, did you know that Chip Scale Review is the leading magazine for the IC 

assembly and packaging community? What do we mean by “leading”? 

• More editorial pages on an issue-by-issue basis than our nearest competitor. 

• More staff-written editorial pages on an issue-by-issue basis, more than twice as many! 

• More advertising pages in every issue—and this is where the “rubber meets the 

road” for a publication, since it shows the faith our advertisers have placed in us! 

• Two key editors with a combined total of 50 years in the semiconductor industry, 

creating a magazine of editorial excellence! 

The company that publishes the number two magazine in the field has 40 other magazines 

in such areas as oil and gas, dentistry, graphic arts, electrification, etc., plus a multitude 

of conferences in those areas. 

We have one magazine, this one; a newsletter, The TUESDAY REPORT; and one conference, 

our International Wafer-Level Packaging Conference in September. We don’t have to worry 

about what the corporate nabobs in Tulsa want. The buck stops right here—with me. 

Decisions are made in Silicon Valley, the capitol of semiconductor technology since the beginning. 

We’re dedicated to publishing the best magazine for IC assembly and packaging 

available. That is our continuing goal, and that is our mission. And our advertisers and 

readers, by making us #1, have shown that we’re succeeding. 

Report from ECTC 

I recently returned from the 57th Electronic Components and Technology Conference 

(ECTC) in Reno, Nevada. 

ECTC continues to be a “must-see” conference that provides a dynamic environment 

for learning, discussion and networking the technology. 

We were, by the way, the only publication whose publisher was on site. We spoke to 

about 60 exhibitors, many of whom will also be at SEMICON West. 

Our congratulations to the ECTC participants and staff for an outstanding event! i 

4 

Chip Scale Review ■ July 2007 ■ [ChipScaleReview.com] 

VOLUME 11, NUMBER 5 

The International Magazine of Chip-Scale 

Electronics, Flip-Chip Technology, Optoelectronic 

Interconnection and Wafer-Level Packaging 

STAFF 

Gene Selven Publisher 

7291 Coronado Dr., Ste. 8, San Jose, CA 95129 

b 408.996.7016 > 408.996.7871 

gselven@aol.com 

Ron Iscoff Editor & Associate Publisher 

929 Ebbetts Ave., Manteca, CA 95337 

b 209.824.1289 > 209.644.7747 

chipscale@gmail.com 

Terrence Thompson Senior Editor 

2303 Randall Rd. #140, Carpentersville, IL 60110 

b 847.515.1255 

tethompson@aol.com 

Steve Berry Contributing Editor 

b 408.369.7000 > 408.369.8021 

saberry@electronictrendpubs.com 

Dr. Tom Di Stefano Contributing Editor 

b 408.399.4501 > 408.395.0448 

tom@centipedesystems.com 

Dr. Subash Khadpe Contributing Editor 

skhadpe@semitech.com 

Harvey S. Miller Contributing Editor-at-Large 

b 650.328.4550 > 650.327.2360 

h.miller@ieee.org 

Paul M. Sakamoto Contributing Editor–Test 

b 925.924.9110 x148 

paul.sakamoto@inovys.com 

Sandra Winkler Contributing Editor 

b 408.369.7000 > 408.369.8021 

slwinkler@electronictrendpubs.com 

The Official Publication of the WLCSP Forum 

SUBSCRIPTION INQUIRIES 

Judy Levin Chip Scale Review 


b 408.996.7016 > 408.996.7871 

csrsubs@chipscalereview.com 

ADVERTISING PRODUCTION 

INQUIRIES 

Kim Newman 


b 408.996.7016 > 408.996.7871 

csradv@aol.com 

REPRINTS 

Kim Newman b 408.996.7016 

8 csradv@aol.com 

ADVISORS 

Mark DiOrio MTBSolutions 

Dr. Tom Di Stefano Centipede Systems 

Charles R. Harper Technology Seminars Inc. 

Mark Murdza Antares Advanced Test Technologies 

Dr. Guna Selvaduray San Jose State University 

Dr. Thorsten Teutsch Pac Tech 

Dr. Dietrich Tönnies SUSS MicroTec AG 

Dr. David Tuckerman Tessera Technologies 

Professor C.P. Wong Georgia Tech 

Copyright © 2007 by Gene Selven & Associates Inc. 

Chip Scale Review (ISSN 1526-1344) is a registered trademark 

of Gene Selven & Associates Inc. Publishing headquarters are 

located at 7291 Coronado Drive, Suite 8, San Jose, CA 95129. 

All rights reserved. 

Chip Scale Review is published eight times a year. 

Subscriptions in the U.S. are available without charge to 

qualified individuals in the electronics industry. Subscriptions 

outside the U.S. (eight issues) by airmail are $60 per year to 

Canada or $60 to other countries. In the U.S., subscriptions 

by first class mail are $40 per year.

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Umicore: a good joint keeps its promise!

ASSEMBLY LINES 

Software Radio: Can You Hear Me Now? 

By Ron Iscoff, Editor [chipscale@gmail.com] 

Unlike “normal” people, 

editors live in issue years. 

When it’s May, which it is 

now, we’re thinking of July. When it’s 

August, we’ll be thinking of December, 

or earlier or later, depending on when 

our next issue is printed. 

Too bad everyone doesn’t think like we 

do. If they did, no one would ever be late! 

When you read this, SEMICON West 

will be almost a memory—a good, bad 

or indifferent one, depending on your 

point of view and your business. 

At this point, many of you may be 

soaking your feet in Epsom salts as you 

wait for your corns and calluses to enjoy 

the sweet relief from Moscone’s hard, 

concrete floors. 

Still Lamented 

Even after all these years, I still lament 

the loss of the San Mateo County Fairgrounds, 

SEMICON West’s original venue 

(and one that was only about two miles 

from my house). 

For my colleagues who are becoming 

somewhat long in the tooth like me— 

and you know who you are—I have a 

pop quiz for you: What “things” were 

the buildings at the San Mateo County 

Fairgrounds named after? Can you 

name four of them? You’ll find the 

answers at the bottom of this page. 

Sadly, Moscone has taken the easy 

way out: The buildings are either North 

Hall, South Hall or West Hall. 

Last year after the show, I suggested 

that the Powers that Be (PtB) at Moscone 

rename the halls after famous people. I 

suggested “Homer Simpson Hall,”“Spartacus 

Hall,” and “Venus de Milo Hall.” 

I won’t even go into further details, 

since the PtB appear to have disregarded 

my well-meaning suggestions. 

In my next column, I’ll be thinking 

out loud again. And we will both have 

benefited because SEMICON West will 

be over for another year. 

One possible question I will address 

may be, “Is SEMICON West now an 

antiquated albatross with algae-like 

detritus dangling from its oral cavity?” 

I hope to see you (or hope I saw you 

at Moscone). If not, I guess it was karma. 

Sin City Follies 

As we reported earlier, APEX has abandoned 

The City of the Angels, Los Angeles, for 

Las Vegas, the City of What? I’ve been to 

Vegas a few times over the years, but I 

leave the gambling to my better fraction. 

APEX, however, is betting that Vegas 

will bring the magic touch to its conference—magic 

that’s been on the wane. 

Appropos Vegas, as philosophers have 

pointed out, you don’t build multimillion-dollar 

casinos like New York, 

New York or Mandalay Bay from the 

contributions of winners! 

SEMI itself, which is getting as long 

in the tooth as I am, has made guttural 

noises from time-to-time about moving 

the whole SEMICON West kit-n-kaboodle 

to Sin City. From what I understand, 

that’s still a possibility over the long 

term. 

Photo taken at last year’s SEMICON West shows 

Homer Simpson Hall (at left, formerly North Hall) 

and Venus de Milo Hall (formerly South Hall). 

Free for All 

Seriously folks, how often do you get 

something valuable free? I don’t mean 

the samples of Grandma’s Tortilla Dip 

that they hand out at Costco while you’re 

heading for the bread aisle. I mean something 

really good for you! 

Well, it’s here now. Dr. Ken Gilleo, 

that witty inventor, chemist, litigation 

consultant, MEMS 

expert, public 

speaker, mime, 

scrivener, multicoastal 

manabout-Rhode 

Island and manamong-men 

(and 

Get your free download these are only a 

of Ken Gilleo's book! few of the glowing 

descriptions he 

uses in his own bio!) will let you download 

his latest book, The Day Niagara 

Falls Turned Green, free! 

Continued on page 101 >> 


MEMS THE WORD! 

What Packaging Hurdles Do MEMS Face? 

By Terrence E. Thompson, Senior Editor [tethompson@aol.com] 

Will MEMS (microelectromechanical 

systems) play 

nice with ICs and what 

packaging hurdles lie ahead? Are they 

candidates for wafer-level packaging? 

Let’s look at the facts: 

One of the most exciting, and frustrating, 

aspects of grasping the MEMS 

market share is the incredible rate of 

adoption in dozens, probably hundreds, 

of industries. Industry groups such 

as the MEMS Industry Group (MIG) 

in Pittsburgh, Pa. do an excellent job 

of tracking progress. 

[memsindustrygroup.org] 

A Better MEMS Product 

Those incredibly small MEMS, and 

their nanoscale NEMS counterparts, are 

increasingly fulfilling needs that complement 

ICs, not replacing them. 

In some cases, ICs were small enough 

for many sensor, medical and other 

applications, but were in need of equally 

Sensors are a major application area for MEMS. 

(Bosch Sensortec GmbH) 



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ELECTRONIC TRENDS 

Wafer-Level Packaging with a Twist 

By Steve Berry, Contributing Editor [saberry@electronictrendpubs.com] and 

Sandra Winkler, Contributing Editor [slwinkler@electronictrendpubs.com] 

Wafer-level packages (WLPs) 

are IC packages created on 

full wafers, rather than on 

individual die. Thus, WLPs have the distinction 

of being truly die-sized. 

WLPs are ideal for handheld products 

which require small form factors and 

light weight. 

However, because they are die-size, 

WLPs are not a standard size. Fortunately, 

many handheld products frequently 

change the design, which lessens the 

impact when the package size shrinks 

after a die shrink. 

Benefits of a WLP 

Given that WLPs are created on the face 

of the die, they boast the shortest electrical 

path. Because WLPs are a tested part 

when completed, the devices can also be 

used in modules as known good die. 

In addition to excellent electrical performance, 

reduced cost is a driving 

force behind wafer-level packaging. The 

cost for packaging the devices on a 

given wafer does not change with the 

number of die per wafer; generally, all 

processes are additive and subtractive 

steps performed with mask steps. 

As a result of the benefits of WLPs, 

their numbers will continue to grow 

rapidly, as illustrated in the figure. 

Where Are WLPs Found? 

IC products that contain WLPs include 



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Contact Honeywell for solutions to your puzzle… 

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© 2007 Honeywell International Inc. All rights reserved.

INDUSTRY NEWS 

Singapore’s Flextronics to Acquire 

Solectron, Milpitas, for $3.6 Billion 

Singapore—The shrinking world of EMS 

providers will become smaller still with the 

proposed acquisition of giant Solectron, 

Milpitas, Calif., by competitor Flextronics, 

Singapore. 

The acquisition has already been approved 

by both boards. Flextronics will pay $3.6 

billion, based on the June 1 closing price of 

the company’s common stock. 

SEMICON West XXXVII 

Our Annual Rite-of-Passage 

‘Glory Days’ Are Gone! 

“No surprise there! The glory days of non- 

Asia-based EMS companies such as 

Solectron are long gone,” said Dr. Subash 

Khadpe, president of the Semiconductor 

Technology Center, Neffs, Pa., responding 

to the acquisition news. 

“The future is with Hon Hai Precision 

(Foxconn), Flextronics, et al.” 


Panasonic’s Grand Opening 

Was Truly a First-of-Its-Kind 

Buffalo Grove, Ill.—Attendance exceeded 

160 on June 7, when the doors opened to 

Panasonic’s new Advanced Packaging Lab 

for Microelectronics, a significant event 

for North American chipmakers and electronics 

designers and producers. 

Panasonic Factory Solutions Co. Ltd. 

(PFSC) President Katsutoshi Kanzaki, and 

Director Neal Okuda of Panasonic Factory 

Solutions Co., Osaka, 

Japan, handled the 

opening remarks. 

PFSC has long been a 

major player in IC 

package development, 

and now it’s opening 

the new lab to those 

Gene Dunn 


INSIDE NEWS 

• SEMI Says Q1 Billings for Equipment Reached 

$10.75 Billion page 104 

This is a view looking down from the escalator in the second floor of West Hall, the newest 

building at Moscone Center. (Chip Scale Review) 

By Ron Iscoff, Editor 

San Francisco—SEMICON West, the semiconductor equipment industry’s 

annual rite of passage in July is upon us. 

When you hear someone say, en passant, “This will be my first SEMICON 

West.” You can’t contain a secret snicker; an ungracious chortle, way down 

deep in your throat; you know you can’t! It is, to crib a line from Charles 

Dickens’ Tale of Two Cities, “The Best of Shows, the Worst of Shows!” 



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INDUSTRY NEWS 

SEMICON West Continued from page 15 >> 

A person’s first SEMICON West is a 

rite akin to a Bar Mitzvah held in the sandy 

trenches of the Gaza Strip with artillery 

rounds buzzing overhead; or a Baptism 

conducted on a burning funeral pyre in 

the humanity-swollen Ganges River. 

I have been to more SEMICON West 

shows than I have fingers and toes, a lot 

more. This will be the thirty-seventh 

running of this nearly indescribable 

event, which means the first—which I 

did not attend—took place in 1970. 

The Fairgrounds Remembered, Fondly 

In past issues, we have repeated our fond 

recollections of SEMICON West at the 

San Mateo County Fairgrounds. 

We have also noted our many trips to 

the Convention Center in San Jose to 

observe the shenanigans of the backend 

equipment displays; and we have intermittently 

chided our good friends at 

SEMI for the continuing on/off San 

Francisco agglutination. 

We will, as we have done for lo these 

many years, give you our impressions of 

SEMICON West XXXVII in due course, 

after the show is finished, the lights 

turned off at Moscone, and the displays 

placed in moth balls for another year. 

But this year, I decided to let you tell 

me how you feel about SEMICON West. 


THERE ARE NO SHORTCUTS 

TO A 5-MIL DOT 

Micro-volume dispensing requires three core 

technologies. Without them, you can forget 

about accurate volumes and placement: 

• DL Micro Valve with brushless 

servo motor dispenses micro 

volumes of material in precise, 

repeatable patterns. 

This was the way it looked, circa 1985, from outside 

the Fairground gates. (SEMI photo) 

Flextronics Continued from page 15 >> 

Combined, the companies will operate 

in 35 countries with a workforce of 

200,000, which includes about 4000 

design engineers. 

Total annual revenues are expected to 

exceed $30 billion. 

In its news release, Flextronics’ CFO 

is quoted as saying, “While some synergies 

will be achieved in the first 12 months 

after closing, it could take up to 18-24 

months to fully integrate this acquisition 

and realize the full synergy potential, 

which we estimate to be at least $200 

million after-tax.” 

Flextronics reported fiscal year 2007 

revenues of $18.9 billion. Solectron 

reported sales from continuing operations 

in fiscal 2006 of $10.6 billion. 

[flextronics.com] ■ 

• DL carbide auger and cartridge 

combine for exceptional material 

flow. Easily extracted for 

rapid cleaning. 

For dot sizes less than 10-mil, there is one 

product line that is proven and trusted – 

by manufacturers in semiconductor packaging, 

electronics assembly, medical device, and 

electro-mechanical assembly the world over. 

R 

• DL custom dispensing needles 

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facilitates material release. 

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Phone: 978-374-6451 

Fax: 978-372-4889 

www.dltechnology.com 

Micro Valve is a trademark of DL Technology LLC. DL Technology is a registered trademark of DL Technology LLC. 


INDUSTRY NEWS 

Corona, Calif.—Ron Sheets, Tamarack 

Scientific founder, 

president and CEO, 

has retired after 41 

years. He will be 

replaced as president 

and CEO by Steven 

Thompson,former 

vice president of 

Steven Thompson engineering. 

PEOPLE IN THE NEWS 

Tamarack Scientific Founder Retires; Promotes Thompson and Souter 

Thompson, who joined the company 

27 years ago, has been in charge of engineering 

for development of the company’s 

photolithography and laser ablation 

systems. 

Matt Souter, who joined the company 

six years ago, has been promoted to vice 

president of sales and marketing. 

In a letter to customers, Sheets wrote, 

“While I may be stepping back from the 

JCET Establishes North American Operations in California 

Fremont, Calif.—Jiangsu Changdian 

Electronics Technology Co., (JCET), 

and its subsidiary, Jiangsu Changdian 

Advanced Packaging Co., (JCAP),have 

established operations in Fremont. 

Dr. Weiping (Bill) Li is the general 

manager and is tasked with sales and 

marketing activities for North America. 

Founded in 1972, JCET/JCAP is the 

leading packaging provider in China, 

According to Dr. Li. 

In the last five years, the company has 

grown about 30 percent CAGR, with 

2006 revenue reaching $240 million. 

JCET’s Fremont office is at 41341 

Joyce Ave., Fremont, CA 94539, phone 

510.573.3612. [jcet-us.com] 

day-to-day management 

of Tamarack, I 

will continue to pursue 

my passion— 

developing creative, 

best-in-class equipment 

that satisfies 

our customers’ 

needs.” [tamsci.com] 

Matt Souter 

Farrell Replaces Conlon as 

CEO of XSIL Ltd., Dublin 

Dublin, Ireland—Brian Farrell has 

replaced Peter Conlon as CEO of XSIL 

Ltd., a maker of laser micro-machining 

systems. Conlon has assumed the company’s 

chairmanship. 

Farrell is an XSIL founder and has 

been vice president of engineering since 

the company began in April 2000. 

[xsil.com] 

SuperButton and SuperSpring Contact Elements 

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• Mating against BGA, LGA, QFN, CSP or flex 

sales@hcdcorp.com www.hcdcorp.com (408) 743-9700 x331 

Copyright © 2006 High Conection Density, Inc. All rights reserved. Information is subject to change without notice. “SuperSpring” and “SuperButton” are trademarks of High Connection Density, Inc. 

18 

Chip Scale Review ■ July 2007 ■ [ChipScaleReview.com]

We keep it real. 

Not all vision inspection is created equal. 

Especially when it comes to 3D. Some 

technologies emphasize speed, while others 

focus on accuracy. 

But SolVision’s 3D is the real deal. 

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Just true 3D metrology and inspection 

at industry-leading throughputs. 

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And keep the competition guessing. 

WAFER • IC PACKAGING • FC SUBSTRATE 

VISIT US AT SEMICON WEST 2007 

JULY 17-19, MOSCONE CENTER, SF 

BOOTH 8527 • WEST HALL • LEVEL 2 

Global Headquarters 

50 De Lauzon Street, Suite 100 

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T: 514.679.9542 

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E: sales@solvision.net 

SolVision Singapore 

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T: +65 6759.8858 

F: +65 6755.2272 

E: sales-asia@solvision.net 

© 2007 SolVision inc.

INDUSTRY NEWS 

Panasonic Continued from page 15 >> 

seeking device packaging and inspection 

systems guidance. 

Panasonic is a huge company with 

over 320,000 employees in the group! 

Impressive Talent 

That is an impressive amount of talent 

to back-up any effort, existing or new. 

When we hear Panasonic say the new 

U.S. process lab is unmatched anywhere, 

you have to believe they are serious. 

In May 2007, Panasonic opened a 

process lab in Germany in collaboration 

with Fraunhofer IZM. They also have 

labs in Japan and Singapore, but the 

North American lab is said to be the 

Cutting the ribbon for the new lab are, left to right, 

Neal Okuda, director of Panasonic Factory Solutions 

Co. (PFSC); President Katsutoshi Kanzaki, PFSC; 

Frank Barney, marketing and communications group 

manager, Panasonic Factory Solutions Co. of America; 

Bill Brimm, Buffalo Grove Village manager; and Alex 

Shimada, president, PFSCA. (Panasonic photo) 

most comprehensive yet. 

Genn Dunn, PFSA engineering manager 

for microelectronics, was as proud 

of the lab as a new father. 

He said, “Because the cleanroom is 

complete with state-of-the-art equipment, 

we’re able to offer customers a hands-on 

experience for developing truly productive 

microelectronics product systems. 

For the first time in North America, 

customers can qualify their samples on 

high-volume production equipment, 

not semi-automatic tools.” 

Partnership Approach 

Dunn stressed Panasonic’s partnership 

approach for anyone who needs to 

develop a chip package 

and/or verify 

process integrity. 

Unlike the usual 

grand openings, this 

one had unusual 

depth. We heard 

some excellent technical 

presentations Jan Vardaman 

on packaging topics, 

including “New Developments and 

Trends in SiPs” by Jan Vardaman, 

TechSearch International; “Package 

Stacking: The Next Dimension in 

System Board Design” by Moody Dreiza 


20 


SENJU SOLDER 

Working to Make Lead-Free Virtually 

“Pain-Free” 

Senju Comtek Corp. 

20300 Stevens Creek Blvd. #300 

Cupertino, CA 95014 

phone: (408) 446-7866 fax: (408) 253-2140 

email: sales@senjucomtek.com 

www.senjucomtek.com 

SMIC 

Senju Comtek Corp.

INDUSTRY NEWS 


Japanese sawing machine giant Disco occupied a prominent spot in West Hall at last year’s SEMICON West. 

Of course, you’ll be telling SEMI, too. 

Exactly to that end, I sent out many, 

many e-mails to people in the industry 

whom I know and people whom I 

don’t. I was surprised at how quickly 

responses starting coming back. 

I also asked people how they felt 

about SEMICON West moving to Las 

Vegas. This has been a backburner item 

at SEMI for at least a decade. Vegas 

draws certain people like a moth to a 

flame. (And you know what happens 

when a moth is drawn into a flame!) 

APEX, as you probably know by now, 

has abandoned Los Angeles after one 

year and will meet in Vegas next year. 

Is the same fate in store for SEMICON 

West? 

Love/Hate Relationship 

Most of us have a love/hate relationship 

with SEMICON West. Why is that? I 

wondered. Since I didn’t know the 

answer, I decided to consult a doctor. 

Dr. Phil was not available, so I immediately 

thought of Dr. Ken Gilleo, chemist, 

MEMS specialist, bon viver and author 

of many books. Dr. Ken responded: 

We in the Boston area are clueless 

about West Coast stuff. Some think that 

everything west of the Mississippi is just 

grand. Others are sure that there’s nothing 

but wasteland once you get past Lake 

Woebegone. 

I’ve always had a good time at SEMICON 

West and didn’t know there was a bad 


Panasonic Continued from page 20 >> 

of Amkor 

Technology, and 

“Case Studies in 

Electronics Assembly 

Solutions” by Tom 

Baggio of Panasonic 

Factory Solutions 

America. 

Moody Dreiza I left the grand 

opening convinced 

that PSFC was both serious and capable 

of delivering microelectronics solutions 

from chips to wafers. 

It is clear Panasonic, with its own systems 

and those of partners, is addressing 

the needs of board-level through IC 

and wafer-level device packaging. 

The grand opening ceremony included 

the annual joint meeting of trade organizations 

IMAPS Chicago/Milwaukee and 

SMTA Great Lakes. [panasonicfa.com] ■ 

–Terry Thompson, Senior Editor 


INDUSTRY NEWS 

Amkor and UTAC Sign Cross-License Contract 

Workers at Amkor’s Pudong, China, factory inspect leadframes. Amkor and UTAC have agreed to crosslicense 

each other on certain package types. (Amkor Technology Inc.) 

Chandler, Ariz.—Amkor Technology 

Inc., Chandler, and United Test and 

Assembly Center Ltd. (UTAC), 

Singapore, have signed a multi-year, 

package cross-licensing agreement. 

Amkor will license its MicroLeadFrame 

(MLF) patents to UTAC and UTAC will 

license its QFN patents to Amkor. 

The contract covers the licensing of 

intellectual property rights and the 

transfer of associated packaging technologies. 

The MLF package is Amkor’s version 

of a QFN leadframe-based, near-chipscale 

package. The package features an 

exposed die paddle and leads on the 

bottom. 

Amkor says it has shipped about five 

billion MLF packages since their introduction 

in the late 1990s. [amkor.com] 


side. Well, maybe the long walk between 

the front end and backend of the line is 

an issue unless you have a golf cart. Or 

did they every figure out how to merge 

the two ends? 

Their website was semi-disabled when 

I went to check if it was still a two-town 

event. Maybe everyone was surfing the 

site on a Sunday afternoon, but let’s hope 

not, so it looks like I did find something 

to rap about: low bandwidth, or corrupted 

scrip or whatever. Maybe the site is only 

accessible using San Francisco Wi-Fi. 

But if the front end and backend shows 

have not yet merged, there’s a solution on 

Gregg Taran (left) and Helmut Rutterschmidt of 

Datacon, were among major SEMICON West exhibitors 

in West Hall last year. (Chip Scale Review) 

the way. As Wafer-Level Packaging (WLP) 

takes over, the front and backend processes 



INDUSTRY NEWS 


will merge and that should simplify 

SEMICON West. 

These responses, for the most part, 

have only been edited when someone 

became too long-winded or profane; 

otherwise, they are verbatim. 

From Newport News, Va., on our great 

Eastern shores, Gerald Steinwasser of 

equipment-maker and SEMICON West 

exhibitor Mühlbauer [muhlbauer.com], 

wrote: 

In my opinion, it was a mistake to 

“re-unite”’ the backend in SF. The heart 

of the semiconductor industry is in the 

valley, and that’s where the show belongs. 

A move to Las Vegas would only help the 

city of Las Vegas, but not the industry or 

SEMICON West. 

From the Midwest, Mike Fedde, 

president of Ironwood Electronics 

[ironwoodelectronics.com], one of our 

favorite test and burn-in socket makers, 

e-mailed: 

Attendees found the lounges outside the second and third floors of West Hall provided a spot to relax and 

meet colleagues. (Chip Scale Review) 

Don’t move to Vegas, please. We 

already have trouble getting customers to 

come. None will be in Vegas—they are 

engineers. Love/hate info maybe later. 

We know our pal, Dr. Skip Fehr, packaging 

consultant extraordinaire in San Jose, 

is always good for a comment, so he was 

one of the first people we contacted. And 

he didn’t disappoint this time either: 

Why I like SEMICON: It is a chance to 

see the new products in a short period 


26 


INDUSTRY NEWS 

Rohm and Haas Opens New Korean R&D Center 

Company executives and local officials cut the ribbon dedicating the new Rohm and Haas Electronic 

Material Chonan, Korea, Research and Development Center. Participants at the Center’s grand opening were, 

from left: H.S. Chung, president, Rohm and Haas Electronic Materials Korea; I.H. Lee, GM; Y.H. Kim, GM, 

Samsung Electronics; S.C. Moon, director, Hynix; Y.H. Kwon, deputy mayor of Chonan City; J.S. Lee, Chonan 

fire station; J.H. Park, director, Chonan customhouse; and G.H. Kwag, plant manager, Rohm and Haas 

Electronic Materials. 

Chonan, Korea—Rohm and Haas 

Electronic Materials has opened a new 

five-story R&D Center in Chonan in 

west S. Korea. 

The Center represents part of a recent 

$30 million expansion of the company’s 

Microelectronic Technologies site in 

Chonan. 

Among other tasks, the Center will 

perform research on 193-nm photoresists 

as well as organic and silicon-based 

anti-reflectants. Now in place, according 

to the company, are 193- and 248-nm 

lithography clusters, as well as leadingedge 

defect and metrology tools. 

Further growth of the R&D and engineering 

resources will continue throughout 

the year, as Rohm and Haas ramps 

to meet local and global demand for 

next-generation semiconductor materials. 

[rohmhaas.com] 


of time, particularly those I do not 

presently use. My normal vendors keep 

us informed, but the others (of course) 

do not. A second reason is that of meeting 

and talking to people that I usually see 

only at the shows. It’s a great chance to 

renew relationships. I always hope to find 

that one new product or vendor that 

makes being at the show worthwhile. 

Why I dislike the SEMICON show: The 

biggest issue for me has always been the 

parking. If you don’t get to the show 

early, the spaces are full and it is difficult 

to find a place. I have not found the buses 

Klaus Ruhmer (left) of SUSS MicroTec talks with 

Fernando Mendez of Image Technology at last 

year’s SEMICON West. (Chip Scale Review) 

they furnish to be handy enough, 

although many do use them. I think the 



INDUSTRY NEWS 


organizers do a great job once you are in 

the show. 

Heck No! We Won’t Go (to Vegas)! 

Skip also voted against moving the 

show to Vegas, as did most people. 

Lonny Plummer of Kinesys Software 

[kinesyssoftware.com], is content having 

the show in San Francisco. 

“No” on the move to Vegas; stay in 

SFO,Lonny says. 

I hate that it has become such a business 

and that the show seams to be more 

focused on making a dollar than a showcase 

for the companies that exhibit. I have 

been going to the show for 25 years and 

the days of the meadowlands were the 

best in terms of focus and results, when 

equipment venders actually sold 

machines at the show. 

That time has come and gone. Now the 

show has evolved or degraded into a meetand-greet 

for venders. The level of actual 

Joel Camarda visited the Antares Advanced Test Technologies booth to discuss sockets with Selina Gonzales. 

customers coming to the show to see new 

technology in the backend is very limited. 

I love the show because it is in SFO 

and it is a great time out to meet and 

spend some time with old friends. 

Martin Hart, president of Mirror 

Semiconductor Inc. [mirrorsemi.com], 

in Irvine, Calif., admits to being a 

“betweener.” 


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Internet: www.muehlbauer.de 

28 


INDUSTRY NEWS 

Forecast Predicts IC Unit Shipments Will Grow by 9.5% CAGR 

San Jose—Industry analyst Electronic 

Trend Publications predicts IC unit 

shipments will grow from 137 billion 

last year to 216 billion units in 2011, a 

compound annual growth rate (CAGR) 

of 9.5 percent. 

Additionally, revenue growth should 

nearly equal unit growth from 2006-2011, 

as long as the industry is cautious about 

adding capacity. 

The forecast is made in ETP’s annual 

Worldwide IC Packaging Market study, 

which also predicts CSPs—including DFNs, 

FBGAs/DSBGAs, QFNs and wafer-level 

packages—will show the highest growth 

rates over the forecast period. 

The report also predicts total IC 

assembly revenue, based on the estimates 

of independent packaging 

foundries. 

If all packages 

had been 

assembled by 

non-captive 

vendors, total 

assembly revenue 

would 

have been $27 

billion in 

2006. This 

will expand, 

ETP says, to 

nearly $41 

billion by 

2011, a CAGR of 8.4 percent. 

Revenue growth for IC packaging, 

however, will trail unit growth over the 

next five years, ETP believes, because 

competition between vendors will push 

ASPs down slightly. 

‘Solid Increase’ in Units 

Some 43.8 billion ICs were assembled 

by packaging foundries last year, ETP 

estimates, representing a “solid increase” 

from 2005. With overall IC volume up 

sharply since the 2001 recession, contractors 

have become “very busy again.” 

IC packaging revenue was pegged at 

$10 billion in 2006 by ETP. This figure 

will grow to $19 billion in 2011, a 

CAGR of 13.3 percent. This is slightly 

above package unit growth. 

Much of the recent packaging 

foundry volume increases have been in 

low-I/O packages. Future growth, says 

ETP, should “show a slight increase in 

average I/O count” and ASPs. 

Last year, independent packaging 

foundries were responsible for some 32 

percent of the world’s total packages, 

nearly 44 billion, essentially unchanged 

from 2005. 

ETP predicts that contractor volumes 

Forecast by Package Family 

Units (M) 2006 2007 2008 2009 2010 2011 CAGR 

DIP 7830 7928 8531 8513 8896 9905 4.8% 

SOT 13,870 14,103 16,013 17,076 19,167 21,532 9.2% 

SO 35,965 36,123 38,605 38,947 41,979 45,811 5.0% 

TSOP 17,926 18,419 19,576 18,798 19,757 20,741 3.0% 

DFN 3143 3814 5134 6168 7575 8911 23.2% 

CC 865 847 798 692 640 696 -4.3% 

QFP 13,267 14,017 15,334 15,570 17,111 18,771 7.2% 

QFN 6594 8102 10,202 11,748 14,062 16,401 20.0% 

PGA 147 151 150 147 151 155 1.0% 

BGA 10,725 11,890 13,615 14,115 15,539 17,063 9.7% 

FBGA/DSBGA 14,590 17,521 21,055 23,332 27,245 31,261 16.5% 

WLP 3649 3909 4898 6010 7448 9814 21.9% 

DCA 8790 9981 11,628 12,158 13,410 14,807 11.0% 

Total 137,361 146,807 165,538 173,273 192,979 215,866 9.5% 

(Source: ETP) 

will grow to 78 billion packages in 2011, 

or 36 percent of the total, a CAGR of 

12.3 percent. 

The report says recent business outcomes 

of various packaging foundries 

show there are three keys to success: 

1. A broad package portfolio; 2. An 

extremely lean cost structure; and 3. 

Close relations with major wafer 

foundries and IDMs. 

[electronictrendpubs.com] 

Dage Precision Industries Names New Sales Rep 

Fremont, Calif.—Dage Precision Industries has appointed Electronic Assembly Products Inc. to represent 

its x-ray inspection systems and bond test equipment throughout Colorado, Utah and Costa Rica. 


INDUSTRY NEWS 


SEMICON West is a conundrum. I am 

a “betweener,” and I neither love, nor hate 

SEMICON West. So why should my 

opinion be heard? Am I just one of the 

silent majority, who cringes each year and 

is numb from the discomfort of having to 

deal with flying into SFO and Moscone 

Center? If forced to vote between San 

Francisco in July and the heat of Las 

Vegas in July, I would opt to continue 

with San Francisco. 

Of course, if you were to tease me with 

the prospect of returning the “backend” 

exhibits to their recent home in San 

Disco and Synova Join on Hybrid Singulation Saw 

Lausanne, Switzerland—Swiss manufacturer 

Synova says it will co-develop a 

hybrid dicing tool with Disco Hi-Tec 

Europe, Munich, Germany, a subsidiary 

of Japan’s Disco Corp. 

The companies will combine Synova’s 

patented Laser MicroJet technology with 

Disco’s newest blade-saw dicing systems 

to develop a hybrid dicing tool. 

The resulting saw, according to the 

companies, “will enable semiconductor 

manufacturers to meet their dual need 

for higher throughput and minimal 

damage to silicon wafers.” 

The initial tools are scheduled for 

introduction late this year. 

Both companies will contribute to the 

manufacturing of the hybrid saw and 

will share marketing and sales tasks. 

Synova’s technology combines a laser 

beam and a water jet, where a hair-thin wafer 

jet guides the laser beam onto the wafer. 

Employing the difference in the 

refractive indices of air and water, the 

technology creates a laser beam that is 

completely reflected at the air-water 

interface, similar in principle to optical 

fiber. [disco.co.jp] 

Jose, I would definitely opt for that. 

Bottom line, the benefits of attending 

the show still outweigh petty arguments 

involving its location. Place it 

where you will. I still vow to make the 

annual trek to SEMICON West. 

Mark Sullivan, marcom director at 

Kulicke & Soffa [kns.com], Horsham, 

Pa., wisely avoided the Las Vegas part of 

our question. But he had this to say 

about the show: 

SEMICON West has evolved into an 

industry-positioning event for all its 

exhibitors and attendees. 

At this three-day exhibition, companies 

create dialogs between semiconductors 

management leaders and the financial 

world to review and discuss the most current 

trends and future emerging 

roadmaps. 

The show is becoming less about just 

showing chip equipment and materials, 


30 


INDUSTRY NEWS 


and more about building closer relationships 

within the market. With so much of 

our semiconductor industry moving to 

Asia, companies located in the United 

States utilize SEMICON West as a key 

gathering place to meet and get the pulse 

on our chip industry. 

The show also provides an important 

forum to review new technology roadmaps 

and difficult industry challenges. Bottomline: 

SEMICON West is changing just like 

our industry is changing. It is not becoming 

obsolete to anyone. 

never stop. Also the number of vendors 

who purchase exhibitor lists and then 

spend weeks trying to sell spurious marketing 

programs…anyone had a call from 

Alabama recently? 

The food could be a lot better. And 

what’s with Smart Booths? There seems 

to be a constant push to upsell exhibitors 

for a show that has seen dramatic declines 

in attendance in recent years, traffic for 

2006 was basically the same as 2005. Yes, 

we would vote for Vegas—better hotels, 

more fun and cheaper to fly to. 

Vegas or Bust! 

Chris Goodrich at DCC in Ivyland, Pa. 

weighed in on the side of Vegas: 

We love SEMICON West simply for the 

very efficient way logistics are handled. 

We hate SEMICON West for the stupid 

layout—second floor of Moscone Center 

West gets slim traffic. Also for the barrage 

of emails that start ten months ahead and 

Conclusion 

In five years, will we be fondly reminiscing 

about the “Good Ol’ Days,” 

when SEMICON West was in San 

Francisco, as the rat-a-tat-a-tat of a 

large slot machine liberating its treasure 

sounds off in the Vegas background? 

We don’t know, but stranger things 

have happened! ■ 

Tessera Announces Wafer-Level Camera Technology 

San Jose—Tessera 

Technologies has 

announced OptiMC 

WLC,a new,waferlevel 

camera technology 

designed to 

advance the integration 

of miniaturized 

cameras in mobile 

phones, personal 

computers, security 

cameras and other 

electronics. 

The technology 

makes it possible to 

manufacture the 

camera module at the wafer level, 

reducing the size and total bill of 

materials. 

Tessera says its solution is designed 

to overcome the cost, size, and manufacturing 

roadblocks facing the industry 

as cameras become pervasive in electronics. 

Tessera’s OptiMC WLC camera module reduces the size of camera modules 

by up to half, the company says. (Tessera) 

The OptiML WLC reduces the size of 

the camera to a minimum, delivering 

up to 50 percent size reductions over 

camera modules used in current camera 

phones. Tessera will license the technology 

to the global electronics industry. 

[tessera.com] 

32 


INDUSTRY NEWS 

IWLPC Morning Panels Will Address Hot Topics in IC Packaging 

San Jose—Experts 

on two morning 

panels, one on 

INTERNATIONAL WAFER-LEVEL PACKAGING CONFERENCE 

Tuesday, Sep. 18 and 

one on Wednesday, 

Sep. 19, will tackle current trends in 

wafer-level packaging at the fourth 

Annual International Wafer-Level 

Packaging Conference. 

The Tuesday panel will address “The 

Business and Marketing of WLPs, ICs 

and Novel Devices.” Last year, this session 

attracted a standing-room only 

audience. 

Panelists are Larry 

Gilg of the Die 

Products Consortium; 

David Hays of Amkor 

Technology Inc.; Jan 

Vardaman of TechSearch 

International; and 

Jim Walker of 

Larry Gilg Gartner Dataquest. 

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Wednesday’s 8 a.m. opening session 

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Strategies—Merging, Crashing or 

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Panelists include Joe Fjelstad of 

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RoHS a Year After: Too Little, Too Late; 

Too Much, Too Soon—or Just Right? 

Although these whiskers belong to an angry Persian cat, tin whiskers, one of the scourges of the semiconductor industry, can be just as troublesome! 

It’s been a year since RoHS became the hottest electronics industry 

buzzword since Chlorofluorocarbons. Although the European Union earmarked 

six hazardous substances for elimination in electronics, clearly 

the removal of lead from electronics was closest to the hearts of the 

EU commission. Where has RoHS gone? We’ll tackle that subject now. 

By Ron Iscoff, Editor 

[chipscale@gmail.com] 

It seems incredible that despite the 

plaintive wails from a cadre of 

Nervous Nellies, the sky has not fallen 

in on the formerly lead-ridden semiconductor 

packaging industry. 

Barely a year has passed since the 

European Union instituted extraordinary 

mandates—most significantly 

“The Reduction of Hazardous 

Substances” (RoHS)—to rid the 

electronics world of cadmium, hexavalent 

chromium, lead, mercury, 

polybrominated biphenyls and polybrominated 

biphenyl ethers. 

36 


Although the RoHS directive, which 

became law on July 1, 2006, in theory 

only affected vendors of electronics and 

electrical equipment sold in Europe, in 

practice the impact was worldwide. 

“For companies doing electronics 

business in Europe, there is a complex 

system of regulations that must be complied 

with,” says Rogelio C. Rodriguez, 

director of engineering and science programs 

at UC Irvine Extension, on a web 

page advertising a RoHS-compliance 

seminar. 

Worldwide Implications 

In fact, companies doing business anywhere, 

with anyone—at almost any level 

of the supply chain—are likely to 

become ensnared in the RoHS mandate. 

A second directive that received far less 

industry recognition was WEE, “the 

Waste from Electrical Equipment.” 

Although, as we noted, five substances 

in addition to lead are covered 

in the RoHS directive, lead is the poster 

child for the legislation and has received 

most of the publicity. We will, accordingly, 

focus our report on that element. 

By the way, the European Union 

(EU), according to Wikipedia’s tonguetwisting 

language, “is a supranational 

and intergovernmental union of twenty-seven 

states and a political body. It 

was established in 1993…as the de facto 

This is the European parliament building complex in Brussels, Belgium. 

Locals call it “caprice des dieux” (folly of the gods) because the main 

building’s shape is like a box of camembert cheese of the same name! 

The plating line at AIT, Batam, Indonesia, faced with the conversation from lead plating, is looking at either 

100 percent tin plating or the use of pre-plated leadframes. 

successor to the six-member European 

Economic Community founded in 1957.” 

Isaac Newton Said It 

The RoHS directive, like so many regulations 

that affect international business, 

has proven to be like Sir Isaac Newton’s 

Third Law of Motion: For every action, 

there is an equal and opposite reaction. 

We could paraphrase Sir Isaac to contend 

that for every nattering and costly 

change “Company A” had to make to stay 

within RoHS, another change by “Company 

B” or “Company C” has provided additional 

business and/or income. 

There are now a bevy of new, leadfree 

solders that have 

come into being. Test 

and burn-in sockets 

are now being built to 

test the new lead-free 

packages. Even purveyors 

of packaging 

for lead-free solders 

have benefited by 

making new, greencolored 

containers for 

lead-free products! 

In addition, a new 

industry of consultants 

to ensure that companies 

comply with RoHS 

has been born, presenting multiple 

income-producing opportunities. 

Assessing RoHS’ True Impact 

From this May through mid-June, Chip 

Scale Review tried to assess RoHS’ true 

impact on the semiconductor packaging 

industry, its suppliers and users. 

We contacted representatives from 

about 125 companies from our industry 

database by e-mail, phone and in person. 

Surely, we thought, we would be deluged 

with comment, especially from the six 

or so makers of solder we contacted. 

Ultimately, a total of only about eight 

responses trickled in to our repeated 

requests for comment on how companies 

have benefited or coped with RoHS. 

That could mean one (or more) of 

several things: Either most companies 

were too busy to comment; they were 

afraid to comment; or they considered 

it a non-issue not worthy of pursuit. 

We were especially eager to bring you 

comment “from the trenches,” but 

apparently the trenches don’t exist in 

this non-battle for the European Union’s 

hearts and minds. 

When comment from most users and 

manufacturers fails, we turn to the experts. 

Harvey S. Miller, our contributing editorat-large, 

and a long-time veteran of 


Harvey Miller 

both the PWB and 

semiconductor 

packaging industries, 

is part of the 

community that is, 

not pro-lead, but 

believes the RoHS 

directives may be 

largely unneeded. 

Enforcement ‘Almost Non-Existent’ 

In a broadside he sent to several dozen 

people, Miller said, “It’s been whispered 

in dialogues here that enforcement of 

RoHS, lead ban included, has been almost 

non-existent since the July 1, 2006 

doomsday deadline.” 

Miller says no one is “blowing the 

whistle on non-compliant competitors.” 

Unisem began the transition to lead-free plating in 

2002. By the end of last year, Unisem’s percent of 

lead-free plating surpasssed 90 percent. 

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While penetration of lead-free solders has 

topped 55 percent, this is due to cellular 

phones, games and laptop computers alone. 

“There is no question that lead-free 

penetration is increasing for now, [but] 

what are the possibilities for the 

future?” our contributing editor asks. 

Even the EU Environmental 

Commission, Miller reports, says that 

enforcement is a problem. “Customs 

officials are not equipped to deal with 

all the confusing exemptions, nor to 

measure lead content.” 

Escalating Costs 

The Commission, Miller adds, “has 

heard of the many economic issues 

attendant on the drastic process 

changes, including the escalation of tin 

and silver costs due to the lead ban.” 

Ironically, Miller points out, tin and 

silver mining is increasing at a robust 

rate “at great cost to the environment.” 

The EU has hired the OKO Institute to 

study the effects and implementation of 

RoHS for a 2008 review. 

Joseph C. Fjelstad, co-founder of 

SiliconPipe [sipipe.com], San Jose, is an 

outspoken critic of 

the lead ban. 

A former Tessera 

Fellow who holds 

many packaging 

patents, Fjelstad says 

the first year of 

RoHS has been 

Joe Fjelstad “uneventful in terms 

38 


of prosecution of violators, but has 

resulted in an increase in activity to find 

viable solutions among both latecomers 

and those who had exemptions.” 

Most sources for traditional solutions, 

Fjelstad adds, “are reducing their 

product mix complexity, offering only 

lead-free products.” 

‘Still Illusive’ 

If technical chat boards can be believed, 

says Fjelstad, “it is clear that soldering 

solutions equal in every way to tin-lead 

solders are still illusive. 

“The range of different potential solutions, 

in terms of various compliant solderable 

finishes and solder alloys is large,” 

he adds. Many, he concludes “have proven 

to be dead ends relative to meeting product 

costs, quality and reliability targets.” 

Fjelstad also believes that although published 

evidence of the harmful effects of 

lead-free solder in the field are small and 

mostly anecdotal,“the rumors are troubling.” 

He feels that “based on comments from 

world soldering and reliability experts” 

who are not connected to solder suppliers, 

“it will be a long time until we know 

the full impact of RoHS.” 

The EU Parliament, adds Fjelstad, 

“asked for too much, too soon, and 

unfortunately without just cause.” 

The only solder supplier that responded 

to our call letters was Indium Corp. of 

America in Clinton, N.Y. 

‘No Visible Crises’ 

Dr. Ron Lasky, Indium's senior technologist 

[indium.com], told Chip Scale Review, 

“After all the battles to stop RoHS and 

all the predictions of disaster, it is instructive 

to ask how the RoHS implementation 

went. Like Y2K, the RoHS deadline 

came and went with no visible crises.” 

Dr. Lasky, who is also a professor at 

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their enforcement 

of RoHS and have 

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National Semiconductor was one of the first 

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A technician prepares to inspect a cassette carrier of wafers at Amkor’s China facility. Amkor and other 

packaging foundries in China will be subject to the strict Chinese RoHS regulations. 

worked with companies “behind the 

scenes” to address compliance issues. 

• EU countries were not seeking to 

make an example of companies not 

in compliance, but to help them 

become compliant. 

• Many leading companies’ RoHS 

preparations (HP, IBM, Motorola, 

others) minimized compliance crises. 

A critical RoHS concern was the finished 

goods reliability of lead-free solder compared 

to tin-lead solder. The latter has a 

reliability history of nearly 100 years. 

This factor, says Dr. Lasky, convinced 

the EU to grant exceptions to “missioncritical” 

products such as medical 

devices and military electronics. 

“Going into July 2006, there was hope 

in the lead-free, solder-reliability arena. 

Organizations like iNEMI and companies 

like Motorola performed extensive 

reliability testing. Some began as early 

as the late 1990s.” The test results 

appear to validate data now coming 

from the field, Dr. Lasky says. 

Reliability Concerns 

Although there are “lingering concerns” 

about SAC reliability under high-stress 

conditions, “the industry is evolving to 

handle them: Novel alloys are being 

developed, and revolutionary epoxies 

are being formulated to enhance the 

reliability of the lead-free solder joint,” 

according to Dr. Lasky. 

His conclusion is that RoHS implementation 

has gone better than expected. “Oh, 

and by the way, RoHS is here to stay!” 

Although user comment was limited, 

several IC packaging foundries did 

respond to our call letters. 

Amkor Technology Inc. [amkor.com], 

Chandler, Ariz., said lead-free implementation 

was free of technical issues except 

for process optimization and commercialization. 

The chief process change was for 

lead-free alloys, owing to their higher 

reflow temperature. “We had to adjust 

the reflow profile,” said Ahmer Syed, 

Amkor’s senior director of mechanical 

engineering. “This,” he added, “fell into 

the ‘as expected’ category.” 

Alloy Selection 

The selection of lead-free alloys for 

drop reliability was another area that 

needed development effort, according 

to Jim Fusaro, Amkor’s corporate vice 

president of product management. 

The alloys which Amkor initially 

selected, adds Fusaro, “based on industry 

and Amkor data from temp-cycle 

results, were not good enough to meet 

drop reliability requirements.” Twothirds 

of Amkor’s unit volume is comprised 

of leadframe products. The majority, 

says Fusaro, are RoHS compliant. 

Currently, he adds, of Amkor’s laminates, 

20 percent are green and 60 percent 

are lead-free. Some 95 percent of 

Amkor’s leadframes are green and an 

equal percent are lead-free. On an overall, 

wire-bonded-unit basis, 65 percent 

of all units shipped are green, while 85 

percent are lead-free. 

Advanced Interconnect Technologies 

[aitna.com], Batam, Indonesia, was 

being acquired by Unisem, when this 

article went to press. 

Ilan Toriaga, process engineer at AIT’s 

Batam facility, observes that the IC 

assembly industry is still struggling with 

the restrictions of RoHS and WEE. 

“The requirement for change in 

materials has affected the assembly 

process and significantly increased the 

cost of operation,” Toriaga adds. 

Molding Compounds 

A key change, he says, was selecting the 

appropriate molding compound. 

“This is very important, especially at 

higher board-reflow requirements such 

as 260°C.” Toriaga adds methods are 

being explored to improve the adhesion 

of the mold compound by using different 

resin bases and by increasing the 

filler content. 

Unfortunately, however, says Toriaga, 

these processes “pose a challenge, as they 

require a 300 percent increase in the 

cleaning frequency of the mold. This 

results in an increase in the cost of 

cleaning materials and affects the overall 

productivity of the assembly process.” 

Evaluation of various mold coating 

materials to resolve the adhesion and 

40 


Lead-free, water-soluble solder pastes in green jars 

are becoming a common sight on the factory floor. 

cleaning issues is underway, but “there 

are no clear solutions in sight.” 

AIT has also began a migration from 

a lead finish to either 100 percent tin 

plating or a pre-plated leadframe. Both 

options, however, present “unique challenges,” 

he says. 

For example, the industry’s demand 

for thicker plating to mitigate tin 

whisker growth is affecting the downstream 

process, he says. The result is 

higher yield loss and the need for additional 

inspection. The other “solution” 

—moving to lead-free, pre-plated leadframe 

finishing—also poses drawbacks 

during board-mounting assembly, he 

notes. 

‘Relatively Easy for Us’ 

The conversion to lead-free packaging 

has been “relatively easy” for Fujitsu 

Foundry Services, according to Mario 

Aguirre, senior technology manager of 

Advanced Packaging Services, San Jose. 

Fujitsu [fujitsu.com], he says, began 

working toward RoHS compliance 

about six years ago. 

One issue, however, is the necessity of 

keeping the legacy eutectic alloys in production 

for customers who are not ready to 

convert all their components to lead-free. 

Aguirre adds that the appearance of 

the new materials “was something the 

customers had to get used to; also, reliability 

of the lead-free solder joints has 

been a big issue—but this is expected 

when a new material is introduced.” 

On balance, he adds, “I think the 

industry has responded very slowly and 

has a long way to go.” 

Unisem of Ipoh, Malaysia, began 

lead-free plating in 2002. With only 0.5 

percent of the total volume requiring 

100 percent pure tin plating, most of 

the key customers and suppliers were 

adopting a “wait-and-see attitude,” says 

M.Y. Kong, metal finishing department 

manager. 

Indecision was a byproduct, he says, 

of not knowing which type of lead-free 

plating material would replace the thencurrent, 

industry-standard solder. 

Unisem, however, opted for 100 pure tin 

plating as the standard to replace SnPb. 

Tin Whiskers Again! 

That old bugaboo, tin whiskers, which 

cuts a sporadic swathe of fear and 

loathing throughout the user community 

like the bubonic plague of the 13th 

and 17th centuries, was a major concern 

to Unisem’s customer base. 

While the large, lead-free consortia, 

such as iNEMI, was trying to find other 

good, lead-free derivatives, the adoption of 

pure tin plating was gaining momentum. 

Unisem’s lead-free plating surpassed 90 

percent by the end of 2006, Kong reports. 

China’s RoHS 

The adherence to the European mandates 

has not created any problems for 

the company, contends Kong. Periodic 

laboratory tests on Unisem’s plated 

parts have shown they are fully RoHS 

compliant, he says. 

Since the company operates a factory 

in China, it will have to comply with 

China’s RoHS requirements which 

became effective in March. This means 

even raw materials such as anodes and 

molding compounds will have to comply 

with RoHS. 

Martin Hart, president 

of TopLine 

[topline.tv] in 

Garden Grove, 

Calif., says “an interesting 

thing happened 

along the 

pathway to the 

Martin Hart Kingdom of Lead- 

Free—the supply 

chain proved that it could be done!” 

The industry, adds Hart, has access to 

almost every lead-free IC package, as 

well as passive components. 

Hart says the issue that is “trickiest” is 

that most component data sheets do 

not fully disclose the exact percent of 

alloys found on the leadframe’s outer 

surface. 

“Typical data sheets simply mention 

the words, ‘lead-free’ or ‘Pb-free,’ but 

very few IC data sheets drill down the 

disclosure ladder to state Sn100 or 

Sn97/Bi3.0, etc. 

“Perhaps the chip makers do not feel 

this information is needed, but you will 

get an earful of woe from the board 

assembly processing engineers who 

might have valid reasons for not getting 

Bi into the solder paste. 

Conclusion 

Was the fear of RoHS a case of the boy 

who cried wolf? We know that implementing 

the European directives cost 

money. We don’t know at one year out, 

however, the full extent of the changes 

wrought by the EU. 

In some cases and for some companies, 

the bill will be reckoned in the tens 

of millions of dollars. Other companies, 

however, will profit handsomely from 

the mandates. 

Consider, too, that China and other 

countries are following the EU’s lead. 

And, in China’s case, at least, the regulations 

appear to be tougher than anything 

the EU devised. i 


Wafer-Bumping Processes, Tools and Trends 

If you’re expecting a warm, fuzzy feeling from your wafer-bumping vendor, you would be advised to either buy a teddy bear or select a vendor with 

experience, expertise and a reputation for service and quality! 

Wafer bumping continues to make inroads into the IC packaging mainstream. 

As it does, the technology opens Pandora’s box: Should I bump 

my own wafers or send them to an experienced contractor? What technology 

should I use for bumping? This article might help you decide. 

By Terrence E. Thompson, 

Senior Editor 

[tethompson@aol.com] 

Bumped wafers—which are 

usually preceded and followed 

by other wafer-level packaging 

process steps—produce relatively 

low-cost, batch-manufactured ICs. 

Although wafer-bumping is 

becoming more common, the 

bumping tools and services used are 

far from ordinary. In addition, outsourced 

bumping demand is up considerably, 

so waiting until the last 

minute for a bumping services 

provider is unwise. 

42 


The Issues and Challenges 

This article explores the maze of issues 

and challenges—processes, tools and 

materials, as well as the in-house versus 

outsourced experience base—that confronts 

both bumping users and waferbumping 

services. 

If you need a consistently reliable 

supplier, whether for materials, equipment 

or services—one who will give 

you that warm, fuzzy feeling—you need 

experienced vendors! It’s that simple. 

Ponder Away! 

One very significant question at the 

outset: Do you want to bump wafers 

yourself or use an experienced contractor? 

Bumping contractors have significant 

investments in equipment, materials 

and process “secrets” that certainly 

were not learned overnight, but they do 

share their expertise with customers. 

Yet, choosing a method and contract 

supplier is not as easy as it may seem at 

first glance. Do-it-yourself bumping has 

the inherent risk of overextending staff, 

facilities and budgets. 

If a bumping provider is your choice, 

a better understanding of the options, 

and market demands, is essential. There 

are several viable bumping options as 

well as complementary technologies. 

You may want to get your designers 

and manufacturing staffs to plan an 

internal company roadmap specifying 

goals that will address current and 

future bumping needs. 

Roadmaps de Jour 

The oft-quoted and updated 

International Technology Roadmap for 

Semiconductors (ITRS) seems to raise 

more questions than solutions as 

answers for short-term issues are raised. 

From past performance, it is clear 

that packaging and interconnect issues 

are becoming a much greater cost component, 

and bumping is one way to 

reduce interconnect costs quickly while 

improving reliability. 

ITRS estimates that area-array, 

flip-chip pitches are heading 

below 80µm, with peripheral 

pitches moving to ≤15µm within 

the next decade. Pincounts are 

expected to increase rapidly, too. 

These factors suggest a more considered 

approach to picking 

bumping vendors, both for the 

short- and long terms. 

Dr. Raj Pendse, vice president 

of flip-chip products at STATS 

ChipPAC [statschippac.com] in 

Singapore, says “The last decade 

has seen the emergence of flipchip 

packaging from the traditional 

niche of high-end mainframe 

computers and servers to 

mainstream products such as 

PCs, laptops and game consoles. 

“The driver,” says Dr. Pendse, 

“has been the need for high performance, 

high I/O densities; and 

efficient, on-chip power distribution 

schemes that are unattainable by conventional 

wire-bonding interconnection.” 

SATS Growth 

Jim Walker is the research vice president 

at Gartner Inc. [gartner.com], Stamford, 

Conn. 

Walker says semiconductor assesmbly 

and test services (SATS) industry growth 

has been achieved by the accelerating 

transition to new packaging methods. 

These include CSP, WLP, flip chip and 

system-in-package formats. Integration 

via packaging is becoming a larger factor 

in the overall function and cost of a 

semiconductor device. 

Bumping, Walker says, becomes a greater 

part of the SATS business each year. 

The worldwide semiconductor assembly 

and test services (SATS) market exhibited 

double-digit growth for the fifth consecutive 

year in 2006, according to preliminary 

results by Gartner. 

Worldwide SATS revenue totaled $19 

billion in 2006, up 25.7 percent from 

2005 revenue. 

A wafer is shown within the C4NP solder transfer chamber 

(Suss MicroTec) 

Advanced Semiconductor Engineering 

(ASE) Group [aseglobal.com] in 

Kaohsiung, Taiwan, remained the number 

one provider of assembly and test 

services in 2006 by revenue, topping $3 

billion. 

Number two Amkor Technology Inc. 

[amkor.com], however, grew the fastest 

among the top three companies. 

Amkor’s growth was attributed to its 

expansion in flip-chip bumping services 

and leadless leadframe packaging. 

The Changing Face of WLCSP 

David Hays, vice president of waferlevel 

packaging at Amkor Technology, 

in Morrisville, N.C., says, “The landscape 

is changing for WLCSP. 

“There is a rapidly expanding market 

for WLCSP, especially outside its traditional 

realm of ≤25 bump parts into 

≥144+ bump designs. The data exists to 

support the mechanical robustness of 

these large die implementations. That 

means better bumps are essential.” 

The new bumping challenges in this 

space are low cost and green packaging 


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with end-to-end development and production – all in-house – in New Jersey. 

Call IMI today at 856-616-0051 to discuss your specific wafer bumping and WLP needs. 

Or visit us at www.imi-corp.com. 

INTERNATIONAL MICRO INDUSTRIES 

North America’s Center for Wafer Bumping Excellence TM 

1951 Old Cuthbert Road • Building 404 • Cherry Hill, NJ 08034 • 856.616.0051 • FAX 856.616.0226

notes STATS ChipPAC’s Dr. Pendse. 

Hence, the industry is bracing for 

alternative wafer-bumping solutions 

that dramatically reduce cost, streamline 

logistics and enable a “green” package, 

which has spawned interest in 

approaches such as copper-post bumping, 

Au stud bumping, IBM’s C4NP and 

micro-ball attach to name a few. 

Not Just Batch Bumping 

Surfect Technologies Inc. [surfect.com] 

in Tempe, Ariz., offers an alternative to 

the widely used batch wafer wet processing—a 

single chamber, multi-metal, 

bump-plating tool. 

“The goal is offer customers a lower 

cost of entry for wafer bumping and 

wafer-level packaging requirements,” 

says Steve Anderson, Surfect’s CEO. 

The growth of flip-chip packaging 

has been hindered by a lack of infrastructure 

and tools for producing lowcost 

bumps, suggests Anderson. 

The C4NP mold filling tool is shown in operation. IBM’s updated C4NP process is based on its original 

Controlled Collapse Chip Connection. (SUSS MicroTec) 

“Currently 83% of bumped wafers 

are plated. The plating equipment base 

for bumping today is multi-tank technology—equipment 

which typically 

requires significant floor space and is 

not capable of handling the small lots 

and quick changeovers required by the 

backend assembly facilities.” 

Anderson adds, “The wire bonding 

equipment model has been well accepted 

within backend assembly. This model is 

built around individual machines with 

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small footprints that are justified based 

on incremental capacity increases and 

fast ROI.” 

Surfect’s single-chamber plating tool 

is capable of producing multi-metal layered 

bumped wafers. This plating tool 

has a footprint similar to that of a wire 

bonder. The tool handles one wafer at a 

time and plates at high speed through 

improved reaction kinetics and control. 

include IC miniaturization of size and 

weight, the integration of heterogeneous 

technologies in a single package, the 

replacement of long 2D interconnects 

with short vertical interconnects, and 

the reduction of parasitics and power 

consumption. 

We suspect that bumping and TSV 

technology will be complementary, with 

both processes enjoying solid growth. 

What Flavor Bumps? 

Wafer-bumping methods, especially 

with bumping’s numerous variants 

make for interesting reading. Just when 

we thought that bumping was well 

understood, the Pb-free frenzy changed 

the material and process rules. Pb-free is 

not for everyone, and you will find vendors 

that bump with eutectic or highlead 

alloys because there are process 

advantages. 

Tin-lead works well and is backwards 

compatible with most existing electronics. 

Since numerous end products do 

not require Pb-free, especially servers 

and military/aerospace applications, 

bumping with lead or not is a great 

option depending on the OEM product. 

TSV and Bumping 

The typical trend in semiconductor 

technology development is to move 

from 2D configurations to 3D stacking 

(with wires, bumps, and microvias), and 

then move to 3D ICs with through-silicon 

via (TSV) interconnects to reduce 

IC footprints, increase Si efficiency and 

shorten interconnects. 

Depending on the silicon to be 

bumped, chipmakers are likely to find 

TSV plus bumping a very flexible option. 

General advantages of 3D packaging 

C4NP technology is capable of fine-pitch bumping 

while offering the same alloy selection flexibility as 

solder paste printing. 

Pb-free, however, requires higher 

reflow temperatures which often stresses 

internal junctions, a condition which 

is extremely undesirable. Bumping contractors 

and bumping equipment and 

materials vendors have done a remarkable 

job implementing workable Pb-free 

processes. 

In terms of cost, simple stencil print- 

Up to 300mm Bumping 

• BGA/CSP Packaging 

• High Density Packaging/Substrates 

• Laminated Power Components 

• Wafer Bump Reflow, Laser Diode Reflow 

• Microwave Hybrids, Fluxless Au/Sn Reflow 

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46 


ing followed by a trip through a reflow 

oven works well for larger bumps on 

generous pitches. 

Another method is to deposit solder 

balls of known alloy content and volume, 

often onto tacky fluxed wafers. 

This is popular because it works on 

finer pitches with smaller balls than 

stenciling. Yet, there are still other ways 

to bump wafers. 

C4NP Entering Production 

Recently, IBM and SUSS MicroTec 

[suss.com] teamed up to go commercial 

with the updated version of IBM’s venerable 

C4 process (Controlled Collapse 

Chip Connection—New Process)—the 

driving concept behind virtually all 

present day bumping methods. 

To date, it is producing extremely 

consistent bumps upon reflow at a reasonable 

price. IBM is moving C4NP 

into production now with others likely 

to follow. 

FlipChip International’s wafer-bumping facility in Phoenix, Ariz., is one of the largest domestic flip-chip 

providers. FCI’s Ted Tessier says several applications are being considered for wafer-to-wafer and die-towafer 

stacked die WLCSPs. In 2008, he adds, “the migration of WLCSP products from solely 2D packaging 

solutions to 3D packaging” is likely to begin. 

It decouples under-bump metallization 

(UBM) from bumping, which opens 

a whole new set of options for UBM. It 

supports any lead-free alloy, and—most 

importantly—it eliminates the cost and 

waste associated with electroplating solder. 

Equipment is ready and mold suppliers 

are lined up and qualified. 

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• Adhesion to underlying dielectric 

and metal 

• A barrier to protect the silicon 

circuitry; and 

• A solder-wettable surface. 

This photograph of the wafer bumping process application was taken at the MicroFab factory in Singapore. (Ellipsiz) 

It is a solder transfer technology 

where molten solder is injected into 

pre-fabricated and reusable glass molds. 

The glass mold contains etched cavities 

which mirror the bump pattern on the 

wafer. The filled mold is inspected prior 

to solder transfer to the wafer to ensure 

high final yields. 

Filled mold and wafer are brought 

into close proximity/soft contact at 

reflow temperature, and solder bumps 

are transferred onto the entire 300mm 

(or smaller) wafer in a single process 

step without the complexities associated 

with liquid flux. 

C4NP technology is capable of finepitch 

bumping while offering the same 

alloy selection flexibility as solder paste 

printing. The simplicity of the process 

makes it a low cost, high yield and fast 

cycle time solution for both fine-pitch 

and chip-scale package bumping applications. 

Wet Chemistry Batch Bumping 

One widely used process with many 

variants is wet process electroplating 

bump deposition. It can deposit the 

desired metals or alloys with a minimum 

of fuss and with precision. 

According to SEMITOOL 

[semitool.com] in Kalispell, Mont., a 

partner in the international EMC-3D 

consortium, the development of IC 

technology is driven by the need to 

increase performance and functionality 

while reducing size, power and cost. 

The continuous pressure to meet 

those requirements has created innovative, 

small, cost-effective 3D packaging 

technologies. 

UBM Caveats 

The UBM structure is a critical component 

of any solder bump interconnect 

system. The UBM typically provides 

three functions: 

For lead-free solder bumps, the barrier 

layer is key to reliability due lead-free 

solder’s higher Sn content. 

A common barrier layer used in the 

industry is electroplated nickel. This 

layer provides good protection from 

degradation of the silicon metallurgy by 

tin rich lead free solders. C4NP provides 

an opportunity to eliminate electroplating, 

and its associated costs for 

plating chemistry, analysis, supply and 

waste treatment. 

According to Klaus Ruhmer, director 

of global marketing and sales–C4NP at 

SUSS MicroTec Inc. [suss.com] in 

Waterbury Center, Vt., “Electroless 

Ni/immersion Au (ENIG), with and 

without Pd, works as an alternative 

UBM structure. 

“Wafers were fabricated with these 

UBM structures, solder applied with 

C4NP, and chip level stressing performed 

to determine the robustness of these 

alternative stack-ups. Analysis of these 

structures following multiple reflows 

and thermal cycling is presented.” 

Conclusion 

Too many options? Not really, but do 

your homework and talk to the experts. 

Selecting a bumping house is a safe 

bet for most chipmakers with moderate 

to significant volume demands. 

All of the processes work, so it comes 

down to finding the best one for a given 

application. For prototypes and low-tomoderate-volume 

needs, DIY in-house 

bumping is indeed a tempting option. 

bumping equipment companies are 

more than eager to help with design 

and prototype considerations. i 


INTERNATIONAL DIRECTORY OF WAFER-BUMPING SERVICE PROVIDERS 

Notes: This list was compiled from data supplied by the respective providers and is not all-inclusive as to company or service offered. Advertisers in this issue are 

indicated by boldface listings. CM=Consult Manufacturer. 

Company Name 

Address 

b Phone 

> Fax 

Year Founded 

✪ Chairman ★ President 

✦ CEO ✩ COO ✧ Other Title 

✖ Maximum Wafer Size (mm) 

B Bump Pitches (microns) 

★ Equipment 

A=Aligners, B=Stencil Printers, 

C=Steppers, D=Sputtering, 

O=Others 

T Bumping Technologies 

M Bump Metals Alloys 

✍ Other Bumping Services 

[web site] 

❉ Contact 

Additional Offices 

Advanced Semiconductor 

Engineering Inc. 

26 Chin Third Road, 811 

Nantze Export Processing Zone 

Kaoshiung, Taiwan 

b 408.986.6500 

1984 

✪ Jason Chang 

★✦ Richard Chang 

✖ 300mm 

B 150µm+ 

★ A, B, C, D, O=Electroplaters 

T Sputtering, electroplating 

M Sn63/37Pb, 

low alpha Sn63/37Pb, 

Pb95/5Sn, Sn95.5/4Ag/0.5Cu 

✍ Advanced wafer bumping services as part of 

a complete turnkey solution, encompassing 

circuit design through final test 

[aseglobal.com] 

❉ Patricia MacLeod 

marketing@aseus.com 

ASE U.S. Inc. 

3590 Peterson Way, Santa Clara, CA 95054 

b 408.986.6500 

Amkor Technology Inc. 

1900 S. Price Rd. 

Chandler, AZ 85248 

b 480.821.2408 

1968 

✪★✦ James Kim 

✖ 300mm 

B 6µm+ 

★ CM 

T Electroplating, ball load, paste 

M PbSn95/5 and 63/37, SnAg, 

SnAgCu, Cu pillar 

✍ Bumping, with and without repassivation, 

RDL, turnkey WLCSP, integrated passives 

[amkor.com] 

❉ David Hays, VP–Wafer Level Packaging 

dhays@amkor.com 

140 Southcenter Ct., Suite 600 

Morrisville, NC 27560 

b 919.940.0606 

Chipbond Technology Corp. 

No. 3 Li Hsin 5th Road, Science Park 

Hsinchu 300, Taiwan 

b +886.567.8788 

1997 

✪✦ Fei-Jain Wu 

★ Hoo-Wen Gau 

✖ 300mm 

B 25µm+ 

★ A, B, C, D 

T Sputtering 

M Au, high lead, eutectic, 

lead free, Cu 

[chipbond.com.tw] 

❉ Robert Hsu, VP–Sales and Marketing 

robert-hsu@chipbond.com.tw 

b +866.3.567.8788 ext. 6000 

FlipChip International LLC 

3701 E. University Dr. 

Phoenix, AZ 85034 

b 602.431.6020 

1996 

★✦ Bob Forcier 

✖ 200mm in Arizona, 

300mm in China 

B 70µm+ 

★ A, B, C, D, 

O=Electroless Ni UBM 

T Standard flip chip, UltraCSP, 

sputtering, repassivation, etc. 

M SAC 351, SAC 105, SAC 266, 

63/37 SnPb, 95/5 PbSn 

✍ Bumping services for flip chip and WLCSP 

plus post bump thin, dice and sort to T&R/ 

tray 

[flipchip.com] 

❉ Bret Trimmer, Senior Marketing Manager 

bret.trimmer@flipchip.com 

b 602.431.4760 

Fujitsu Microelectronics America Inc. 

Div. of Fujitsu 

1250 E. Arques Ave., M/S 333 

Sunnyvale, CA 94088 

b 800.866.8608 

> 408.737.5999 

1979 

★✦ Kazuyuki Kawauchi 

✖ 300mm 

B 35µm+ 

★ A, B, C 

T Electroplating, plating 

M High lead-low alpha, 

lead free 

✍ Fujitsu has a lot of experience in 

bumping technology. 

[fujitsu.com/us/services/edevices/microelectronics] 

❉ Mario Aguirre, Senior Technology Manager 

maguirre@fma.fujitsu.com 

b 408.737.5604 

International Micro Industries (IMI) 

1951 Old Cuthbert Rd., Building 404 

Cherry Hill, NJ 08034 

b 856.616.0051 

1971 

★✦ Chris N. Angelucci 

✖ 200mm production, 

300mm prototypes 

B ≥10µm and up, design 

dependent 

★ A 

T Electroplating 

M In, Au, Au/Sn alloy, Cu, Sn/Pb 

alloys, Ni, Ag 

✍ Fine pitch bumping and WLP services, 

co-design/supply development through 

production, medical, MIL, automotive, 

sensor, MEMS 

[imi-corp.com] 

❉ Chris Angelucci, President and CEO 

cangelucci@imi-corp.com 

50 



Company Name 

Address 

b Phone > Fax 

Year Founded 





★ Equipment 



O=Others 




[web site] 

❉ Contact 


Millennium Microtech (Shanghai) 

Co. Ltd. 

Zhang Jiang Hi-Tech Park 

Pudong, Shanghai, China 201203 

b +86.21.5080.1128 

1999 

★✦ Vic Tee 

✖ 300mm 

B CM 

★ CM 

T CM 

M CM 

[m-microtech.com] 

❉ James Teh, VP–Business Development 

jamesteh@m-microtech.com 

351 Guo Shou Jing Road, Pudong New Area, 

Shanghai 201203, China 

b +86.21.5080.1128 ext. 328 

Nepes Pte. Ltd. 

12 Ang Mo Kio, Street 65 


b +65.6412.8181 

2005 

✦ Esdy Baek 

✖ 300mm 

B 100µm+ 

★ A, B, C, D 

T Sputter, plating, reflow, 

ball mount 

M Lead free (SnAg2.5), SAC, 

high lead, eutectic, Cu pillar 

[nepes.com.sg] 

❉ B.J. Lim, Senior Business Development Manager 

bjlim@nepes.com.sg 

b +65.6412.8177 

Pac Tech USA 

328 Martin Ave. 

Santa Clara, CA 95050 

b 408.588.1925 

2001 (USA), 1995 (Germany) 

✪★ Dr. Thorsten Teutsch 

✦ Dr. Elke Zakel 

✖ 300mm 

B 120µm (solder), 

40µm (Ni/Au) 

★ A, B 

T Electroless, stencil printing, 

ball drop, solder jetting, etc. 

M Eutectic SnPb, lead free (SnAg, 

SnAgCu), high lead, AuSn 

✍ Low-cost wafer bumping using maskless 

electroless Ni/Au UBM. Facilities in Europe, 

USA and Asia. 

[pactech-usa.com] 

❉ Dr. Thorsten Teutsch, President and CTO 

teutsch@pactech-usa.com 

Pac Tech GmbH, Am Schlangenhorst 15-17 

D-14641 Nauen, Germany 

b +49.1723963706 

❉ Thomas Oppert, VP–Marketing, oppert@pactech.de 

Siliconware Precision Industries Co. Ltd. 

No. 123, Sec. 3, Da Foung Rd. 

Tantzu, Taichung, Taiwan 

b +886.4.25341525 

1984 

✪ Bough Lin ★✦ C.W. Tsai 

✖ 300mm 

B 120µm+ 

★ A, B, C, D 

T Printing bump, plating bump 

M Sn63/Pb37, Sn5/Pb95, 

SnAgCu, SnAg, SnCu, 

Au bump 

[spil.com.tw] 

❉ Ah-San Kyu, Marketing Director 

ahsank@spilca.com 

Siliconware USA Inc. 

1735 Technology Dr., Suite 300, San Jose, CA 95110 

b 888.215.8632 

Staying Ahead in Innovative 

Bonding Technology 

WIRE BONDERS TEST EQUIPMENT LINE INTEGRATION 

Heavy Ribbon Shows Our Leadership 

5th Generation – the only all-in-one bonder 

on the market 

Fine and heavy wire wedge, gold ribbon, 

gold ball – and now heavy ribbon 

Leading-edge heavy ribbon bonding technology 

with minimal investment 

www.fkdelvotec.com 

F&K Delvotec Inc. 

27182 Burbank Avenue, Foothill Ranch, CA 92610 

phone (949) 595-2200, fax (949) 595-2207 



Company Name 

Address 

b Phone > Fax 

Year Founded 





★ Equipment 



O=Others 




[web site] 

❉ Contact 


STATS ChipPAC Ltd. 

10 Ang Mo Kio Street 65 

#05-17/20 Techpoint, Singapore 569059 

b +65.6824.7777 

1995 

✪ Charles Wofford ★✦ Tan Lay Koon 

✖ 300mm 

B 150µm+ 

★ A, B, C, D 

T Electroplating for 300mm 

wafers, printing for 200mm 

M Eutectic, ultra low alpha high 

lead, Pb-free 

[statschippac.com] 

❉ salescontact@statschippac.com 

STATS ChipPAC Inc., 47400 Kato Rd. 

Fremont, CA 94538 

b 510.979.8000 

Unisem-Advanpack Technologies Sdn. Bhd. 

No. 1A, Persiaran Pulai Jaya 9 

Kawasan Perindustrian Pulai Jaya 

31300 Ipoh, Perak, Malaysia 

b +60.5.3572800 

2004 

✪✦ John Chia ★ C.H. Ang 

✖ 200mm 

B 100µm+ 

★ A, D 

T CM 

M Ti-Cu, TiW-Au, Ni, SAC 

[unisem.com.my] 

❉ H.G. Su, Marketing Manager, hgsu@unisem.com.my 

b +60.5.3572800 ext. 722 

❉ Mike Stokman, VP–North American Sales 

mike.stokman@unisem-us.com 

b 925.245.1535 

VLSIP Technologies Inc. 

750 Presidential Dr. 

Richardson, TX 75081 

b 972.437.5506 

1984 

✧ Robert C. Gilbert (Vice President) 

✖ Chips to 50mm square 

B 60µm 

★ Thermosonic bonder 

T Gold stud bumping 

M Au 

✍ Gold stud bumping supporting rapid 

utilization of conventional wire bond die 

designs 

[vlsip.com] 

❉ Robert C. Gilbert, Vice President 

r.gilbert@vlsip.com 

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Our Solutions Set Standards

Single Device Tracking: A Cost-Benefit Analysis 

The acceptance and implementation of 

single device tracking has been made 

much easier with the release of SEMI 

standard E142. This article discusses 

how, when and why to implement this 

new standard on the assembly floor. 

By Dave Huntley, 

President, KINESYS Software, 

Petaluma, California 

[kinesyssoftware.com] 

There has been much talk recently 

about Single Device Tracking 

(SDT), and now the release of the SEMI 

E142 standard provides the necessary 

framework to make SDT possible. One 

big question remains, however: Is the 

significant investment justified? 

Several independent device manufacturers 

(IDMs) and test and assembly providers 

have already made the qualitative assessment 

that SDT will be required to accelerate new 

product introductions and respond more 

quickly and precisely to field failures. 

Richard Groover, engineering director 

at Skyworks Solutions, notes, “We 

can trace returns on a total lot basis, but 

lots can be in several thousands of 

units. SDT could facilitate our reaction 

time and our ability to more quickly 

contain and resolve issues.” 

However, it is difficult to justify the 

investment in SDT without more quantifiable 

benefits that yield an acceptable return 

on that investment. Groover says, “Implementation 

of SDT, especially for complex 

modules, can also yield other productivity 

improvements, such as enhanced 

equipment efficiency and throughput.” 

What is SDT? 

Intel, Micron and others identify individual 

units by burning a unique serial 

number into onboard memory. 

Figure 1. SDT involves the management of wafer, strip and tray maps containing bin code, device ID and 

XY transfer data, including integration with equipment from wafer sort to final test, so the entire and precise 

manufacturing history of a single device can be recorded and analyzed. (Kinesys Software) 

SDT takes this a step further by also 

tracking the device after it is picked from 

the wafer and assembled on a strip, singulated, 

then tested on a tray. With SDT, 

therefore, the entire assembly and final 

test experienced by a single device 

become identifiable (see Figure 1). 

The Benefits 

SDT offers compelling benefits for new 

product introductions and for enabling 

rapid and precise response to field failures. 

These benefits will play a more important 

role when SDT is available from competitors. 

Until then, however, the investment 

will most likely be justified on the 

basis of reduced manufacturing costs 

with a quantifiable return on investment. 

When an assembly and test provider 

bids on a new contract, the first hurdle 

is to deliver evaluation lots with an 

acceptable yield—not an easy task with 

today’s advanced package designs. 

Anything that reduces the time to deliver 

evaluation lots may make the difference 

between winning and losing the contract. 

With SDT implemented, defect trend 

analysis moves from the statistical realm 

to pin-point precision. It is possible to 

identify the XY location on the wafer 

and strip in case the defect is related to 

the geometry of either. 

Moreover, it is also possible to pinpoint 

the exact equipment, consumables, shift, etc., 

employed to process the device and to find 

all the other devices that experienced the 

same mix of manufacturing conditions. 

The root cause of a process defect can thus 

be found and removed much more quickly. 

Improved Response to Field Failures 

Field failures may not be common, but 

they can be devastating to the device 

supplier because they may lead to entire 

production lots being placed on hold, 

resulting in delayed revenue. If the situation 

is not quickly resolved, loss of primary 

supplier status may follow! 

The first step is to analyze the root 

cause of the field failure. This will lead 


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Figure 2. Strips will be identified with a 2D matrix 

ID. Microcircuit Technology is cooperating with 

KINESYS Software to offer marked strips with 

SEMI E142 strip maps. 

the analysis team to the process step 

and materials responsible. At this point, 

SDT can already provide a report that 

the root cause was a particular tool or 

material batch and all devices not 

processed with that equipment or batch 

can be taken off “hold.” 

More important than the reduced 

scrap, however, will be the customer’s 

appreciation when the delivery of quality 

parts returns to normal levels with a 

minimum delay. 

Saving Manufacturing Costs 

Implementing SDT at each process step 

requires significant investment; but on 

the flip side, there are significant cost 

savings available. As always, the investment 

decision rests with the return on 

investment (ROI) analysis. 

To explore the ROI analysis we will 

take an example of a memory device for 

the consumer market. 

The bare strip from the supplier is 

inspected and bad locations are inked. 

Additional passives are added to the 

substrate in a surface-mount (SMT) 

process, which is followed by die attach 

of the memory die and then the controller 

die after curing. 

Each device is then wire bonded, 

molded, marked, singulated and tested. 

Without SDT, the marks must be 

detected and skipped at each step up to 

wire bond. Prior to mold, bad locations 

are marked along the strip rails; afterward 

the molded devices are re-marked. 

These new marks are used at singulation 

to sort the devices into the test tray. 

With SDT, the bare strip is marked 

with a unique identifier (Strip ID) and 

shipped by the supplier with a strip map. 

At each step, the equipment downloads 

the strip map, skips the bad locations 

completely and uploads the strip map— 

updated with any in-process or postprocess 

inspection results. At singulation, 

the strip map is used to bin out the 

good devices into the test tray. 

SDT eliminates the cost of: 

• Die and consumables being applied 

to bad locations. This is particularly 

important at the die-attach step because 

good die may be wasted if placed on a 

location that failed at SMT; 

• Equipment time spent on bad locations, 

as well as indexing to processing or 


• Testing devices that with SDT would 

not have ended up in the test tray. 

Figure 3. Manual or automatic optical inspection 

marks bad units in a strip map identified by the 

strip ID. (Microcircuits Technology) 

detecting ink marks and skipping bad 

locations. 

• Inking of bad locations. One problem 

with inking strips is that the marks 

are obscured after mold. To overcome 

this problem, the ink marks are transcribed 

onto the rails of the strip 

before mold and then back to the 

outside of the package after mold. 

With SDT, these error-prone and contaminating 

steps can be eliminated. 

Deployment 

Nothing good is free. Deploying SDT 

requires that the strips be marked, 

equipment upgraded to use strip maps 

and all equipment be networked to a 

central map server. 

What will the strip supplier charge to 

provide marked strips with strip maps 

containing the inspection results? 

Suresh Rao of Microcircuit 

Technology, a strip supplier, notes, 

“Strip mapping will add value both 

upstream, in the manufacture of complex 

multi-layer strips (Figure 2), and 

downstream in packaging and test. 

“Another benefit we see is the ability 

to quickly and precisely report the number 

of good locations being delivered 

since this what our customers pay for.” 

The model assumes that the strip 

supplier will apply a one time charge of 

Figure 4. Skyworks is presently developing the 

capability internally and in cooperation with others 

to map the individual strips. (Skyworks) 

$40,000, once the market has matured, 

to cover the cost of the strip mark equipment 

and to upgrade the automated 

optical inspection (AOI) equipment to 

generate strip maps (Figure 3). 

Upgrading Equipment for SDT 

Equipment must have a reliable strip ID 

reader. To enjoy the maximum benefit 

from SDT, the equipment should 

include post-process inspection. The 

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58 


Figure 5. The Renesas DB800 will offer OEM software 

as its primary wafer and strip mapping software. 

(Renesas) 

camera used for this inspection can 

often serve the additional purpose of 

reading the strip ID by widening the 

field of view. 

Such cameras are not cheap (~$16,000), 

and analysis software must also be purchased 

or developed. 

The equipment control system software 

needs to be upgraded to use the 

strip map. Part of the upgrade must be 

a SEMI E142 host interface to download 

and upload the strip maps to the factory, 

as well as a user interface for visualization, 

setup, editing, and so forth. 

Just as with SECS/GEM, SEMI E142 

will give rise to enabler products (see 

Figure 4). 

Step Phase 1 Phase 2 

Strip Mark Y Y 

Strip Inspect Y Y 

SMT Y Y 

DA for Memory Y Y 

DA for Controller Y Y 

WB N Y 

Mold N Y 

Device Mark N Y 

Singulate Y Y 

Test N Y 

Analysis 

Savings per week $43,928 $3,261 

Investment $400,000 $500,000 

ROI (Weeks) 9 153 

Phase 1, with a relatively modest investment of $400K promises 

an ROI of 9 weeks on a line producing ~1.3M devices per week. 

Phase 2 ROI is not compelling by itself so adding these 

steps must be justified on the less quantifiable “new product 

introduction” and “response to field failure” benefits. 

In our informal survey of equipment 

vendors, the expected price for the 

upgrade varies considerably between 

$6,000 and $30,000. Most figures cluster 

around the $15,000 mark, so the model 

uses that figure for all equipment 

(except wire bonders where $7,500 is 

used because of the economies of scale 

and because many wire bonders already 

have an AOI camera onboard). 

This survey did highlight one important 

trend: Equipment vendors are receiving 

serious requests for this capability, as 

Toshikazu Miyata, senior director of 

global sales and marketing for Renesas 

confirms, “We receive more and more 

requests from our customers for SEMI 

E142 compliance and SDT. 

“The majority of our die attach and 

flip-chip systems now offer this functionality, 

and our installed base of machines 

can be upgraded to some level of compliance 

with an additional investment.” 

(See Figure 5.) 

Central SDT Server 

It is possible to string together equipment 

using file-based mapping, in which one 

tool uploads a map to a pre-defined 

folder on the network, and the next 

downloads it from that location. 

This is not an enterprise-worthy solution, 

however, because the files can be 

accidentally deleted, overwritten or otherwise 

lost; and, because the process flow 

is fixed, it is not possible to effectively 

extract the traceability data, which is the 

core requirement for an SDT system. 

Accordingly, the equipment must be 

networked to a central enterprise SDT 

server. Powerful new features then 

become possible, such as lot and substrate 

tracking; the prevention of lot 

mixing; real-time yield analysis; factory 

wide monitoring; customized reporting; 

and MES integration, to name a few. 

The cost of the SDT server, data management 

and reporting tools, and other 

necessary components is estimated to be 

$5,000 ($2,500 for wire bonders) per tool. 

Phased Deployment 

It makes sense to deploy SDT in phases so 

that the first phase can realize the maximum 

benefit and the lowest cost and risk. 

Phase 1 in the model analyzes the 

deployment of SDT only on the strip 

mark and inspect steps, surface mount, 

die attach and singulate steps. Phase 2 

analyzes the deployment of SDT on the 

remaining steps, after which all benefits 

of SDT can be realized, including 

improved new product introductions 

and responses to field failure. 

The chart shows the investment, savings 

and ROI calculation for each phase. 

Conclusion 

On the benefit side, we have looked at 

three distinct areas: 

1. New product development; 

2. Response to field failures, and 

3. Saving manufacturing costs. 

Although the first two items will ultimately 

be the most important benefits 

driving SDT, the final item may get the 

first projects started. 

On the cost side, equipment vendors 

play a significant role. The good news is 

that they are aware of the upcoming 

SDT requirements and have studied the 

SEMI E142 standard. 

The model shows that deploying SDT 

Phase 1 promises an acceptable ROI for a 

modest investment; deploying SDT Phase 

2 must be justified by benefits 1 and 2. 

Ultimately, the realization of SDT will 

be the result of a partnership between 

the end user, the equipment vendor and 

the software and integration services 

providers. i 

Mr. Huntley is 

founder and president 

of KINESYS Software. 

His is currently cochair 

of the Sort Map 

Taskforce at SEMI 

responsible for the 

SEMI E142 standard. 

[dave.huntley@kinesyssoftware.com] 


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Advances in Wafer Plating: Meeting the Next 

Challenge of Through-Silicon-Via Processing 

Copper electroplating has become a 

standard in electronics for making 

electrical interconnects between 

devices. A new packaging technology, 

using through-silicon-vias employs 

copper plating for high-density packaging 

at wafer level through chip stacking. 

This article discusses the benefits 

and limitations of wafer plating. 

By Robert S. Forman, 

Rohm and Haas Electronic Materials, 

Freeport, N.Y. [rohmhaas.com] 

In the manufacture of electronics, 

copper electroplating is used to 

make electrical interconnects between 

devices. Part of the reason for using 

copper is to create vias, which are 

employed as conductors of electrical 

signals between adjacent layers. These 

vias are often built with electroplated 

copper. 

This article will investigate the use of 

copper at the level 0 and level 1 interconnects—the 

electrical connections 

within the die and within the IC package, 

respectively. 

A survey of the state of the art of Cu 

plating on wafers will be discussed with 

special attention to a newly developed 

technology, through-silicon-via (TSV) 

copper plating. 

TSV manufacturing is key in the 

development of a new, high-density packaging 

method, TSV 3D chip stacking. 

Copper Plating 

Figure 1 illustrates the interconnect 

hierarchy. At the bottom of the pyramid 

is the PWB, where copper plating is 

used extensively. At this level, the PWB 

structural dimensions are in the millimeter 

range. At each step up the pyramid, 

Figure 1. Cu electroplating can be found at every level of the electronics device interconnect hierarchy. 

(Rohm and Haas) 

there is more evidence of copper plating, 

including vias, wiring circuits and 

bond pads, which are all formed with 

copper. 

As each level changes, however, the 

size of the plated structure also changes 

in dimension by 10-1000X. 

Damascene Structures 

As the structures become smaller, the 

difficulty of Cu electroplating increases. 

The finest and most exacting structures 

are the internal IC interconnections— 

the copper Damascene structures. (The 

SEM in Figure 2 illustrates Damascene 

structures before chemical-mechanical 

polishing.) 

Between the Damascene level and the 

chip-to-lead level is the wafer-level 

packaging (WLP) level. WLP is where 

the most recent developments in copper 

plating on wafers has occurred, including 

one emerging technology not yet 

included in the hierarchy, TSV manufacturing. 

WLP Copper Plating 

Damascene and WLP plating are the 

two main areas of wafer fabrication that 

use copper plating. 

Damascene plating is performed in 

the wafer fab. There, copper is used 

chiefly to replace sputtered aluminum; 

its function is to interconnect regions of 

transistors within the chip. These wiring 

layers facilitate distribution of power 

and intra-chip communication between 

transistors. They may consist of one to 

eight discrete wiring layers. 

The top wiring layer brings the 

desired signals to the surface of the die 

in the form of bonding pads, allowing 

signal I/O and power-and-ground 

access between the chip and package. 

Damascene chemistry is typically 

made with lower concentrations of 


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Figure 2. This SEM illustrates copper-plated 

Damascene vias before chemical-mechanical 

polishing. (Rohm and Haas) 

copper sulfate and higher concentrations 

of sulfuric acid. Included in the plating 

bath are three organic compounds: a 

grain refiner (accelerator), a suppressor, 

and a leveler. 

The chemistry is certified to be free of 

foreign particles to sub-micron levels, 

and wafers are plated in tools that can 

assure void-free copper deposits. The 

plating rates are low, typically 0.2- 

0.5µm/minute, and the plating times are 

short, ranging from 2-10 minutes. 

WLP is the other area where copper 

plating is widely applied to wafers, and 

 

this usually occurs in a dedicated packaging 

facility, normally separate from 

the IC fab. 

In the wafer-level packaging operation, 

there is a diverse use of copper 

plating, with most of it applied to the 

die while in wafer form; thus, it is called 

WLP copper plating. In WLP operations, 

copper is used to form an intermediate 

(2-15µm) under-bump metallization 

(UBM) structure used in flip-chip 

bumping. (Figure 3 shows copper UBM 

below plated SnPb.) 

Figure 3. Copper UBM below plated SnPb. 

(SEMITOOL) 

Redistribution 

Copper is also applied to form I/O 

redistribution on chip-scale packages. 

On CSPs, copper is plated (0.2-5.0µm) 

onto a deposited dielectric layer forming 

circuits that “redistribute” the bond 

pads from the original site to a new 

location within the die. (Figure 4 shows 

copper-plated redistribution.) 

UBM and redistribution copper plating 

chemistry are typically composed of 

moderate concentrations of copper sulfate 

(100-125 gr/lt), moderate concentrations 

of sulfuric acid (150-200 gr/lt) 

and two organic components: a grain 

refiner and a suppressor. 

The plating rates are typically 0.5- 

2.0µm/minute, with plating times of 5- 

20 minutes. More recently, copper pillars 

of 40-80µm heighth have been introduced 

as an alternative to “high lead” 

wafer bumps. 

 

 

 

 

 

 


Current logic/bottom 

package for PoP 

µPILR provides 

fine pitch solution

Figure 4. Copper-plated redistribution 

(IZM Fraunhoffer Institute) 

It is common practice to use highly suppressed 

copper plating solutions in these 

applications to ensure that target plating 

rates and uniformity specifications are met. 

Highly suppressed plating baths contain 

high concentration of specially formulated 

organic suppressors that effectively 

control copper thickness on die in 

areas that tend to “over plate.” 

MEMS 

Micro-Electro-Mechanical-Systems 

(MEMS) are fabricated on special 

wafers and often incorporate copper 

electroplating in the manufacturing 

sequence. 

The manufacturing is performed on a 

variety of wafers, including Si, glass, 

metallic, plastic, and even ceramic. The 

Because the structures are 10X taller than 

copper applied as a UBM, plating rates must 

be increased to maintain productivity. It 

is now common practice to plate copper 

pillars at rates of 2.0-4.0µm/minute. 

(Figure 5 illustrates copper-plated pillars.) 

Electroplating ‘above the Chip’ 

Recently, packaging vendors have begun 

electroplating copper structures “above 

the chip.” In this process, thick mechanical 

and electrical structures are formed 

on top of the passivation layer. 

Examples of these structures are 

inductor coils used in building on-chip 

filters, mechanical standoff structures, 

and heat sinks for large, current-carrying 

components. (Figure 6 shows a copperplated 

coil test structure.) 

For “above the chip” plating, copper 

thickness may range from 5.0-40µm 

and generally demands tight requirements 

for intra-chip co-planarity and 

flatness. The plating rates are typically 

0.5- 3.0µm/min, with plating times of 

10-60 minutes. 

Figure 5. Micrograph shows an array of copperplated 

pillars. (Rohm and Haas) 

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Figure 6. Copper-plated coil (Rohm and Haas) 

range and scope of plated structures is 

diverse, and fascinating new devices 

appear on the market continually. 

(Figure 7 illustrates a MEMS device 

built with copper and nickel.) 

The plated copper structures on a 

MEMS device range from 0.5-200µm in 

dimension, and generally have specific 

plated-copper mechanical requirements. 

The plating rates are typically 0.5- 

2.0µm/minute, with plating times of 10 

minutes to several hours. 

Through-Silicon Vias 

Manufacturing of TSVs is the newest 

WLP development that uses copper 

plating. Vias have been formed and 

plated in many electronic substrates 

over the past 20 years. With the advent 

of chip stacking, however, micron-sized 

vias in silicon need to be filled quickly 

with a highly conductive material. The 

metal of choice has become electroplated 

copper, as shown in Figure 8. 

The example shown in Figure 9 

depicts a “Via First” TSV process. The 

criteria for successful copper via filling 

The EMC-3D Consortium 

Promotes TSV Manufacturing 

A consortium of equipment and materials 

manufacturers has been formed to 

investigate the TSV manufacturing 

process. Known as EMC-3D, for 

“Equipment and Materials Consortium 

for 3D Interconnects,” this organization’s 

charter is to develop cost-effective 

methods using commonly available 

tools and materials for fabricating TSV 

production wafers. [emc3d.org] 

is that the filling process be relatively 

fast and the resulting plating be voidfree 

with a minimal amount of surface 

over-plating. 

Because the vias can take many different 

shapes and sizes (straight wall, 

tapered wall, high- or low-aspect ratio) 

it is quite a challenge to tailor a plating 

process to meet all these requirements. 

Table 1 shows plating conditions that 

affect copper via filling. 

The Wafer 

The seed layer is the key to successful 

via filling. Without a continuous seed 

layer, there can be no void-free electroplating. 

It is necessary to condition the side 

walls using a dielectric and an adhesionpromoting 

metal stack before applying 

the copper plating base. As the aspect 

ratio and side-wall angle of the via 

increases, it becomes more difficult to 

deposit these layers using vapor deposition 

methods. 

Complete wetting inside the via by the 

plating solution is necessary to minimize 

voids at the bottom of the via. It is 

important that the electroplating begin 

simultaneously in all vias. 

With complete via wetting, the odds 

of complete filling are greatly increased. 

During the plating process, copper ions 

are reduced to copper metal. The rate of 

occurance is dependent on the concentrations 

of copper ions inside the via. 

A layer of copper ions is intimately 

close to the seed layer, and it is continuously 

depositing and building metal 

thickness. The consistent transportation 

Figure 7. A MEMS device built with copper and 

nickel plating. (Microfabrica) 

of fresh solution into the via assures this 

process can continue at a high rate. 

The Plating Tool 

The tool must provide adequate solution 

agitation at the surface of the wafer, 

thus affecting the mass transport of 

copper ions into the via. Electrical contact 

of the power supply to the wafer 

and the power supply waveform are 

important aspects of the tool design. 

The power supply waveform can influence 

the deposition rate and morphology 

of the copper inside the via. A direct 

current (DC) waveform is currently the 

most common method deployed to plate 

wafers, but with the advent of via filling, 

many development fabs are looking at a 

process that uses an electrically modulated 

power supply, referred to as a periodic 

pulse reverse (PPR) process. 

This technology is new to wafer fabricators, 

but has been in use in other 

electronics plating applications for 

many years, so the benefits of PPR are 

understood. For TSV manufacturing, 

PPR provides an increase in copper 

Table 1. Plating Conditions that Affect Copper Via Filling 

Wafer Tool Chemistry 

1. Via shape and aspect ratio 1. Solution flow 1. Additive 

2. Seed layer 2. Electrical contact 2. Suppressor 

3. Wetting 3. Power supply wave form 3. Leveler 

4. Mass transport in via 4. Chemistry temperature 4. Acid 

5. Feature layout 5. Current density 5. Copper 

6. Chloride 

66 


Table 2. Acid Copper Plating Bath Constituents 

Component Chemical compound Concentration (grams/liter) 

Cu +2 CuSO 4 *5H 2 O 25-200 

H+ H 2 SO 4 20-100 

Cl- HCl 20-80 ppm 

Water H 2 O Majority 

Grain refiner Sulfur-bearing compounds 1-20 

Suppressor Glycol polymers 2-50 

Leveler Amine-based dyes 0.5-10 

Figure 8. A copper plated TSV before thinning 


deposition rates inside the via. At the 

same time, PPR is very effective at minimizing 

over-plating of the wafer surface. 

Plating Chemistry 

The third element that affects via filling 

is the plating chemistry. The most commonly 

used acid copper plating baths 

are simple solutions of copper sulfate 

(CuSO 4 *5H 2 O); sulfuric acid; a small 

amount of chloride ion (Cl - ); proprietary 

organic molecules, (commonly referred 

to as “plating additives”); and water. 

In a plating bath, the source of copper 

is, of course, the copper sulfate, 

which, when mixed with acid and water, 

disassociates into cupric cat ions (Cu +2 ) 

and sulfate anions (SO 4 -2 ). 

Chloride ions provide the key function 

of making a chemical link between Cu +2 

ions in solution to the substrate plating 

surface (usually copper) and facilitate 

the action of the plating additives. 

Organic Additives 

Up to three different organic additives 

can be added to the bath: a grain refiner, 

Figure 9. The “Via First” TSV process sequence 


a suppressor, and a leveler. The grain 

refiner smoothes the copper deposit 

and accelerates the overall plating 

process. The suppressor works by 

adsorbing on the copper surface and 

thus interferes with the plating process, 

but preferentially only in the higher 

current density areas. The leveler has 

the effect of moderating the formation 

of microscopic pits and protrusions. 

By varying the concentrations of the 

cupric ion, sulfuric acid, chloride ion, 

and the three organic components, a 

wide range of performance characteristics 

may be obtained. 

Key Characteristics 

A key characteristic for all wafer plating 

is the resulting plated metal uniformity 

over the die surface. Chemistry compositions 

and plating rates have a direct 

effect on die uniformity. 

As a general rule, when the plating rate 

increases, the uniformity becomes 

worse. For many wafer-plating applications, 

the die uniformity tolerance is 

specified at ±5%, and most specifications 

can be met by plating in the range of 

0.5-3µm/minute. 

The constant challenge for tool and 

chemistry suppliers is to improve plating 

rates above 3µm/minute with no 

decrease in die surface uniformity. Table 2 

shows plating bath constituent chemicals. 

Conclusion 

Copper-plated interconnects are everywhere 

in electronics packaging. For 

many years, these interconnections have 

been made with electroplated copper. 

Plated copper has evolved and is now 

incorporated into IC manufacturing in 

the form of copper Damascene plating 

and into several WLP applications. The 

next frontier for copper plating is TSV 

manufacturing. 

This technology is being driven by 

the need to advance IC packaging to 

smaller geometries and higher performance. 

Increased speed and reduced size 

are driving the next level of die stacking 

which will exclude wire bonding in 

favor of TSV chip stacking. i 

Mr. Forman is the 

sales manager for 

semiconductor 

advanced packaging 

at Rohm and Haas 

Electronic Materials 

LLC, Packaging and 

Finishing 

Technologies. He received a bachelor’s 

degree in chemistry from the University 

of Oregon, and began his career in the 

electronics industry at Tektronix. 

He has been involved in electronic 

materials engineering and manufacturing 

for the past decade with Rohm and Haas. 

During that time, Mr. Forman has held a 

variety of positions in technical and sales 

management. His current role is in the 

development and promotion of materials 

that address the needs of wafer-level 

packaging. [bforman@rohmhaas.com] 


Handling and Processing Technologies Utilized 

In a High-Volume Manufacturing Environment 

As semiconductor manufacturers 

continue to squeeze the thickness of 

devices and wafers down, new and 

disruptive methods to meet the manufacturing 

challenges associated with 

new products and processes have to be 

utilized. Emerging products require 

thinner and more fragile substrates for 

complex devices. This article discusses 

how to insert thin-wafer processing 

into a high-volume manufacturing 

environment. 

By Stefan Pargfrieder, Paul Lindner, 

Steven Dwyer and Thorsten Matthias, 

EV Group, Linz, Austria 

[evgroup.com] 

Emerging products such as RFID 

tags, more sophisticated chip 

cards and ever-denser memory devices— 

with the advent of new advanced packaging 

technologies—require increasingly 

thinner substrates. 

Fragile—Handle with Care! 

While thin silicon, as well as compound 

wafers, exhibit increased flexibility— 

which in some cases is actually desired— 

these wafers also exhibit increased instability 

and fragility. 

The lack of mechanical stability and 

the increased fragility present major 

challenges to maintaining high-yield 

levels in volume manufacturing environments. 

Reliable handling and support solutions 

are therefore needed to overcome 

the challenges of working with thin 

wafers, while maintaining yield levels 

compatible with low-cost, high-yield 

manufacturing. 

The solution of choice must enable 

safe, reliable handling of the substrates 

through processing steps, while being 

This fully automated temporary bonder is shown with dry-film lamination. (EV Group) 

compatible with existing equipment 

lines and processes. 

Two Approaches 

Two complementary approaches for thin 

wafer processing for implementation into 

a high-volume manufacturing environment 

will be discussed (Figure 1). 

As a first consideration, processing of 

unsupported thin wafers could be utilized. 

The main challenge of this 

approach relates to the safe and reliable 

handling and storage techniques. These 

handling and storage methods are critical 

both within the production line and 

in individual process steps, equipment 

and process modules. 

Second, we will examine temporary 

bonding and debonding technology. 

In this bonding method, the original 

thick-device wafer is temporarily bonded 

onto a rigid carrier wafer before thinning 

and additional backside processing 

steps are accomplished. 

At the end of these backside processing 

steps, the thin-device wafer is debonded and 

transferred into a dedicated output form. 

The main driving forces for ultra-thin 

semiconductor devices can be found in 

high-integration microelectronics, 

System-on-a-Chip applications, power 

semiconductors and in the compound 

semiconductor industry (III-V, II-VI), 

as well as others. 

Thin, Unsupported Wafer Processing 

To enable processing of already thin, 

unsupported wafers, the main difficulties 

are based on their flexibility, brittleness 

and fragile behavior, as well as on 

the potential bow and warpage of those 

substrates. 

Due to those properties, the main 

challenges are shifting towards handling 


INDUSTRY NEWS 

Chip Scale Review Teams with Technology Seminars 

San Jose—Chip Scale Review has 

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seminars and training courses. 

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Figure 1 (left). Using two complimentary technologies may enhance manufacturing and processing of thin 

semiconductor devices at the wafer-level. Figure 2 

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thinned wafers, at least four alternatives are available. 

industrial, business and university 

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fundamentals. 

“On-site training seminars are a 

highly cost-effective means of 

increasing skill levels at all levels of 

staffing. Because we bring the 

courses to you, employee travel and 

lodging expenses are eliminated,” 

noted Harper. For information, 

contact TSI at charptsi@erols.com. 

issues, requiring dedicated storage and 

transport boxes in place (Figure 2). 

The four types of storage and handling 

units are, first, dedicated wafer cassettes 

with a dedicated design for holding thin 

wafers (13 slot). The second alternative 

is storage and transfer of thin wafers in 

a coin-stack box. The third alternative is 

to select single-wafer carrier boxes, 

where each wafer is placed into an individual 

box. This media is also utilized in 

manufacturing environments. The final 

alternative is the attachment of the thin 

wafer onto a film frame. 

Each alternative has its own properties, 

advantages and disadvantages. The choice 

is usually based on the requirements and 

boundary conditions that exist in the 

individual manufacturing environment. 

For further transfer of the thin wafers 

onto the process equipment and the 

individual process modules, dedicated 

handling capability has to be available. 

Application Example 

An application example for the transfer 

of thin wafers from a double-pitch cassette, 

is a dedicated robot end-effector 

(Bernoulli), which is combined with a 

vacuum-enforced transfer technology 

on each individual process module. 

This approach allows the safe and 

reliable pick-up of the wafer from the 

cassette, by first planarizing the wafer 

and then keeping the wafer flat during 

each individual process and transfer 

step. 

70 


Due to the many potential issues with 

thin wafers, however, this option for 

handling and storage of unsupported 

wafers in a high-volume facility is only 

used if no alternatives exist. 

Temporary Bonding and Debonding 

The best-accepted method in high-volume 

manufacturing to prevent wafer 

damage during processing is to temporarily 

bond the device wafer to a suitable 

rigid carrier substrate. 

Advantages of using a rigid carrier 

include the protection of the active surface 

of the device wafer during grinding 

and polishing procedures and the flattening 

of the extremely warped wafer 

material. (The principle of temporary 

bonding and de-bonding is shown in 

Figure 3.) 

In these operations, the formerly 

thick device wafer is bonded with its 

active surface to a carrier wafer using a 

dedicated intermediate layer. 

After backside processing, including 

the thinning process and further 

process steps (lithography, etching, 

etc.), the thin device wafer, supported 

by the rigid carrier substrate is released 

(debonded) from the carrier wafer. 

Further cleaning of the thin wafer, as 

well as transfer of the thin wafer into the 

dedicated output format (cassette, coinstack, 

single wafer carrier, film frame), 

enables further handling and processing 

such as testing, dicing, or packaging. 

The intermediate material used for 

temporary bonding must be selected to 

ensure that the two wafers are bonded 

together in a reliable way until debonding 

has been accomplished. 

Intermediate Layers 

Several different aspects must be considered 

before selecting the type of intermediate 

layer to be employed in the chosen 

application. Major criteria include: 

• Maximum Temperature Capability— 

The maximum temperature capability 

of the intermediate material is a key 

factor 

enabling further 

processes. 

Today’s available 

waxes or 

dry-film laminates 

enable 

maximum 

release temperatures 

up 

to 200°C, 

where newly 

developed, 

high-temperature 

spin-on 

adhesives offer 

the widest range of operating temperatures 

up to 250°C or even higher. As 

a matter of fact, high-temperature 

adhesives are de-bonded by heating 

up to their respective softening temperature 

and further slide-liftoff 

debonded. 

• Achievable TTV—The total thickness 

variation (TTV) of the intermediate 

layer severely affects the back-grinding 

process, as well as the actual thickness 

of the thinned device wafer. Achieving 

highest uniformity of the bonded 

Figure 3. The principle of temporary bonding and de-bonding is shown. 

wafer stack is therefore mandatory to 

ensure highest uniformity during further 

backside processing. 

• Chemical resistance—The resistance 

of the intermediate material to the 

chemicals used during the backside 

processing of the bonded device wafer 

(backgrinding, coating and developing, 

and etching) is a critical consideration. 

A chemical attack can affect the 

properties of the material and, therefore, 

cause unwanted effects during 

further backside processing steps. 

Chemical resistance may also substantially 

change the debonding 

behavior. 

• High vacuum capability—During 

etching processes, particularly, ultrahigh 

vacuum levels are often applied 

to the wafer stack. Trapped air bubbles 

in the interface (due to poor TTV of 

substrate or carrier, poor uniformity 

of adhesive or dry-film laminate) 

tend to discharge through the thinner 

and more brittle device wafer, potentially 

causing damage or yield losses. 

• Ease of processing—This criterion 

mainly involves the ease of material 

application (spin coating in the case 

The total thickness variation (TTV) of the intermediate 

layer severely affects the backgrinding process, as well 

as the actual thickness of the thinned device wafers. 

of adhesives and lamination in the 

case of dry-film tape); the ease of the 

de-bonding process (heat release, UV 

release or solvent release) and the 

degree of achievable automation, as 

well as the ease of cleaning of the 

device wafer after de-bonding. 

Materials 

Today’s available intermediate materials 

include dry-film adhesives. Commercially 

available thermal release films are usually 

laminated with their permanent adhesive 

side onto the carrier wafer, while the thermal 

release side is bonded to the device wafer. 

Maximum process temperature is limited 


elow 150-180°C. Debonding is done by 

heating or UV-exposure and subsequent 

wedge lift-off. 

Waxes, another intermediate material, 

are usually applied to the carrier wafer 

with a dedicated coating system. The temperature 

capability of the waxes is typically 

below 150°C. Debonding is done 

by heating and subsequent slide-liftoff. 

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Figure 4. This debonder is designed for thermal 

release de-bonding. 

Spin-on adhesives in conjunction with a 

newly developed class of high-temperaturecapable 

thermoplast materials, are 

applied by spin coating the wafer before 

bonding. The temperature capability 

actually goes up to 250°C; further development 

activities will enable 300°C or 

even higher spin-coating temperatures. 

For debonding, a slide liftoff is performed 

after heating up to the softening 

point. 

Temporary Bonding 

Reversible wafer bonding using low or 

high temperature adhesives usually 

requires a spin-coating step in the liquid 

phase, where the highest level of 

uniformity for the spin-coated adhesive 

is essential. 

A new temporary bonding platform 

is configurable for processing various 

spin-on materials and includes a coating 

station, hot plates and bond chambers. 

First, the device wafers are spin-coated 

in a coating module. The thickness of the 

spin-coated adhesive layers may range 

as high as some tens of microns, 

depending on the topography which has 

to be covered in the wafer interface. 

Prior to bonding, a bake step is performed 

to remove the solvent. The bond 

occurs in the bonding chamber under a 

controlled atmosphere. To ensure bubble-free 

bonds, this step is performed 

under vacuum and controlled temperatures 

for highest uniformity. 

Dry-Film Laminates 

The recently increasing popularity of 

dry-film adhesive tapes, especially for 

thermal-release bonding in the thinwafer 

industry, may be attributed mainly 

to the enhanced thermal release temperature, 

the improved TTV (

Figure 5. This process flow illustrates the dry-film lamination module of a fully 

automated temporary bonder for dry-film adhesives. 

temporary bonding platform. The 

device wafer will be bonded to the laminated 

carrier substrate in a bond chamber 

under controlled process parameter 

(vacuum, temperature, force). 

Advantages of the punching technology 

compared to the cutting technologies 

(laser and blade cutting), are better edge 

quality, no carrier-edge degradation 

through cutting blades, and more flexibility 

in the tape dimension. 

Shapes are also improved (a tape 

diameter smaller than the carrier substrate 

diameter is possible, enabling 

pyramid-structured assemblies for minimum 

wafer-edge breaking rates) and 

no wear of the punching module. 

Debonding 

After the dedicated backside processes 

are finished, the debonding process 

takes place. 

First, the selection of the appropriate 

debonding method (wedge-lift off, slide 

lift-off, UV debond) has to be selected, 

see Figure 5. This selection depends on 

the type of intermediate material, which 

originally was used for temporary 

bonding. A thermal release slide lift-off 

is performed and waferstacks with thermal 

release tapes are debonded using 

wedge lift-off. 

After debonding, 

the thin wafer 

is transferred to 

the single-wafer 

cleaning station, 

where the 

remaining intermediate 

material 

is removed. 

Both wafers 

(the device wafer 

and the carrier 

wafer) are 

cleaned at this 

station. (Again, 

the selection of 

cleaning method 

and solvent 

depends on the type of the intermediate 

material.) After cleaning, the thin wafer 

is transferred into the dedicated output 

format (thin wafer cassette, coin-stack 

module, single wafer carrier or film frame). 

On the debonder in Figure 4, the 

processed wafer stack is separated 

through a slide lift-off step. The thin 

device wafer, supported through a dedicated 

thin wafer handling technology, is 

further transferred to the cleaning station. 

Finally, the thin wafer is unloaded onto 

single wafer carriers, whereas, alternatively, 

film-frame mounting, or unloading 

in thin wafer cassettes may be accomplished. 

Finally, the carrier is cleaned at 

the cleaning station before re-use. 

Summary 

This article introduces equipment technology 

for the high-volume manufacturing 

thin-wafer industry. Fully automated 

temporary bonding equipment is 

capable of mounting the device wafer 

onto a carrier substrate with its active 

side facing the intermediate adhesive 

layer, thus preparing the device for 

secure and reliable backgrinding and 

backside processing steps. 

The intermediate adhesive layer can 

either be applied in liquid form (adhesive, 

wax or thick resists), via spin coating, or 

in rigid form (dry-film adhesive tape) 

with fully automated lamination. 

After completing backside processing 

of the back-thinned device wafer, it can 

be debonded in a fully automated manner 

onto the new debonding platform. 

After cleaning and removal from the 

remaining intermediate material, the 

thin wafer will be transferred to the 

dedicated output format to enable further 

safe and reliable handling and processing. 

i 

Mr. Pargfrieder is the business development 

manager for the EV Group. He is a 

graduate in technical physics from the 

University of Linz, Austria. He received a 

master’s degree in collaboration with 

Infineon Technologies in semiconductor 

metrology. Mr. Pargfrieder is responsible 

for EVG’s thin wafer processing, temporary 

bonding and debonding activities. 

[s.pargfrieder@evgroup.com] 

Mr. Dwyer serves as vice president and 

general manager–North America of EV 

Group. He graduated from the University 

of New England in 1991 with a bachelor 

of business (marketing and management) 

degree. He has managed EV Group’s U.S. 

operations since 2002 from U.S. headquarters 

in Tempe, Arizona. 

[steven.dwyer@evgroup.com] 

Mr. Lindner is vice president and chief 

technology officer at EV Group headquarters. 

His background is in mechanical 

engineering. He began at EV Group in 

1988 as a mechanical design engineer. 

His current responsibilities include new 

technology development, project management 

and process technology. 

[p.lindner@vgroup.com] 

Dr. Matthias is EV Group’s technology 

manager in Schaerding, Austria. He is a 

graduate of the Vienna University of 

Technology, where he received a degree in 

technical physics and a doctorate in solidstate 

physics. He is currently responsible 

for high-precision wafer alignment and 

wafer-bonding systems. 

[t.matthias@evgroup.com] 


AkroMetrix unveils the LineMoiré J5000 

at SEMICON West 2007! 

The J5000 breaks new ground for high-volume, 

automated flatness measurement. 

The J5000 is the 

latest advance in 

our respected 

LineMoiré 

product line and 

provides powerful, 

full-field, noncontact 

measurement of substrate and material 

topography. 

In-tray inspection 

The J5000 enables in-tray parts inspection at data 

acquisition speeds of about 1s/JEDEC tray with z-axis 

sensitivities of 2~5 micron or better. 

Up to 5000 parts/hour 

The J5000 can analyze an entire tray of parts, 

combined with tray stacking/de-stacking capability. 

Based on 24 parts/tray and a 6 percent failure rate, 

the J5000’s output can exceed 5000 parts/hour! 

Replaces bad parts automatically 

The J5000’s automated handling system can replace 

bad parts in the tray with known good parts, and then 

stack good trays and bad trays separately! 

Applications for flatness measurement: 

• Flip-chip substrate measurement 

(Level 1 and Level II interconnect areas) 

• Finished packages, ICs 

• Package lid, cavity and flange 

• Heat sinks 

• Substrate “out of pocket,” tilt and missing-part 

determination 

• Die-to-substrate tilt (pre-wire bond; 

pre/post underfill cure) 

• Die flatness (post-underfill cure) 

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Visit us on the Web at www.akrometrix.com

Projection Scanning: Not a New Kid on the Block 

What’s the best photolithography tool 

for your wafer-level packaging applications? 

In this article we’ll take a 

close look at projection scanning and 

compare it to 1:1 wafer steppers and 

proximity alignment systems. 

By Jim Sooy, San Jose, Calif. 

[jesanda.com] 

Making an investment in a 

photolithography tool for 

wafer-level packaging requires more 

than a cursory decision. Every machine, 

from the 1:1 wafer stepper to the competing 

proximity aligner or projection 

scanner is a capital investment, and 

may cost from several hundred thousand 

to over $2 million. 

No Single Answer 

There’s no one single answer, agree Doug 

Mitchell at Freescale Semiconductor, 

Raul Lopez at Touchdown technologies, 

and Doug Ridley at Power Integration. 

“It’s kind of like going to dinner on a 

Saturday night. Some of us drive a Toyota, 

some drive a Cadillac and some a 

Mercedes, but we all get to the same 

place,” observes Mitchell. 

“If you get into a conversation about 

their choice of vehicle with any one of 

the drivers, you’ll find they measure performance 

and the cost of ownership in 

more than one way and so do photolithography 

equipment buyers!” he adds. 

Although numerous arguments are made, 

sellers and buyers or tool manufacturers 

and wafer-level package producers consistently 

agree on two things: 

Performance is part of the cost equation, 

and the choice of tool is all about cost. 

Cost, Performance Key Criteria 

Now, if everyone measured performance 

and cost in the same way, would each 

Figure 1. Projection scanning, introduced in the 1990s, is not the new kid on the block, but it is vying for 

market share against 1:1 wafer steppers and proximity aligners. (Tamarack Scientific Co.) 

system be an equally worthwhile tool? 

Of course, that doesn’t happen! 

Each system, according to its manufacturer 

(who hopes to sell one or more 

to every user), has advantages over the 

other. (See “Lines in the Sand,” Chip Scale 

Review, July 2004; and “How Machine 

Suppliers View the Market,” Chip Scale 

Review, July 2003. 

The capital cost of a proximity mask 

aligner is the least expensive, with steppers 

on the high end and projection 

scanners somewhere in the middle. 

While mask aligners are the least 

expensive tools for WLP, a buyer makes 

several measurable tradeoffs regardless 

of the tool choice. 

Tradeoffs 

For example, a stepper buyer sacrifices 

throughput for tight CDs; a scanner 

buyer accepts global alignment for 

throughput, and a proximity aligner 

user may forego throughput and/or 

machine life for the lowest acquisition 

cost. Measuring return on investment 

by acquisition cost, maintenance, performance, 

versatility, and yield are convincing 

more and more manufacturers 

to choose a scanner for wafer-level 

packaging, according to Matt Souter of 

Tamarack Scientifc Co., Corona, Calif., 

whose company manufactures steppers, 

scanners and aligners. 

A stepper is most ideal when an 

application requires independent, siteto-site 

alignment. This advantage, however, 

may be a double-edged sword, 

since each die image must be stepped, 

which significantly reduces throughput. 

The projection scanner on the other 

hand (seen in Figure 1), like the mask 

aligner, does not rely on stepping, but 

employs a full-field mask, which allows 

non-repeated features to be imaged at 

the same time. This feature makes it 

ideal for applications where global 

alignment is sufficient and higher 


Figure 2. Depth of focus as shown by a projection 

scanner in an SEM. 

throughput is desired or required. 

(Figures 2, 3 and 4 illustrate the projection 

scanner’s depth of focus and contrast.) 

Projection scanners also deliver the 

added benefit of an extended range depth 

of focus, making them a logical choice 

where bowed wafers, wafers with topography 

and/or thicker resist profiles are 

required, according to both Lopez and 

Mitchell. 

To compare the optical resolution of 

a scanner with a stepper, consider that 

the typical stepper has a DOF of 10.0µm 

at 5.0µm, while today’s projection scanners 

deliver 45.0µm at 

5.0µm. 

The paramount sidewall 

angle control is a 

direct result of the projection 

system’s ability 

to selectively focus the 

projected artwork 

image at optimum 

depth. In addition, a 

series of low-distortion 

projection lenses combined 

with uniform 

illumination deliver 

superior dimensional 

consistency. 

Power Integration 

builds high voltage ICs 

for cost and energy efficient 

power conversion. 

Ridley, the company’s 

assembly foundry manager, 

says,“The fundamental 

difference between projection 

scanners and proximity aligners is the 

use of projection optics versus the shadow 

mask. 

“The image quality of a contact or 

proximity aligner is directly affected by 

diffraction of the light passing through 

the photomask. The diffraction effect 

increases and the image quality is 

diminished as the breach between the 

mask and the wafer widens.” 

Ridley adds, “When looking at the 

alignment accuracy of an aligner, one 

has to consider not only the accuracy of 

the tool, but the possible misalignment 

due to UV declination. 

“The placement and the alignment of 

a feature can also be affected by the declination 

angle (DA) or the shifting of 

this feature.” 

Ridley adds if a company is planning 

to move from an aligner to a stepper or 

a scanner to increase throughput, 

another consideration is that a new 

inventory of masks will be required for 

a stepper, but not for a scanner. 

“This is a significant cost savings in 

itself,” Ridley says. “And with aligners, 

there is always the “mouse bite” effect to 

consider, and the possibility of reliability 

issues from design rule violations 

when imaging resists for a gold bump 

application.” 

Misalignment 

This misalignment increases as the tool 

is moved from the center of the substrate. 

Maintaining resolution and control of 

critical dimensions can be difficult with 

aligners, which use collimated light, 

according to Ridley. 

Because the scanner, he notes, illuminates 

a much smaller area at a time, it 

controls uniformity to a much greater 

level. As resists become thicker, the traditional 

aligner has difficulty delivering an 

accurate image transfer, Ridley contends. 

Touchdown Technologies designs, 

manufactures, and markets advanced 

MEMS probe cards that are both scalable 

and reliable. 

Touchdown’s Lopez, who is the company’s 

equipment engineering manager, 

says, “We considered buying a new gen- 

Ready to Buy a WLP Tool? 

Here are 10 questions you might ask when you’re ready 

to investigate the purchase of a photolithography tool for 

wafer-level packaging: 

1. What kind of yield will your tool deliver for my 

applications? 

2. How much wafer bow will your tool handle? 

3. What Critical Dimensions will your tool hold? 

4. What wafer thicknesses will your tool accommodate? 

5. Can I process a variety of wafer sizes on the 

same machine? 

6. Can I achieve 90° side walls with my current resist? 

7. Will your tool target blind vias? 

8. Will we be able to isolate specific wavelengths? 

9. Will I be able to process both ceramic and 

silicon wafers? 

10. Can we use our current mask library? 

76 


Figure 3. SEM of projection scanner produced 

MEMS image with 860 micron thick SU-8 resist 

eration aligner as well as a stepper, but 

chose a scanner, instead, because of its 

performance and the scanner’s ability to 

meet both our current and anticipated 

needs due to our rapid growth. 

“While both scanners and aligners 

reproduce images in photosensitive 

films, scanners are much more accurate 

in thick, 50µm, or more, films. 

“Unlike wafer fabrication, the waferbumping 

process requires reproduction 

in thick photoresists, making CD control 

much more important if you are to 

achieve uniformity in bump height 

across the entire wafer,” Lopez adds. 

Additional Considerations 

“Another consideration is mask cleaning,” 

says Lopez. Mask cleaning is a continuous 

process and a significant cost when using 

proximity printers or mask aligners and 

there is always the risk of causing damage 

to the mask during the cleaning process. 

“If you employ pellicles with a proximity 

printer or mask aligner to protect 

the mask, as you can with a scanner, 

you increase the exposure gap, which, in 

turn, reduces imaging capability.” 

Lopez says to improve imaging capability 

with Touchdown’s proximity 

aligners “required working with narrower 

and narrower gaps between the 

mask and wafer which increased resist 

out-gassing and static charges.” 

Imaging improvement in-turn reduced 

throughput from time-outs to clean the 

mask, he observes. “Finally, there was the 

time it takes for changeovers. We run a 

variety of substrates from 3" x 3" up to 

24" x 24" in size.” 

According to Lopez, changeover with 

proximity aligners consumed about 10 

minutes. 

Mitchell is a distinguished member of 

the technical staff at the company’s 

Technology Center in Austin, Texas. 

“Like mask aligners, the scanner images 

with a full-field mask which means the 

scanner can print all features in a single 

exposure without the need to stitch 

fields or step-and-repeat without multiple 

masks for non-repeated features.” 

No Mask-to-Wafer Contact 

Unlike aligners, there is no mask-to-wafer 

contact because the image is projected 

through the lens and onto the wafer. 

This eliminates yield defects that might 

be propagated by incidental wafer to mask 

contact, Mitchell points out. 

“In our scanner, the mask and wafer 

are aligned by non-contact air planerization 

and move together as a unit 

under the projection lens in a serpentine 

motion until the entire wafer has 

been imaged,” he says. 

“The adjustable NA allows us to easily 

change the DOF to match process requirements, 

making it ideal for bowed wafers. 

This focus flexibility makes for excellent 

wall angle control and resolution,” he adds. 

Continuously Evolving 

Projection scanners have continuously 

evolved since their introduction in the 

early-to-mid 1990s. 

Current models include precise substrate 

alignment stages; fully automated throughthe-lens 

alignment systems; high-powered, 

high wafer-plane irradiance illumination 

systems; multiple-size wafer handlers; 

and automated mask handling. 

An important benefit of the projection 

scanner is that it is able to maximize 

illumination intensity for the large exposure 

dosage frequently required for high 

aspect ratio imaging with thicker resists. 

Photolithography with projection 

Figure 4. SEM shows a thick resist image with 

walls 70 microns high x 10 microns wide. 

scanning provides broadband illumination 

from 350nm to 450 nm. Users may 

optimize the exposure process by isolating 

specific wavelengths for a broad 

range of positive or negative resists 

from a few microns to >100 microns. 

The scanner’s optical and mechanical 

design provides a uniquely large DOF, 

making it ideal for imaging wafers with 

topography or bow, and with thin or 

thick resists. 

Tamarack’s Souter says, “To ensure 

successful volume production in a costcompetitive 

environment, device manufacturers 

and wafer foundries, especially 

those in a growth stage, must look long 

and hard at any photolithography tool 

for throughput, yield, versatility, and 

the cost of maintenance. 

Conclusion 

“The primary purpose of any photolithography 

tool is to reproduce an image 

from a mask in photosensitive film. Today, 

there are many applications where that 

reproduction must take place in 50 micron 

or thicker resists. 

“Scanners deliver a large depth of focus 

making them ideal for imaging in either thin 

or thick photoresists,” Souter says. i 

Mr. Sooy is a Northern California-based 

freelance writer, who specializes in writing 

medical and technology features. He has 

more than 400 published articles to his 

credit. He wrote this article for Tamarack 

Scientific Co. [jim@jesanda.com] 

78 


INNOVATE YOUR PROCESS WITH 

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➤ LC Tape (Wafer back surface protection film) 

➤ UV Dicing Tape for Thin Wafer 

➤ Anti Static UV Dicing Tape for Packages 

➤ Wafer mounting systems 

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Phoenix, AZ 85048 USA 

Tel: +1.480.966.0784 

Email: Info@lintec-usa.com 

www.lintec-usa.com 

Advanced Sn-Ag Bumping 

Sn-2.5%Ag Bump (TS-202) 

Mitsubishi Materials introduces a new brand of lead-free wafer bumping 

solution: 

SULA TS-140 and TS-202 (high-speed) are advanced Sn-Ag alloy plating 

chemicals, which have the following advantages: 

• High-speed plating 

• Super ultra-low alpha

“ 

– A D V E R T O R I A L – 

Thinking Big Is the Growth Strategy at ATE 

Test Tooling Solutions Provider TTS Group 

Think Big” is the five-year 

growth strategy through 2010 

at Penang, Malaysia-based Test Tooling 

Solutions Group (TTS Group). 

TTS Group, says CEO S. L. Wee, “aims 

to be a leader in integrated ATE test 

solutions in the region with an emphasis 

on customer focus, operating excellence 

and close proximity to our customers. 

“Furthermore,” he adds, “our focus is on 

lowering the total cost of final test for our 

customers through the relentless pursuit 

of innovation, yield, quality, reliability 

and on-time delivery. We understand 

our customers’ needs and provide onestop 

solutions for all their concerns.” 

With operating headquarters in 

Penang, the company has diversified 

throughout the region with facilities in 

China, Singapore and Thailand. The 

Group’s extensive line of products and 

services includes test probe and PCB 

design, simulation, fabrication, manufacture, 

assembly and validation; burnin 

boards and ATE boards. 

Turnkey Services 

TTS Group offers full turnkey services 

for an extensive array of products, says 

Mr. Wee. “Our design center is capable 

of designing pins, sockets, BiBs and ATE 

boards. Our in-house autolathe and 

SMT assembly facility are able to fabricate 

pins and test boards based on exact 

customer specs.” 

S. L. Wee, Chief Executive Officer 

On-site labs at the Group’s facilities 

are equipped to perform a complete 

range of mechanical, electrical, thermal 

and structural simulation and analysis. 

The Group has invested more than 

$2 million in R&D equipment including 

x-ray, SEM, cycling and testers. Apart 

from in-house R&D capability, the 

Group also works closely with local 

government institutions and universities 

to develop the future technology 

roadmap for the final test industry. 

Test Probes 

The Group is justly proud of its reputation 

for superior quality custom and 

off-the-shelf spring test probes. It is able 

to customize a wide variety of low-volume 

probes with blazing-fast turnaround 

time. The Group designs and fabricates 

pins of up to 0.2mm fine pitch and 

20GHz bandwidth for high current and 

low resistance testing solutions. There 

are more than 500 customized designs 

in the database. 

Load Boards 

The facilities offer complete services for 

ATE Boards, including the design and 

engineering expertise needed for building 

complex and customized socket and loadboard 

solutions up to 50 layers with 30:1 

aspect ratios, micro-drilled and impedance 

controlled for Advantest, Agilent, 

Fusion, Teradyne and other testers. 

Burn-in Boards 

The Group guarantees optimized burn-inboard 

solutions every time.“We design and 

manufacture burn-in boards for systems 

built by Despatch, MCC, Reliability Inc., 

Wakefield and others,” Mr. Wee notes. 

PCB Assembly 

The on-site assembly facility features 

both conventional through-hole and 

surface mount technologies. “We provide 

a full range of services. These include 

engineering development and support, 

schematic, PCB layout, design assembly, 

prototype build and test service, system 

build to final packaging and distribution.” 

The company is multi-cultural and 

“The majority of our employees are 

bilingual with English as the primary 

business language,” Mr. Wee says. “We 

also have employees who are fluent in 

Chinese, Japanese, Bahasa Malaysia and 

French.” ❖ 

80 


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Hesse & Knipps Announces Several BJ920 Enhancements 

Paderborn, Germany—Hesse & Knipps 

GmbH has announced several major improvements 

to its BONDJET BJ920 heavy wire bonder, 

including the integration of both pull- and 

shear-test functions into the bond head. 

These functions, according to H&K, have 

been added without affecting the free space 

around the bond head or limiting applications. 

Enhancements to the BJ920 include 

patented Process Integrated Quality Control 

(PIQC). This system enables the acquisition 

and assessment of several feedback values 

that influence bond quality. 

H&K says PIQC is being tested in the field and 

will soon be incorporated into the machine. 

Other enhancements will include an “active” 

cutter system on the bond head. This unit has 

been decoupled from the Z-axis and requires 

no pusher, which increases the available bonding 

area inside packages. 

The company claims this system enlarges 

the setting window for cutting, allowing a 

much quicker cut process. Accuracy, H&K 

adds, is highly repeatable and greatly reduces 

the risk of cutting into the substrate. Cutter 

lifetime will also be increased as a result of 

the new system. 

An additional enhancement is vibration 

The BJ920 BONDJET is being fitted with several 

enhancements. 

elimination, employing a state-of-the-art sensor 

and technology to ensure that machine 

vibrations either do not occur or do not 

impact the wire bonding process negatively. 

The touchdown and deformation sensor 

on the BHJ920 offers a resolution of 0.1mm, 

“with virtually no signal propagation delay and 

no calibration needed.” [hesse-knipps.com] 

Ironwood Electronics Intros QFN Socket for 0.4mm Pitch 

Minneapolis—Ironwood Electronics 

has introduced a new, high-performance 

QFN socket for 0.4mm pitch 

QFN 40-pin ICs. The socket is capable 

of 100,000 insertions, according to 

Ironwood. 

Known as the DG-QFN40C-01, 

the socket is designed for a 5X5mm 

package and operates at bandwidths 

up to 40GHz with less than 1dB of 

insertion loss. The units will dissipate 

up to several watts without extra heat 

sinking, and can accommodate up 

to 100W with a custom heat sink. 

This Ironwood Electronics socket is designed for QFN [ironwoodelectronics.com] 

package test. 

82 


Advantest Corp. Debuts T6373 LCD Driver Test System 

Tokyo—Advantest Corp. has debuted its 

T6373 LCD driver test system for LCD source, 

gate and one-chip controller-driver ICs. The 

unit is available with up to 3072 chanels and 

offers parallel test for up to 32 devices. 

The demand for large, high-definition LCD 

panels will increase the market for LCD driver 

ICs, a key IC for LCD panels. 

Forecasts suggest, says Advantest, that by 

2010, shipments of these ICs will increase by 

about 45 percent, although that will represent 

a dollar increase of just 7 percent, leading to 

mounting price pressure for manufacturers. 

Advantest says the T6373 will “contribute 

greatly” to test-cost reduction. It offers 512 

channels for digital test of image signal inputs, 

as well as it 3072 output channels. The unit 

provides twice the capacity of its predecessor 

for parallel test of 684- and 720-pin drivers 

ICs commonly used in large LCD televisions. 

The unit offers a high-accuracy digitizer 

unit for each of its LCD channels, enabling 

test of higher bit resolution and pincount ICs 

at a throughput 1.5 times greater than its 

predecessor. [advantest.com] 

The Advantest T6373 offers 3072 output channels. 

OK International Launches 

New Array Rework System 

Garden Grove, Calif.—OK International has 

introduced the APR-5000-DZ array package 

rework system with dual convection, bottomside 

heating. The system is aimed at lead-free 

rework and high thermal demand applications. 

[okinternational.com] 

The APR-5000-DZ array package rework system is 

aimed at lead-free applications. 


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84 


INSIDE PATENTS 

How to File Patents (and Fight 

Patents) Without Tears! 

By A. Jason Mirabito [jmirabito@mintz.com] and 

Carol Peters [cpeters@mintz.com], Contributing Legal Editors, 

Mintz Levin Cohn Ferris Glovsky and Popeo P.C., Boston [mintz.com] 

In this issue, we’re diverging from 

our usual analysis of specific patents 

to focus on the upcoming International 

Wafer-Level Packaging Conference in 

San Jose on September 17-19. 

This column’s two authors will present 

a workshop/seminar at the conference 

on September 17, entitled “Filing Patents 

(and Fighting Patents) Without Tears.” 

The workshop will be directed to 

non-attorneys who, nevertheless, are 

inventors, or who work with inventors or 

inventions in the wafer-level packaging 

industry, and apply for patents to protect 

their intellectual property. 

As readers will also appreciate, there 

has been a significant amount of patent 

litigation in the packaging area. 

Moreover, there is no logical reason to 

believe it will not continue and increase. 

As they say on the gridiron, “The best 

defense is a good offense,” and we’ll 

show you how and why this is also true 

in patent litigation and IP protection. 

How to File Patent Applications 

We will touch on the proper methodology 

for filing patent applications with the 

U.S. Patent and Trademark Office, and 

how to turn such applications into patents 

successfully in the least amount of time. 

The U.S. Patent Office has instituted 

an accelerated application examination 

program which essentially allows applicants 

to file and prosecute patent applications 

from beginning to end within 

about a year. This is a far 

shorter period than the 

“normal” three to four year 

pendancy period for 

applications. 

The accelerated examination, 

however, comes with 

extra costs and extra duties 

which are imposed on the 

applicants and their patent 

attorneys. 

Since our June 2007 column, 

the U.S. Supreme Court has 

issued what some commentators 

have heralded as a 

major change in U.S. patent 

law related to obviousness. 

The Standard of Obviousness 

For those unfamiliar with the standard 

of obviousness, the patent statute basically 

states that a patent will not be 

granted if the differences between what 

was in the prior art and what is being 

sought to be patented would have been 

obvious to a person of ordinary skill in 

the art at the time of the invention. 

While this sounds simple enough, the 

obviousness standard has been one of 

the most controversial provisions, as 

well as the most difficult to interpret, in 

the patent statutes. 

The Supreme Court threw, perhaps, 

another ball into play in the KSR Int’l 

Co. v. Teleflex, Inc., case, which is said 

to have revamped the standard of 

A chief goal of the IWLPC workshop is to help ensure that 

you’re on the right side of justice if you should be involved in 

patent litigation. 

obviousness—particularly for so-called 

combination inventions that combine a 

number of already known elements into 

a new apparatus. 

Many inventions fall into this category. 

Some commentators believe that the 

decision now makes it easier to invalidate 

litigated patents (beneficial if you 

are on the defendant’s side of a lawsuit), 

but it may make it more difficult to 

obtain patents as well. 

As with any Supreme Court case, the 

ramifications will not really be known 

for some time, and we expect by the 

September workshop we may have some 

better guidance as the lower courts 

attempt to apply the law annunciated in 

the KSR decision. i 


10 GREAT REASONS 

TO BE IN SAN JOSE ON SEPTEMBER 17, 18 AND 19: 

1 

2 

3 

4 

Fourth International 

Wafer-Level Packaging 

Conference, Wyndham Hotel. 

Half-day workshops 

taught by experts on 

September 17. 

More exhibits than you 

can shake a stick at on 

September 18-19. 

Annual Thursday panel 

on the state of packaging 

with the industry’s wisest 

forecasters! 

5 

6 

7 

8 

Lots of technical presentations 

covering everything packaging 

and test guys need to know 

about on September 18-19. 

Free parking at the 

Wyndham Hotel located close 

to the San Jose International 

Airport. 

Great place to meet 

your vendors, your customers, 

your friends, etc. 

Register three people 

from your company and the 

fourth is FREE! 

9 

10 

11 

12 

Special rates at the 

Wyndham for attendees. 

Register early and get our 

early bird discount. 

Plenty of sun in 

San Jose! 

Special keynote speaker will be 

Oleg Khaykin, Amkor Technology’s 

Chief Operating Officer. 

(There are so many reasons to be in San Jose at the 

Conference, we couldn’t keep it to just 10!) 

SA N JOSE, CALIFO R NIA 

Jointly presented by: 

INTERNATIONAL WAFER-LEVEL PACKAGING CONFERENCE 

Platinum Sponsors: 

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Visit www.smta.org/iwlpc for more information.

From Cow Chips to Silicon Chips: Setting-Up a WLP 

Microfabrication Facility Far from the Infrastructure 

Setting up a modern facility for waferlevel 

fabrication, chip-scale packaging 

and surface mount technology far from the 

center of semiconductor activity entails 

tough challenges and careful planning. 

This article relates some of the good, 

the bad and the Quasimodo-ugly 

experiences faced by the NDSU staff. 

By Fred Haring, Bernd Scholz, 

Syed Sajid Ahmad and Aaron Reinholz, 

Center for Nanoscale Science and 

Engineering, North Dakota State 

University, Fargo, N.D. 

[ndsu.edu/csne] 

The Center for Nanoscale Science 

and Engineering (CNSE) is a 

university research center located in 

the Research and Technology Park at 

North Dakota State University (NDSU) 

in Fargo (Figure 1). 

This park was created as a venue 

where university researchers and private 

industry can combine their talents to 

develop new technologies, methods, and 

systems. 

Current Park tenants are CNSE, the 

NDSU Department of Coatings and 

Polymeric Materials, Phoenix International 

Corp (a John Deere company), and 

Alien Technologies Corp., a provider of 

UHF RFID products and services. 

Additionally, the Center for 

Technology Enterprise (CTE), designed 

to house entrepreneurial companies and 

extend NDSU’s College of Business 

Administration and College of 

Engineering and Architecture, is located 

in the park. Its purpose is to provide 

students with real-world exposure to 

early-stage entrepreneurship programs. 

The CTE is anchored by Ingersoll- 

Rand Bobcat, a compact vehicle maker. 

Being far away from Silicon Valley—or one of its spinoffs—doesn’t mean you can’t operate a semiconductor 

facility successfully. It just means you might have to try harder. 

Multidisciplinary Research 

CNSE was developed to provide multidisciplinary 

research in polymers and 

coatings combined with the development 

of electronics technology. 

The electronics technology group 

consists of thick- and thin-film technologies, 

chip-scale packaging and surface 

mount technology. Core competencies 

of the Electronics Miniaturization Group 

(EMG) include electronics R&D, electronic 

packaging and R&D, reliability 

analysis, sensor applications, SMT and 

CSP prototyping and failure analysis. 

The organization is geared to deliver 

results within the customer’s timeline 

starting with basic research leading to 

proof of concept, design development 

and testing to establish prototype and 

pre-production fabrication leading to 

commercialization and integration. 

The center is able to handle ITAR and 

EAR controlled programs and provides 

a limited-access secure facility. 

CNSE is divided into two major 

research focuses: The first is materials 

discovery for coatings and electronics 

applications and the second is electronics 

miniaturization. 

This article will focus on the facilities 

for the electronics organization (as shown 

in Figure 2). These cleanroom facilities 

can be classified as thin- and thick-film 

development facilities that are housed in 

Class 100 cleanrooms, and SMT and CSP 

facilities that are housed in Class 10,000 

cleanrooms (Figures 3 and 4). These were 

established with help from Tessera Technologies 

and Alien Technology Corp. 

Facility Requirements 

The focus of this facility was microfabrication 

processes linked to the semiconductor 

and electronics industry. 

Since our goal was to combine a specialized 

polymers and coatings group 

with microfabrication skills, all processes 

had to be evaluated and defined. 


Photos for Figures 1-7 courtesy of NDSU 

Figure 1. This building houses the semiconductor fabrication, chipscale 

packaging and surface mount lab at CNSE/NDSU. 

The basic requirements began with 

projected needs leading to budget, 

equipment sets, floor space and utilities 

(Figure 2). A master list of equipment, 

competitive and accepted suppliers, and 

budget was established. Buyoff agreements 

and procedures were established 

in consultation with Tessera and Alien. 

A purchase specification was created 

for each piece of equipment, 

which defined exact 

functional parameters 

desired for each piece of 

equipment. The specs also 

included space, safety, 

power, utilities, delivery, 

installation, training, support, 

and warranty 

requirements. 

Purchasing required 

three competitive quotes 

from prospective suppliers. 

We performed a thorough 

supplier and equipment 

search to identify the three best suppliers 

and sent them specifications with 

an RFQ. 

Sole Source 

In some cases, a sole-source justification 

document was required if we could not 

identify three suppliers, or if a specific 

machine design or capability was needed 

that was not available elsewhere. 

We preferred new equipment, but due 

to budget constraints we had to settle 

for some certified refurbished equipment 

with warranty. Three-quarters of 

the equipment was new, and one quarter 

of the total-equipment base was 

refurbished. 

After establishing the lab and having 

been exposed to the processes for a 

while, we feel that any critical piece of 

equipment should be purchased new, 

rather than refurbished. Non-critical 

pieces may be purchased refurbished. 

In this article we present some data 

with respect to our experience during 

the equipment purchase. 

Major Criteria 

We defined four major criteria to evaluate 

the quality of service with respect to equipment 

purchase and installation: delivery, 

installation, training, and equipment 

operation after its installation. 


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90 


Figure 3. A section of Class 10,000 SMT and CSP 

facilities at CNSE/NDSU. 

These criteria have been evaluated for 

each piece of equipment. 

Criteria percentages illustrate realworld 

data collected during and after 

setup. (See the sidebar on page 94.) This 

data covers 77 major pieces of equipment. 

Minor equipment, microscopes 

and items less than $5,000 for example, 

was not included in the evaluation. 

Figure 2. This illustrates the initial layout of the CSP/SMT lab at CNSE. The layout follows chip-scale 

packaging and surface-mount processing flows. 

Delivery 

We looked at punctuality. Was the delivery 

on schedule? Was the equipment delivered 


Figure 4. Another section of the Class 10,000 CSP 

facilities. The main production equipment is 

placed along the walls of the lab and support 

equipment is set up on centralized tables. 

in good condition? Was there any shipping 

damage? Were the shipping indicators (tip/ 

tilt, temperature and shock) activated? What 

was the general condition of the equipment 

on arrival? Was it ready for the cleanroom? 

As received, did the equipment have all its 

specified functions and options? 

Most suppliers provided timely delivery, 

but 14 percent did not. Fourteen percent is 

a significant number when a facility is in 

operation and orders are waiting to be filled. 

In today’s fast-paced, high-technology 

environment, the “Just in Time” (JIT) 

concept cannot work with late-delivery 

performance. 

High-tech industry demands on-time 

delivery performance due to its highly 

competitive nature, requiring that new 

products meet projected timelines to 

capture emerging markets. 

Delivery delays seemed to be due to 

poor planning and coordination by the 

manufacturer or shipping services. 

Many times it was possible to read 

between the lines when working with 

suppliers, even during a phone call. If 

the person was prompt, professional and 

had dates, delivery status, and seemed 

to be confident in delivery knowledge, 

usually a timely delivery occurred. 

Delivery was also timely when the 

supplier was able to provide tracking 

information or there was the ability to 

have a written statement on delivery 

time. Additional discounts may be 

negotiated for late delivery. 

Certified Vendors 

It helped to use certified vendors. We 

found that it was necessary to keep track 

of shipping activity on a day-to-day 

basis to alleviate hold-ups at any stage, 

especially during offshore shipments. 

Customs officials required certain 

information and documentation before 

the release of the equipment. A continuous 

contact with the handling agent helped 

minimize or avoid delays. 

Good delivery at site begins with 

receiving conditions. Skilled coordination 

with building and facilities management 

teams, combined with a preset plan of 

attack on how to receive shipments greatly 

alleviated any problems that could occur. 

Asking the shipper if we could be in 

contact with the driver of the delivery 

truck was helpful in identifying exact 

delivery times, in scheduling receiving 

teams and having receiving equipment, 

such as forklifts, etc., ready at delivery. 

Eight percent of the equipment failed 

92 


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How Good Were the Suppliers? 

Figure 5. This is a design drawing of an actual 

product designed and built at NDSU/CNSE. Overall 

package dimensions 9.7 x 9.7mm 

to meet specifications on arrival, although 

the specifications were mutually agreed 

on before the order was placed. 

Sometimes payment had to be withheld 

until the situation was resolved. 

Communications 

The main reason for such problems in 

most incidents was that we were communicating 

with the sales department 

of the supplier. It appeared there was 

miscommunication, or inadequate 

communication, between the sales and 

manufacturing areas at the supplier’s 

facility. 

The equipment was delivered mostly 

according to specification when the 

sales department involved the manufacturing 

representative in the whole purchase 

process, and we could communicate 

directly with both. 

Nine percent of the equipment arrived 

with some damage caused during shipment. 

This is a high percentage and should 

be a matter of concern for the industry. 

Shipping damage to the equipment 

seemed to be caused by very careless 

handling, improper packing and rough 

shipping conditions. Some items appeared 

to have been dropped or had other 

heavy freight stacked on them, causing a 

section or part of them to be crushed. 

Loading or unloading damage seemed 

to be prevalent, illustrating smashing of 

equipment. Some damage was only minor. 

Some equipment had many parts or 

fasteners that had vibrated loose during 

transport. Some damage was due to 

repeated bouncing or vibration during 

transport either by rail or truck. This 

Late delivery, equipment that doesn’t 

work “out of the box,” trainers who can’t 

train, and suppliers who don’t return 

calls were just some of the problems 

that the staff at NDSU’s CNSE 

discovered. 

A supplier that suddenly vanishes after 

the customer’s equipment is delivered is 

a supplier that will not be selling any 

more equipment to that customer—and 

hopefully not to many others, either. The 

information below tells the story. The 

suppliers that left a negative impression 

hopefully know who they are! 

–Editor 

1. Delivery punctual? 

On time 86%, Late 14% 

2. Delivery met specs? 

Yes 92%, No 8% 

3. Arrival condition? 

Good 91%, Damaged 9% 

4. Installation quality? 

Satisfactory 87%, Mediocre 5%, Not satisfactory 8% 

5. Problems installing? 

No problems 77%, Problems 23% 

6. Installation success? 

First attempt 78%, Second attempt 19%, More than twice 3% 

7. Training quality? 


8. Trainer quality? 


9. Specified training time? 

90-100% 66%, 75-90% 20%, 

50-75% 9%, 25-50% 5% 

10. Training met expectations 

Yes 57%, No 43% 

11. Equipment ease of use 

Easy 51%, Somewhat easy 26%, 

Difficult 14%, Quite difficult 9% 

12. Post-installation support 

Adequte 65%, Not adequate 35% 

13. Operational stability 

Good 91%, Mediocre 9% 

94 


Figure 6. A Center technician evalutes assembled CSP components 

attached to a leadframe. 

vibration caused a loss of structural 

integrity of fragile components leading 

to premature failure and breakdown of 

the machine soon after installation. 

In some cases, the equipment had to 

be returned and replaced, while in other 

cases the supplier’s representative had to 

come and fix the equipment. The installation 

schedule suffered either way just 

because the equipment was not packed 

properly or was mishandled by the 

shipping company. Requiring shipper 

and vendor to install tip/tilt, temperature, 

and shock indicators on shipping crates 

would be very beneficial in preventing 

later liability and/or warranty issues 

regarding premature damage and failure 

of the equipment. 

Unpack and Reassemble 

Some shipments came with a procedure 

to unpack and reassemble. Such 

instructions were very helpful in speedy 

unpack and transport to the installation 

site. Many pieces did not come with any 

instructions. For some pieces, we had to 

contact the supplier to make sure that 

unpacking was carried out without 

damaging the equipment. 

One piece of equipment weighed nearly 

nine tons and nobody in the city was confident 

they could move it. Some rigging 

companies estimated $3000 to move it 

from the shipping and receiving area to the 

lab area, a distance of less than 100 yards. 

They also had very 

high commuting costs 

because they were two 

hundred miles away. A 

thorough search of 

three states led us to a 

rigging company sixty 

five miles away that 

did the job very well 

for only $1700. 

The shipping company 

also took care of 

the concern for damaging 

the floor tile en 

route. 

We took pictures of delivery on site to 

record any shipping or handling discrepancies. 

We did not accept poor shipments 

or damaged materials as specified by the 

buyoff agreement. 

We made sure of size, weight, and 

floor limitations. We also took into 

account the access areas, receiving areas, 

hallways and floor plans during order 

and receipt of the equipment. 

Measure Twice 

We faced a dilemma when we discovered 

that a hallway was not what it measured 

on the floor plan. 

We had to have some equipment custom 

made, otherwise it would not have 

cleared the passageways to reach the 

designated spot. Pre-measuring prior to 

ordering, purchasing and receiving is 

absolutely necessary. 

Space considerations should be taken 

into account when the building is designed, 

but sometimes modifications are necessary—especially 

when retrofitting an 

existing facility. 

Installation 

We looked at the quality of installation. 

Was the installation problem-free? Was 

the first install effort successful or was 

more than one effort necessary? 

Some suppliers had a good procedure 

established for installation. They sent 

facilities and materials requirements in 

advance and in writing. Some required 

that a pre-installation form be filled out 

and returned before they would schedule 

their installer. 

They refused to schedule a visit until 

they received a signed form stating that 

all the facilities were in place and all the 

materials had been procured. 

These procedures helped achieve a 

quality on-time installation and training. 

Most of the problems occurred with 

suppliers who did not have proper procedures 

established for installation and 

training activity. 

Some companies sent installers into 

the field that really had no knowledge 

of equipment, software and hardware. If 

the installer was also the trainer, and a 

breakdown occurred that could not be 

fixed, the entire install and/or training 

time was wasted for the supplier and 

the customer. 

Some installers were only distributors 

of the equipment and really had no idea 

how it functioned, and could not teach 

the required operations to the trainees. 

If they were asked a question, they 

could not answer. 

Some wanted to simply finish as 

quickly as possible and leave, whether 

the trainees understood the equipment 

or whether the trainees were able to 

learn how to run the equipment. 

Faulty Equipment 

The first problem we encountered was 

the inability of the equipment to function 

on start-up. The second was missing 

components. The installer discovered 

that some items needed for the operation 

were not included in the shipment. 

The third was form and fit of components. 

Thanks to the availability of 

overnight shipping, many such delays 

were solved by the next morning. Even 

so, this often cut into the training time 

since training followed the installation, 

and could not be conducted until the 

equipment was functional. 

Only three-quarters of the installs were 


successful the first time. The reasons closely 

followed the installation problems. 

Training 

We evaluated whether we were given the 

training time agreed upon in the purchasing 

specification for the equipment. 

What was the quality of the training? 

How well was the trainer able to train 

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the trainees? 

Training is one of the most important 

aspects of equipment procurement and 

installation. How well personnel can 

operate the machine and produce 

desired results is directly related to how 

well they are trained. 

Did the trainer cover the material in a 

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to understand? Does the trainer really 

understand the machine, its operations 

and idiosyncrasies? Training should be 

in an organized and logical process flow. 

Many suppliers did not provide the 

exact amount of time promised for 

training. The training time was greatly 

reduced when some of them used a significant 

portion of the first and last days 

of training for travel. For a three-day 

training session, often the first and last 

days were used for installation and travel, 

leaving only one day for actual training. 

In some cases, trainers were not adequately 

qualified. They were either 

installers or just a person sent to fulfill a 

requirement. One trainer had not even 

bothered to look through the manual 

during his trip to the facility. After turning 

on the equipment, the display’s 

graphics user interface challenged the 

trainer’s understanding of the equipment. 

Many companies combined training 

and installation into one trip. If the 

install overran its allotted time, the 

training suffered greatly. Stipulating 

install and training as separate blocks of 

time in the buy-off agreement is a good 

way to guarantee fair treatment by the 

manufacturer. 

This will force the company to allow 

enough time to complete a thorough 

install. Two-thirds of the suppliers provided 

training time as agreed on. 

Only slightly more than half of the 

training experiences proved to be adequate. 

Either enough time was not assigned for 

the training, installation problems reduced 

the time available for training, or the 

trainer really was an installer assigned 

the additional chore of training. 

Many trainers continued without taking 

the trainees along step-by-step. One 

trainer did not hesitate to discourage 

questions emphatically. In extreme cases 

we sent a written evaluation and complaint 

to the supplier. 

Training met expectations in most 

cases when there was enough time for 

the trainees to use the machine in the

presence of the trainer and show the 

ability to execute various functions 

without trainer intervention. 

Post-Installation 

A quality-tested piece of equipment 

should be functional after appropriate 

installation. We looked at whether the 

equipment functioned as specified after 

its installation. What was the quality of 

support after installation and what was 

operational stability of the equipment 

after installation? 

Some of the electronic processing 

equipment is inherently quite complex 

due to sophisticated processes it implements 

and carries out. But when we 

compared a number of pieces which are 

similar in complexity, we find that while 

many are easy to use, some are difficult 

to use and some require quite a bit of 

effort in learning all the functions. 

On further investigation, we found that 

during initial training, GUI (graphical 

user interface) and the accompanying 

manuals play an important role in 

determining the learning curve. 

In one training session, the trainees 

found a GUI quite involved and suggested 

improvements to the supplier to 

make the set-up task easier. The trainer 

did not even take any notes of the suggestions 

or clarify why they would not 

adjust the GUI. 

We offered our services to another 

supplier to help identify spelling and 

grammatical oversights in their manuals. 

We did not get any response from 

them. While most manuals are written 

professionally, many foreign suppliers 

rely on internal sources that use idioms 

and expressions common in their culture, 

but ignore the need to make them 

friendly to Western users. 

Our data show that one-third of the 

suppliers could not support the equipment 

adequately after its installation. 

We were bombarded with insistent 

phone calls from suppliers or their representatives 

before purchase, but the 

phones died after the purchase! 

The suppliers who followed up after 

initial purchase were sometimes able to 

get additional orders as our needs 

expanded. The response quality declined 

significantly after the purchase. 

Software Issues 

Equipment is expected to function flawlessly 

after initial install, and mostly it 

did, except for 9% of the cases. 

In one case, there were software issues. 

The program refused to load consistently 

on start-up. It was a new version for the 

trainer, who had to communicate offshore 

everyday and had to take three “installation” 

trips before all the idiosyncrasies 

were straightened out. 

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Figure 7. Center staffer performs wirebonding on a Kulicke & Soffa 

8028 wire bonder. 

If a breakdown occurs, a part may 

only be available from the manufacturer. 

Keeping track of alternate distributors 

or similar parts that are just as good can 

help in times of need. 

An example was a machine that used 

220 volt non-U.S.-styled light bulbs. 

The manufacturer was charging almost 

two hundred dollars for two replacement 

bulbs. With the replacement identified 

onshore in advance, new bulbs could be 

ordered as needed. 

Some machines were allowed to connect 

to the internet so factory technicians 

could make repairs on-line. It was a great 

advantage in most cases, but we needed 

to guard against a virus in another case. 

We found it a good practice to make 

sure to back up all operating systems 

and hard drives on a regular basis. If a 

machine fails or there is a power failure, 

the day of programming or processing 

can be lost. Uninterruptible power supplies 

are a very good investment. 

Safety Mechanisms/Code Requirements 

In some instances we found used or 

surplus equipment lacking, especially 

when it came to safety mechanisms or 

code requirements. Some surplus 

equipment companies do not stand 

behind their products and or do not 

take any responsibility for used equipment 

after the sale. Some equipment 

companies refused to provide service or 

support due to the fact the equipment 

was purchased or sold 

through a third party. 

Operation is also dependant 

on the track record of 

the machine. Is it a new 

model or has it been in the 

industry for a long time? 

We looked through 

trade magazines, called 

other users, and sometimes 

traveled to the supplier to get 

an idea of the machine and 

its parent company. We 

tried to identify the 

strengths and weaknesses of the operation 

of the equipment. We also tried to 

learn what the projected life of the 

machine was and how difficult it was to 

obtain parts and service. 

Conclusion 

Hopefully, this article and similar data 

and publications will shed enough light 

on the challegnes of facility setup to 

allow others to learn from mistakes and 

triumphs. 

The establishment of a quality facility 

and proper equipment procurement, 

again, is dependant on a good buy-off 

agreement and procedure. Thorough 

planning and a clear, strong definition 

of facility purpose, are the keys to establishing 

such a facility. 

The data presented in this article may 

also be used by the suppliers of equipment 

to improve and streamline their 

services to meet the expectations of this 

worldwide industry. i 

Mr. Haring is a 

research technician at 

the Center. He earned 

a bachelor’s degree in 

archeology from 

Moorhead State 

University in 

Minnesota and earlier 

worked for the federal government. He 

later returned to college to study for an 

engineering degree while working for 

North Dakota State University’s 

Industrial Engineering Dept. 

[fred.haring@ndsu.edu] 

Mr. Scholz is a 

research engineer at 

the Center. After 

completing an engineering 

degree in 

machine design and 

development in 

Germany, he transferred 

to Krieger Corp. in the United 

States. He earned a master’s degree in 

mechanical engineering from South 

Dakota State University. Mr. Scholz has 

been at the Center for nearly 5 years and 

is lead engineer for the transfer of Alien 

Technology’s fluidic self-assembly manufacturing 

process. 

[bernd.scholz@ndsu.edu] 

Mr. Ahmad is the 

Center’s manager of 

engineering services. 

He received a master’s 

degree in experimental 

physics from 

Islamabad University, 

India. After graduation, 

he taught math and science in secondary 

schools in Ghana. He later worked at Intel 

Corp., where he contributed to quality and 

the reliability enhancement of assembly 

processes. His lengthy experience in the 

electronics industry includes positions at 

National Semiconductor, GigaBit/ 

TriQuint and Micron Technology. He also 

holds more than 50 patents. 

[syed.ahmad@ndsu.edu] 

Mr. Reinholz is the 

associate director for 

electronics technology 

at the Center. He 

received a bachelor’s 

degree in electrical 

engineering from 

NDSU, and was 

employed by Rockwell Collins in Cedar 

Rapids, Iowa, for 13 years prior to joining 

NDSU. [aaron.reinholz@ndsu.edu] 

98 



— A D V E R T I S E M E N T — 

SHOWCASE 

Continued from page 9 >> 

Share of MEMS Revenues by Device, 2002 vs. 2007 

Applications 2002 Revenues 2007 Revenues 

Microfluidics 36% 27% 

Optical MEMS (MOEMS) 18% 22% 

Inertial Sensors 21% 22% 

Pressure Sensors 14% 11% 

Other Sensors 7% 10% 

Other Actuators 3% 5% 

RF MEMS 1% 3% 

Source: In-Stat/MDR in Scottsdale, Ariz. [instat.com] 

tiny mechanical devices for inputs and outputs to the real world. 

Soon MEMS and MEMS-like nanotubes will provide conduits 

for power and I/O commands—a strange but welcome 

phenomenon. Although work has been done on such innovations 

in the past, most has been R&D or prototypical in nature. 

Now, faster, cheaper and more functional productions are 

moving from concepts to products quickly. 

What’s Hot and What’s Not? 

A quick look at the table suggests that microfluidics and 

pressure sensors have lost some market revenue, but that is 

misleading. 

The entire MEMS pie has been growing very quickly and 

microfluidics and pressure sensors are high volume devices 

with economies of scale driving prices down. 

Price Drop 

In a May 2007 analysis from Frost & Sullivan, a market research 

firm in Palo Alto, Calif., Sara Villarruel reports that motion 

detection sensors (MEMS inertial sensors) play a significant 

role in emerging applications such as inertial sensors in the 

High capability, small-volume packaging solutions are necessary for microsystems 

(Sandia National Laboratories) 


 

CALENDAR 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JULY 

SEMICON West 16-20 (Conference), 17-19 (Exhibits), 

Moscone Center, San Francisco [semi.org] 

SEPTEMBER 

5-7 Wafer-Level Packaging Symposium, 

Presented by SEMITOOL, Whitefish, Montana [semitool.com] 

9-12 KGD Packaging & Test Workshop, 

Embassy Suites, Napa, Calif. [dieproducts.org] 

12-14 SEMICON Taiwan Taipei, Taiwan [semi.org] 

17-19 Fourth Annual International Wafer-Level Packaging 

Conference, San Jose. Workshops scheduled for Sep. 17, with 

exhibits, panels and presentations scheduled for Sep. 18-19. 

[smta.org/iwlpc/] 




two most promising markets: automotive 

and consumer electronic industries. 

[frost.com] 

Automobiles can crash and electronics 

are dropped, so sensors are used to 

minimize damage. 

Tough To Build, Package 

MEMS usually require more complex 

fabrication than ICs, although many 

MEMS device are fabricated and packaged 

with semiconductor-originated 

technologies. 

MEMS technology successfully 

bridges the gap between electronics and 

mechanical systems to provide unique 

properties in a small package at a considerably 

lower cost. 

MEMS inertial sensors have emerged 

as one of the leading areas in MEMS 

development, with numerous applications 

opening up, especially in the consumer 

electronics industry. 

The packaging of MEMS, by the way, 

moved wafer bonding into the mainstream 

over a decade ago. 

F&S research analyst Prithvi Raj says, 

“Due to their small size and reliability, 

MEMS accelerometers have entirely 

replaced traditional crash sensor arrays 

in the automotive industry. The steady 

adoption of MEMS inertial sensors is 

causing a significant reduction in unit 

costs, which in turn has further opened 

up the market to these sensors.” 

Sensor Evolution 

MEMS inertial sensors have evolved 

considerably from expensive devices that 

were highly complicated to design and 

A integrated MEMS device with electronics and 

three-axis accelerometer was fabricated in the 

Sandia MEMS First process (Sandia Microsystems 

Science, Technology & Components) 

fabricate to the current, low-cost, massproduced 

and highly efficient sensors. 

Though relatively newer, MEMS gyroscopes 

show tremendous promise. While 

these devices are more complicated— 

compared to a typical accelerometer— 


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100 




He calls this a “Technology Detective and 

Problem Solving” book (in capital letters!) 

Ken says the 157-page book contains 

101 case histories from around the 

world. “All are true! Most mysteries 

have been solved, but a few are left for 

the reader. The detectives and forensic 

investigators” include scientists, engineers, 

technicians and factory workers.” 

He even includes a final chapter for 

would-be sleuths, entitled, “How to Be a 

Super Sleuth.” This is included, he says, as 

a guide to industrial problem solving. 

This is the first book in a possible 

trilogy. If you have your own industrial 

mystery (solved or unsolved), you can 

upload it for possible future publication 

at his web site. 

My suggestion is that you download 

it now, [et-trends.com] before Ken gets 

wise and starts charging for the privilege! 

Is There a Scion in the House? 

It seems that news travels slowly from 

Bilthoven, the Netherlands. More than 

two months after the fact, ASM International 

[asm.com] announced that 

Arthur del Prado, CEO and founder is 

retiring. 

He will be replaced by Chuck del Prado, 

his son. Chuck has been president and 

GM of ASM America since 2001. 

While most of ASMI’s products are 

geared to the front-end—epi reactors, 

CVD/PECVD furnaces, RTP tools—the 

company also owns 54 percent of ASM 

Pacific [asmpt.com] in Hong Kong. 

ASMP is the largest provider (ASMP 

says) of copper wire bonders and die 

attach equipment. 

The elder del Prado founded the company 

in 1968, and grew it into a business 

power to be reckoned with. 

ASMI’s net 2006 sales topped a billion 

dollars with a record e877.5 million 

($1.178 billion), up from 2005’s e724.7 

million ($971.9 million). 

The company has been publicly traded 

in the Netherlands and on the NASDAQ 

for many years. We don’t recall any 

other case where the scion replaced the 

father at the helm of 

a large, public technology 

company. 

Even with the 

smaller companies 

in electronics, it’s 

not a common 

event. We can only 

Lonny Plummer think of two: the 

defunct KRAS and 

Liberty Electronics. 

Before his retirement, Larry Plummer 

was the president and CEO of KRAS, a 

name constructed from the last-name 

initials of the former owners, not Larry’s. 

KRAS, headquartered in 

Pennsylvania, was a maker of trim/form 

equipment. Two of its key employees 

were Larry’s son Lonny, now an executive 

with Kinesys Software [kinesyssoftware.com], 

and Larry’s daughter 

Melissa. She left the industry years ago 

to become a wife and mother. 

Larry today, Lonny says, has retired to 

Florida. 


Electronic Trends Continued from page 14 >> 

amplifiers, ASICs, DRAMs, Flash memory 

and voltage regulators. WLPs are also 

used for discrete and passive devices, as 

well as MEMS. 

End products include automobiles, cell 

phones, DRAM modules, PDAs, watches 

and almost every handheld electronic device. 

A couple of new twists are occurring 

with WLPs: The first is to create a WLP 

with a larger standard size. This involves 

transferring the cut dice to another wafer 

frame—which puts space between the 

die—with a filler between each. 

This creates another solid wafer on 

which to build the package interconnects. 

A fanout redistribution layer is created 

over the face of the die and the filler material. 

This allows a larger number of I/Os 

and creates a standard-sized package 

while maintaining the benefits of waferlevel 

processing. 

One example of this approach is 

Freescale Semiconductor’s [freescale.com] 

proprietary redistributed chip packaging 

(RCP), which is expected to be in production 

in 2008. Applications include 

PowerQuicc microprocessors, DSPs, 

power amplifiers and many others. 

Another example is from Infineon 

Technologies [infineon.com], Nitto 

Denko, and Apic Yamada Corp., which 

have jointly invented a molded, reconfigured 

WLP. 

Another twist to WLP technology is 

stacking these small packages. 

Micron Semiconductor Asia [micron. 

com] and Samsung Electronics [samsung. 

com] have both announced plans for 

Units (M) 

12000 

10000 

8000 

6000 

4000 

2000 

0 

2006 2007 2008 

WLPs Growing Rapidly 

2009 2010 2011 

using through-silicon vias to vertically 

connect DRAMs packaged in WLPs. 

Vias are created in the die and filled 

with copper to allow for electrical interconnection 

of the top die to a lower 

interposer. 

The die must be backside-thinned to 

remove the excess bulk silicon. This 

negates the need for wire bonds on the 

outside perimeter, which leads to the 

fastest speed, with the least power consumption. 

i 




The Reinvention of Nick Sr. 

Nick Langston Sr. brought in two sons, 

Nick Jr. and Jason, for his company, 

Liberty Research, a small maker of test 

sockets, in Santa Clara. 

Liberty was first merged with DCI, 

another privately held socket company 

in Santa Clara. Then, Credence Systems 

bought DCI, making it part of the 

much larger test company. 

After a relatively brief period, 

Credence found that having sockets on 

its roster maybe wasn’t the great idea 

the ATE maker thought and divested 

DCI in a management buyout. 

DCI went along for awhile on its own. 

In 2006, it was acquired by the company 

that is now Antares Advanced Test 

Technologies, which also includes the 

former Wells-CTI socket company, DB 

Design and Antares. 

By the way, when it comes to mergers 

and acquisitions, tracing the lineage of the 

socket vendors can be an exhausting task. 

Antares is the interface and socket provider 

created from Kulicke & Soffa’s former 

package test and wafer-test subsidiary. 

K&S, like Credence, also decided it 

needed to sell sockets and acquired 

Probe Technology of Santa Clara, Calif., 

and Cerprobe of Gilbert, Ariz., in 2000. 

But by 2006, selling sockets and wire 

bonders didn’t seem like such a good 

idea and for the struggling K&S, the sale 

was literally money in the bank. 

The Wages of Summer 

A father’s company can also be a great 

proving ground for the future. Martin 

Hart, president of TopLine, Garden 

Grove, and the new startup Mirror 

Semiconductor, will bring daughter 

Karen, 20, in for summer training. 

Marty says she’ll work in accounting, 

operations, telemarketing and “whatever 

needs to be done.” She’ll also go to 

TopLine’s Atlanta office for a week’s 

training. 

The PR guys and gals are often their 

company’s unsung heroes. One of the 

best is Jeff Luth, who recently left 

Amkor to set up his own shop in the 

Phoenix area. You 

can reach him at 

jeffluth@cox.net. 

Software Radio 

Editors, having the 

recurring need to fill 

pages constantly, 

Jeff Luth Continued on page 103 >> 

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102 




the capabilities of these devices justify 

their marginally higher cost. 

Lower Manufacturing Costs 

Although producing a MEMS sensor 

requires minimal costs, the costs 

involved in setting up a MEMS foundry 

remain high. This is a major challenge 

for newer and smaller companies entering 

the MEMS arena, but MEMS 

foundries can ease the burden. 

“Another related issue plaguing the set 

up of MEMS foundries is the ‘one device, 

one fabrication flow’ approach,” explains 

Raj. “This means that each type of MEMS 

device requires a specialized fabrication 

approach, and thus puts limits on the 

capabilities of smaller firms to expand 

their MEMS-based products.” 

Sandia National Laboratories, 

Albuquerque, N.M., designs, develops, 

builds and delivers highly sensitive, reliable 

micro and nano-scale optical devices 

and systems across electromechanical 

and biological domains for physical 

sensing and optical signal processing in 

national security applications. 

They are pioneers in MEMS technology, 

and a visit to their web site is certainly 

worthwhile. [sandia.gov] 

Sandia uses microfabrication techniques 

to create novel approaches and 

methodologies for micro- and nano-scale 

optical sensing and control. 

These approaches with proven optoelectro-mechanical 

techniques push 

performance limits in displacement and 

acceleration sensing, optical wavefront 

control and beam shaping. These capabilities 

at the system level permit high 

performance, reliable integrated systems. 

The Near Future 

Nearly all major categories of MEMS 

have seen, or may soon see, applications 

in consumer products, reports In-Stat. 

As a result, the worldwide MEMS 

market in consumer electronics will 

grow from US$727 million in 2006 to 

over US$1 billion by 2009. 

MEMS will expand to a broad array 

of consumer applications including game 

consoles, portable consumer electronics 

devices (such as digital camcorders), and 

GPS devices. 

“In the longer term, MEMS memory, 

A vibratory gyroscope fabricated in Sandia MEMS 

first process which enables MEMS and electronics 

to be fabricated on the same die (Sandia Microsystems 

Science, Technology & Components) 

MEMS fuel cells, and other types of MEMS 

devices could also join the list,” says 

Steve Cullen, an In-Stat analyst. 

“However, these technologies are 

expected to initially find usage in other 

product areas that are less cost sensitive, 

with application in consumer electronics 

products unlikely until after 2010.” 

An Electronics-Centric World 

No matter how sophisticated the MEMS 

device may be, it still must interface 

with the global electronics systems. 

Are those friendly little MEMS 

devices destined for greater integration 

with our established ICs? Absolutely! i 

Assembly Lines Continued from page 102 >> 

receive a lot of what are euphemistically 

termed “news releases.” Much of those 

are subsequently known as junk mail, 

spam—and worse. 

My guess is that no more than 20 

percent of the “news releases” I receive 

have anything to do with semiconductor 

packaging or test. Still, many of them 

are interesting. 

And just when I thought communications 

couldn’t get any more technologically 

complex, I learn about “software 

radio” from a news release. 

A German company, TechnoConcepts 

[technoconcepts.com], says it’s been 

successful in “implementing its advanced 

reconfigurable radio for 

high-volume commercial 

markets.” 

What is software radio, and 

why should we care about it? 

According to a web site 

[comsec.com/softwareradio.html] 

this is the “art 

and science of building radios 

using software.” There is still 

some RF hardware needed, 

but, says the site, “the idea is to 

get the software as close to the antenna 

as feasible.” 

It seems the concept of software radio 

has been around for a while—I just 

This set was created long before software radio. 

missed it. It will be interesting to see if 

this is the next iPod. i 

Answer: Trees: Cedar, Oak, Pine and Redwood. 


INDUSTRY NEWS 

SEMI Says Q1 Billings for Equipment Reached $10.75 Billion 

San Jose—Worldwide semiconductor manufacturing equipment 

billings reached $10.75 billion in Q1 of this year, according to trade 

organization SEMI [semi.org]. 

That figure is four percent higher than Q4-2006 and about 12 percent 

higher than the Q1-2006. 

SEMI also reported worldwide semiconductor equipment bookings 

of $10.50 billion for Q1-2007, six percent higher than the same quarter 

of 2006, but five percent below the bookings for Q4-2006. 

Stanley T. Myers, SEMI president and CEO is quoted in a news 

release saying, “Billings for the first quarter of 2007 posted slight gains 

over the fourth quarter of 2006, with Korea shwoing particularly 

robust growth. “Year-over-year sales 

were largely mixed, with China, Korea 

and Taiwan posting solid double-digit 

growth numbers.” 

SEMI gathers its data (see table) in 

cooperation with the Semiconductor 

Equipment Association of Japan, from 

more than 150 companies that provide 

information. 

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ADVERTISER INDEX 

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Controlled Semiconductor Inc. consemi.com . . 26 

Corwil corwil.com . . . . . . . . . . . . . . . . . . 38, 39 

Datacon datacon.at . . . . . . . . . . . . . . . . . . . . 35 

Design 2 Market design2marketinc.com . . . . . . 90 

Deweyl Tool Company Inc. deweyl.com . . . . . . 79 

Disco disco.co.jp . . . . . . . . . . . . . . . . . . . . . . 68 

DL Technology dltechnology.com . . . . . . . . . . . 17 


electronictrendpubs.com . . . . . . . . . . . . . . . . 90 

E-tec Interconnect Ltd. e-tec.com . . . . . . . . . . 81 

EV Group evgroup.com . . . . . . . . . . . Back Cover 

Exatron exatron.com . . . . . . . . . . . . . . . . . . . 81 

F&K Delvotec fkdelvotec.com . . . . . . . . . . . . . 51 

HCD hcdcorp.com . . . . . . . . . . . . . . . . . . . . . 18 

HDI Solutions hdi-s.com . . . . . . . . . . . . . . . . 83 

Henkel electronics.henkel.com . . . . . . . . . . . . 56 

Heraeus 4cmd.com . . . . . . . . . . . . . . . . . . . . 65 

Hesse & Knipps hesse-knipps.com . . . . . . . . . . 32 

Honeywell honeywell.com . . . . . . . . . . . . . . . . 14 

Indium Corp. of America 

indium.com . . . . . . . . . . . . . . Inside Front Cover 

International Micro Industries imi-corp.com . . . 44 

Inovys Corp. inovys.com . . . . . . . . . . . . . . . . 33 

Ironwood Electronics ironwoodelectronics.com . . . 81 

IWLPC smta.org/iwlpc . . . . . . . . . . . . . . . . . . 86 

JCET cj-elec.com . . . . . . . . . . . . . . . . . . . . . . 12 

Keteca keteca.com . . . . . . . . . . . . . . . . . . . 100 

KGD Workshop napakgd.com . . . . . . . . . . . . . 93 

Kinesys kinesyssoftware.com . . . . . . . . . . . . . 63 

KYEC kyec.com.tw . . . . . . . . . . . . . . . . . . . . . 48 

Lintec lintec-usa.com . . . . . . . . . . . . . . . . . . . 79 

Loranger loranger.com . . . . . . . . . . . . . . . . . . 99 

MAT Ltd. mat-ltd.com . . . . . . . . . . . . . . . . . . 90 

Machine Vision Products 

machinevisionproducts.com . . . . . . . . . . . . . . 20 

Microminiature Technology Inc. 

microminiature.com . . . . . . . . . . . . . . . . . . . 72 

Billings 1Q07/4Q06 1Q07/1Q06 

by Region 1Q 2007 4Q 2006 1Q 2006 (Q-o-Q) (Y-o-Y) 

Europe 0.78 0.86 0.92 -10% -16% 

China 0.65 0.50 0.38 31% 71% 

Japan 2.27 2.29 2.33 -1% -3% 

N. America 1.79 1.92 1.80 -7% 0% 

Taiwan 2.01 2.10 1.59 -4% 26% 

ROW 0.79 0.89 0.79 -12% 0% 

Total 10.75 10.34 9.58 4% 12% 

(Source: SEMI) 

Mintz Levin mintz.com . . . . . . . . . . . . . . . . . . 45 

Mirae mirae.com . . . . . . . . . . . . . 23, 25, 27, 29 

Mitsubishi Materials Corp. mmus.com . . . . . . 79 

Mühlbauer muehlbauer.de . . . . . . . . . . . . . . . 28 

Namics namics.co.jp . . . . . . . . . . . . . . . . . . . 81 

NEPCON nepconchina.com . . . . . . . . . . . . . . . 88 

NEPES nepes.com.sg . . . . . . . . . . . . . . . . . . . 24 

North Dakota State University ndsu.edu . . . . . . 90 

Oerlikon Assembly Equipment oerlikon.com . . . 58 

Pac Tech USA pactech-usa.com . . . . . . . . . . . . 96 

Panasonic Factory Automation 

panasoniccfa.com/lab3/ . . . . . . . . . . . . . . . . . . 5 

Paricon paricon-tech.com . . . . . . . . . . . . . . . . 93 

Piper Plastics Inc. piperplastics.com . . . . . 34, 53 

Plasma Etch plasmaetch.com . . . . . . . . . . . . . 91 

Precision Contacts precisioncontacts.com . . . . 13 

Premier Semiconductor premiers2.com . . . . . . 97 

Profab Technology profabtechnology.com . . . . . 79 

Qualmax qualmaxamerica.com . . . . . . . . . . . . 84 

Robson Technologies Inc. testfixtures.com . . . . . 3 

Rohm and Haas rohmhaas.com . . . . . . . . . . . . 2 

Royce Instruments royceinstruments.com . . . . . 89 

RS Tech rstechinc.com . . . . . . . . . . . . . . . . . . 30 

Senju Comtek senjucomtek.com . . . . . . . . . . . 22 

Sensata Technologies sensata.com . . . . . . . . . 77 

Sensor Products sensorprod.com/samples . . . . 81 

SER USA serusa.com . . . . . . . . . . . . . . . . . . 102 

Sikama sikama.com . . . . . . . . . . . . . . . . . . . 46 

SSEC ssecusa.com . . . . . . . . . . . . . . . . . 10, 11 

SolVision solvision.net . . . . . . . . . . . . . . . . . . 19 

Sonoscan sonoscan.com . . . . . . . . . . . . . . . . 60 

Surface Technology Systems stsystems.com . . 52 

SUSS MicroTec suss.com . . . . . . . . . . . . . . . 54 

Synergetix synergetix.com . . . . . . . . . . . . . . . 16 

Tamarack Scientific Inc. tamsci.com . . . . . . . . 92 

Tessera Technologies tessera.com . . . . . . . . . 64 

Test Tooling Solutions Group tts-grp.com . . . . . 21 

Umicore microbond.eu . . . . . . . . . . . . . . . . . . 6 

Westbond westbond.com . . . . . . . . . . . . . . . . 81 

WinWay Technology winway.com.tw . . . . . . . . . 9 

Xsil xsil.com . . . . . . . . . . . . . . . . . . . . . . . . 99 

Yamaichi Electronics USA yeu.com . . . . . . . . . 82 

Carl Zeiss SMT smt.zeiss.com . . . . . . . . . . . . 62 

This index is provided as a service to advertisers and readers. Chip Scale Review 

does not assume any liability for errors or omissions in the listings. 

104 


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Chip Scale Review - July 2007

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