Energy harvesting: a thin film approach - EE Times Europe

CCD and CMOS features. They facilitate, however, the mitigation
of each technology’s limitations as illustrated in the following
sections.
A true merge of CCD and CMOS
A major advantage of epc’s BSI concept is the optical detectors’
100% fill factor, independent of the numbers of transistors
in the pixel. Looking at the common requirement of global
shuttering, these advantages become evident. CMOS requires
additional transistors in each pixel in order to realize global
shuttering. This usually comes at a loss in fill factor with adverse
effects on device responsivity. In the Espros Photonic CMOS
process, shuttering is completely implemented in the charge
domain and can be controlled in very short timeframes. What’s
more, repetitive shuttering with frame-store functionality in dedicated
frame buffers is also possible. However, the full CMOS
analogue design features including high voltage transistors and
EEPROM blocks remain available for the pixel architecture – all
of which come with no compromise in the fill factor. Responsivity
also benefits from the availability of low power high gain
CMOS amplifiers. And the previously mentioned quantum
efficiency advantage plays a vital supporting role in this respect
by providing higher charges in the first place.
Dealing with noise
When dealing with noise performance, the most suitable design
measures from both worlds can be applied in a complementary
way. Traditionally, CMOS used to be much more prone to noise,
not in the least due to restrictions resulting from limited real
estate inside the pixel. Source follower geometries are limited
by size and complex architectures such as multiple read out
stages compromise the requirement to keep noise levels low.
Although, one has to admit that with recent developments in
CMOS process technology, the differences are dwindling. In
a mixed-process environment, the design engineer can apply
CCD pixel designs with all the noise advantages. In-pixel source
followers do not suffer size restrictions due to BSI and CMOS
readout and amplification stages can be deployed where they
deliver the best performance (e.g. in high gain amplifiers). As a
consequence, the dynamic range will benefit from the ability to
Fig. 3: Pulse response following a 10ns LED pulse with a rise/
fall time of 12ns.
accumulate and handle large charge amounts and the degree of
freedom in pixel design supports the implementation of dedicated
high dynamic range architectures.
Speed
Speed is another requirement often stressed in imaging. A
closer differentiation is appropriate in order to reveal the benefits
on speed. First, speed is determined by an efficient photon
conversion and the subsequent charge collection mechanisms.
These mechanisms are limited by diffusion and by drift velocities
related to the levels of the applied depletion voltage. Higher
depletion voltages generate stronger fields and result in faster
drifts and therefore in faster charge separation and detection.
In the Espros Photonic CMOS environment, a combination of
suitable substrate material and high field charge handling lead
to reaction times in the nanosecond range – see figure 3.
Moving one step further and looking at the speed delivered
by the imager as an entity, we are back to the significant advantages
of CMOS in designing ultra-fast and highly sophisticated
system on chip solutions.
New opportunities and incremental
improvements
The above sections illustrate only an arbitrary choice of examples
of how the combination of CCD and CMOS process
technologies support better performing optical silicon detectors.
In fact, virtually all known trade-offs that used to exist when
considering one particular technology are now obsolete. The in-
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