Energy harvesting: a thin film approach - EE Times Europe

Figure 1 shows the typical power consumption for the latest
ultra-low power A/D converter from Analog Devices for various
throughput rates. Also shown is a comparison of how utilisation
of the power down mode of the device can provide additional
power savings especially with lower throughput rates. The
AD7091R has an on-chip reference and therefore the throughput
rate and utilisation of the power-down mode is determined
by the reference recharge time. Figure 1 also shows the typical
power consumption if an external reference is used. When an
external reference is used the reference recharge time does not
apply, just the time to turn the ADC circuitry that was powered
down back on. Therefore the throughput rate where the power
down mode can be used is greatly increased with an external
reference.
The most common methods for initiating conversion requests
in A/D converters are via a dedicated conversion input pin or
controlled th--rough the serial interface. With a dedicated input
pin a conversion is initiated by a falling edge of a convert start
pin. The conversion is then controlled by an on-chip oscillator
and the result can be read back via the serial interface once the
conversion is complete. Therefore the conversion is always run
at an optimum constant speed allowing the device to enter low
power mode the moment a conversion is complete thus saving
power.
With A/D converters where the sampling instant is initiated
by a /CS falling edge the conversion is controlled by the SCLK
signal. The SCLK frequency will affect the conversion time,
throughput rate achievable and therefore the power consumption.
The faster the SCLK time the faster the conversion time.
Shorter conversion times mean the proportion of the time the
device is in low power mode compared to normal mode increases
and therefore significant power savings can be made.
The power for a complete system is therefore the sum of
each load capacitance by its switching frequency multiplied by
the drive voltage.
Where:
P L
= Power to charge capacitive load
C L
= Capacitive load
V DRIVE
= Drive voltage
f = Frequency of change
As the A/D converter drives the SDO pin and the host microcontroller
drives the /CS, /CONVST and SCLK the lowest power
consumption in both devices will be achieved by having a low
pin capacitance in each device.
For the /CS and /CONVST pins the switching frequency is
determined solely by the throughput rate. The SCLK frequency
as already discussed should be set to the maximum allowable
frequency to reduce power. This is not a contradiction as the
important point is that the SCLK should not be free running
and should only be active for the minimum possible time to
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Where:
t conv
= Time spent converting
N = Number of SCLK cycles to complete conversion
f SCLK
= SCLK Frequency (Hz)
Assuming 16 SCLK cycles to complete a conversion and result
read, a system sampling at 100 kSPS with a 30 MHz SCLK
will spend 5.33% of the time converting (53.3 ms per second).
The same system operating with a 10 MHz SCLK will spend
160 ms converting. Therefore to achieve the optimum power
consumption the converter should be operated at the highest
allowable SCLK frequency.
An important parameter when designing for low power that
can often be overlooked is the capacitive load seen at the
outputs pins. The pins most affected are the communication
interface pins, such as the SCLK, /CS and SDO, as these I/O
are constantly changing state during the conversion process.
The capacitive load seen at an output is the pin capacitance of
the driver IC itself, the pin capacitance of the input pin plus the
PCB trace capacitance.
The trace capacitance should generally be small, in the
femtofarad range, and is not significant. The power required to
charge a capacitive load is a function of the load, the drive voltage
and the frequency of change and is defined by the following
equation.
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www.electronics-eetimes.com Electronic Engineering Times Europe September 2012 37