QDK-nano PIC24/dsPIC-C30 - Quantum Leaps

QDK-nano
PIC24/dsPIC-C30
www.state-machine.com/pic
QP-nano will use uint16_t. If you don’t define this macro in qpn_port.h, the default of 0 (no
parameter) will be assumed.
(3) The macro QF_TIMEEVT_CTR_SIZE defines the size (in bytes) of the time event down-counter. The
allowed values are 0 (no time events), 1, 2, or 4 bytes. Here the value of QF_TIMEEVT_CTR_SIZE is
set to 2, so that QP-nano will use uint16_t. If you don’t define this macro in qpn_port.h, the
default of 0 (no time events) will be assumed.
(4) You must define the QF_MAX_ACTIVE macro as the exact number of active objects used in the
application. The provided value must be between 1 and 8 and must be consistent with the definition
of the QF_active[] array in main.c.
(5) The interrupt locking macro resolves to the single instruction DISI #0x3FFF, which disables
interrupts for 16383 instruction cycles. The number of cycles is much longer than any actual critical
section in QP-nano.
NOTE: The DISI instruction only disables interrupts with priority levels 1-6. Priority level 7 interrupts
and all trap events still have the ability to interrupt the CPU when the DISI instruction is active. This
means that from the perspective of QP, the level 7 interrupts are treated as non-maskable interrupts
(NMIs). Such non-maskable interrupts cannot call any QP services. In particular, they cannot post
events (see also Section 5).
(6) The DISI #0 instruction is then used to unconditionally unlock the interrupts at the end of the critical
section.
(7) The interrupt nesting is allowed, as it is the default for PIC24/dsPIC.
(8) The C99-standard exact-width integer types are defined explicitly, because the MPLAB C30
compiler does not provide the standard header file.
(9) The qpn_port.h must include the QEP-nano event processor interface qepn.h.
(10) The qpn_port.h must include the QF-nano real-time framework interface qfn.h.
3.2 ISRs in the Non-Preemptive “Vanilla” Configuration
The MPLAB C30 compiler supports writing interrupts in C. In the non-preemptive “vanilla” port, the ISRs
are identical as in the simplest of all “superloop” (main+ISRs), and there is nothing QP-nano-specific in
the structure of the ISRs. The only QP-specific requirement is that you provide a periodic system clock
tick ISR and you invoke QF_tick() in it. The ISRs are located in the bsp.c file found in the application
directory.
NOTE: The non-preemptive “vanilla” kernel allows interrupts nesting, as the interrupt preemptions
are handled entirely by the PIC24/dsPIC hardware.
Listing 3: The system tick interrupt calling QF_tick() function to manage armed time events.
(1) void __attribute__((__interrupt__,
(2) auto_psv))
(3) _T2Interrupt(void)
{
(4) _T2IF = 0; /* clear Timer 2 interrupt flag */
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