QDK-nano PIC24/dsPIC-C30 - Quantum Leaps

QDK-nano
PIC24/dsPIC-C30
www.state-machine.com/pic
Figure 3: Architecture of the PIC24/dsPIC port
(IPL = 7) Non-Maskable Interrupt (NMI)
IPL Level 7
(NMI level)
(IPL = 6) User interrupt
(IPL = 5) User interrupt
(IPL = 4) User interrupt
IPL Levels 1-6
(interrupt level)
(IPL = 3) User interrupt
(IPL = 2) User interrupt
(IPL = 1) User interrupt
(QP prio = n) User task (active object)
(QP prio = n-1) User task (active object)
. . .
(QP prio = 2) User task (active object)
IPL Level 0
(task level)
(QP prio = 1) User task (active object)
(QP prio = 0) Idle task
1.3 What’s Included in the QDK-nano-PIC24-dsPIC?
This QDK provides a basic Board Support Package (BSP) for PIC24 and dsPIC MCUs and two versions
of the PEdestrian LIght CONtroller (PELICAN) crossing example for each processor. The PELICAN
application is described in Chapter 12 of [PSiCC2] as well as in the Application Note “PEdestrian LIght
CONtroller (PELICAN) Crossing” [QL AN-PELICAN 08] (included in the QDK-nano distribution):
The PELICAN crossing example with the cooperative “vanilla” kernel for PIC24FJ128GA010;
The PELICAN crossing example with the preemptive QK-nano kernel for PIC24FJ128GA010;
The PELICAN crossing example with the cooperative “vanilla” kernel for dsPIC33FJ256GP710; and
The PELICAN crossing example with the preemptive QK-nano kernel for dsPIC33FJ256GP710.
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