PCIE Validation Methodology

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• Introduction Agenda • PCIE Verification Challenges • PCIE Validation Methodology • PCIE Validations Example using IFV • IFV Recommendations • Summary 2
PCI Express PCI Express is a serial bus interface standard for the PC industry. It employs a layered protocol: • The PHY analog the analog macros dealing mainly with the SERDES (serialize /de-serialize), idle and common mode detections. • The PHY logic layer mainly consists of elastic storage, 8/10 bit decoders, and symbol alignment. • The Data Link (DL) layer contains framers, CRC detection and generation, DLP (Data Link Packet) decoding and generations. • The Transaction Layer (TL) takes care of the following tasks: 1. TLP (Transaction Layer Packet) formation and processing the different packet types. 2. Flow Control tracking. 3. Virtual Channel. 4. Transaction Handling. 3
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PCIE Validation Methodology

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