PCIE Validation Methodology

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PCIE Validation Methodology Structural Testing • No data or parameters are considered in this type of testing. The emphasis is on the control structure of the PCI Express protocol. The structural test can be achieved with the following requirements. • In any state, the layer under test (LUT) can accept and respond to all input symbols from all the vocabulary of PCI Express protocol pertaining to that particular layer. • When a status message is received, the LUT responds with an output message that uniquely identifies its current state without changing state. • When a reset message is received, the LUT responds by making a transition to a known initial state, independent of its current state. • When a set message is received in the initial system state, the LUT responds by transition to that state specified in the message. 8
PCIE Validation Methodology Assertion Based Verification • Due to the challenges, Assertion-Based verification becomes an enticing validation technique for the PCIE. • PSL or SVA are the most commonly used assertions languages. Static Verses Dynamic Validation • Static functional verification is not capable of testing a design alone. We use it in conjunction with dynamic simulation. • Trade off between capacity and completeness • Static verification is hampered by capacity constraints that limit application to small functional blocks of a device • Static methods yield a complete, comprehensive verification of the proven property, and are ideal for small, complex units such as arbiters and bus controllers etc. Hybrid Method • A semi-formal method combines static and dynamic techniques in order to overcome the capacity imposed by static method while addressing the inherent completeness limitations of dynamic methods. This is particularly useful on validation large state machines. 9
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