The IA-64 System Architecture - DIG64

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Hardware Accessed Page Table Processor Memory Region Registers RID RRx 63 61 60 <strong>64</strong>-bit Address Virtual Page # offset 0 Search Virtual Hashed Page Table (VHPT) Hash Flexible Hardware Mechanisms Enable Parallel Execution ®
Virtual Memory Model: Example Virtual Address Space . 2,3 3 1,2 1 P1,2,3,4 Region 7 - One RID, no key Kernel - protected by Priv. level . Region 2 - One RID, protection via multiple keys Shared memory areas Region 1 - Same RID if shared Single address space for code P1 P2P3 P4 Region 0 - Different RID in each process Unique address spaces for data Flexible Virtual Memory <strong>Architecture</strong> Enables Variety Of Efficient OS Implementations ®
Page 1 and 2: 7KH,$6\VWHP$UFKLWHFWXUH 7XWRULDO)RU
Page 3 and 4: IA-64 System Architecture Agenda l
Page 7 and 8: 64-bit Address Space: Large and Spa
Page 9 and 10: Process Address Space 63 64-bit Add
Page 11 and 12: IA-64 Region Registers 64-bit Addre
Page 13 and 14: Virtual Address Translation: TLB l
Page 15 and 16: Virtual Address Translation Region
Page 17: Variable Page Sizes l Minimum on al
Page 21 and 22: IA-64 Interruption Model l Parallel
Page 23 and 24: IA-64 Interruption Process Applicat
Page 25 and 26: IA-64 Interruption Process Applicat
Page 27 and 28: IA-64 Interruption Process IP Appli
Page 29 and 30: Interruption Features l Low interru
Page 31 and 32: IA-64 External Interrupts Processor
Page 33 and 34: IA-64 System Software Stack: OS Boo
Page 35 and 36: OS Calls To Firmware Services 2SHUD
Page 37 and 38: Architected RAS Features - Reliabil
Page 39 and 40: Parallelism and Scalability l Excel
Page 43 and 44: Call to Action l New detailed speci

The IA-64 System Architecture - DIG64

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