The IA-64 System Architecture - DIG64

More documents

Recommendations

Info

IA-64 Virtual Memory Model l Process Address Space l System Address Space Management l Virtual Address Translation –TLB and Page table l Flexible Object Sharing Model –Aliasing and Global addressing ®
64-bit Address Space: Large and Sparse l Requires increased TLB capacities – Mapped files, globally shared memory – Allow for multiple large on/off-chip TLBs – Provide wide range of page sizes l Improve utilization and sharing of TLB and page tables – No TLB flush on context switch – Promote TLB entry sharing IA-64 Overcomes Challenges Of 64-bit Address Space Efficiently ®
Page 1 and 2: 7KH,$6\VWHP$UFKLWHFWXUH 7XWRULDO)RU
Page 3 and 4: IA-64 System Architecture Agenda l
Page 5: IA-64 System Architecture Agenda l
Page 9 and 10: Process Address Space 63 64-bit Add
Page 11 and 12: IA-64 Region Registers 64-bit Addre
Page 13 and 14: Virtual Address Translation: TLB l
Page 15 and 16: Virtual Address Translation Region
Page 17 and 18: Variable Page Sizes l Minimum on al
Page 19 and 20: Virtual Memory Model: Example Virtu
Page 21 and 22: IA-64 Interruption Model l Parallel
Page 23 and 24: IA-64 Interruption Process Applicat
Page 25 and 26: IA-64 Interruption Process Applicat
Page 27 and 28: IA-64 Interruption Process IP Appli
Page 29 and 30: Interruption Features l Low interru
Page 31 and 32: IA-64 External Interrupts Processor
Page 33 and 34: IA-64 System Software Stack: OS Boo
Page 35 and 36: OS Calls To Firmware Services 2SHUD
Page 37 and 38: Architected RAS Features - Reliabil
Page 39 and 40: Parallelism and Scalability l Excel
Page 41 and 42: IA-64 System Architecture Agenda l
Page 43 and 44: Call to Action l New detailed speci

The IA-64 System Architecture - DIG64

Create successful ePaper yourself

Delete template?

Save as template?