The IA-64 System Architecture - DIG64

More documents

Recommendations

Info

IA-64 System Architecture Agenda l System Architecture Highlights l Virtual Memory Model l Interruption Model l System Software Stack l Reliability, Availability, Serviceability l Parallelism & Scalability l Compatibility l Summary / Call To Action ®
Parallelism and Scalability l Excellent Multi-Processing Scalability –High performance relaxed ordering model –Flexible semaphore primitives –Hardware broadcast TLB purge l OS Resource Scaling & Parallelism –Flexible # of PKRs, TRs, , key & RID widths –Parallel update of control register writes (explicitly serialized) IA-64 Features For Scalable MP Systems ®
Page 1 and 2: 7KH,$6\VWHP$UFKLWHFWXUH 7XWRULDO)RU
Page 3 and 4: IA-64 System Architecture Agenda l
Page 7 and 8: 64-bit Address Space: Large and Spa
Page 9 and 10: Process Address Space 63 64-bit Add
Page 11 and 12: IA-64 Region Registers 64-bit Addre
Page 13 and 14: Virtual Address Translation: TLB l
Page 15 and 16: Virtual Address Translation Region
Page 17 and 18: Variable Page Sizes l Minimum on al
Page 19 and 20: Virtual Memory Model: Example Virtu
Page 21 and 22: IA-64 Interruption Model l Parallel
Page 23 and 24: IA-64 Interruption Process Applicat
Page 25 and 26: IA-64 Interruption Process Applicat
Page 27 and 28: IA-64 Interruption Process IP Appli
Page 29 and 30: Interruption Features l Low interru
Page 31 and 32: IA-64 External Interrupts Processor
Page 33 and 34: IA-64 System Software Stack: OS Boo
Page 35 and 36: OS Calls To Firmware Services 2SHUD
Page 37: Architected RAS Features - Reliabil
Page 43 and 44: Call to Action l New detailed speci

The IA-64 System Architecture - DIG64

Create successful ePaper yourself

Delete template?

Save as template?