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An Introduction to the Ericsson Transport Network Architecture ...

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Fig. 4<br />

Control System <strong>Architecture</strong><br />

CP<br />

UP<br />

ICM<br />

SNC<br />

Central Processor<br />

Unit Processor<br />

Internal Communication <strong>Network</strong><br />

Switching <strong>Network</strong> Controller (only SDXC)<br />

Each unit in <strong>the</strong> system has a powerful microprocessor,<br />

and a central master computer<br />

co-ordinates all <strong>the</strong> unit processors<br />

and provides input/output.<br />

Unit processors enable <strong>the</strong> unit itself <strong>to</strong><br />

perform a large amount of processing and<br />

so reduce <strong>the</strong> load on <strong>the</strong> central processor.<br />

All processors are connected <strong>to</strong> an Internal<br />

Communication <strong>Network</strong> (ICN). Depending<br />

on <strong>the</strong> size of <strong>the</strong> <strong>Network</strong> Elements,<br />

different internal communication<br />

network structures have been implemented,<br />

Fig. 4.<br />

The central processor houses <strong>the</strong> MIB, on<br />

which <strong>the</strong> OS and <strong>the</strong> local opera<strong>to</strong>r perform<br />

management operations. It will also<br />

implement parts of <strong>the</strong> MCF functionality,<br />

such as a network layer routing function<br />

between <strong>the</strong> Q- interface and <strong>the</strong> ECC subnetworks.<br />

The central processor can vary in size from<br />

small and inexpensive one-board microprocessor-based<br />

systems, <strong>to</strong> high-capacity<br />

redundant computers.<br />

Each of <strong>the</strong> different printed board assemblies<br />

under <strong>the</strong> control of <strong>the</strong> Central Processor<br />

contains its own Unit Processor.<br />

The Unit Processor is a building block consisting<br />

of a microprocessor, memories,<br />

communication controllers and A/D and<br />

D/A converters when required.<br />

The Unit Processors perform routine tasks<br />

on each printed board assembly, such as<br />

alarm surveillance, collection of performance<br />

parameters, and self-diagnostics.<br />

The Unit Processors also control <strong>the</strong> lower<br />

layers of <strong>the</strong> ECC pro<strong>to</strong>col suite.<br />

The control system software modularity is<br />

ensured through <strong>the</strong> use of a layered structure<br />

combined with object-oriented techniques.<br />

Programs can be downloaded from an Operations<br />

System all <strong>the</strong> way down <strong>to</strong> a Unit<br />

Processor.<br />

Control of Switching <strong>Network</strong><br />

Besides Unit Processors and <strong>the</strong> Central<br />

Processor, <strong>the</strong> control circuitry of <strong>the</strong><br />

SDXC switch, SNC, is also connected <strong>to</strong><br />

<strong>the</strong> Internal Communication <strong>Network</strong>. This<br />

means that all processors can set up and<br />

release cross-connections in <strong>the</strong> SDXC.<br />

This facility comes in<strong>to</strong> use, for example,<br />

when rapid switching has <strong>to</strong> be performed<br />

due <strong>to</strong> a transport network fault discovered<br />

by an access unit. In this case <strong>the</strong> Unit<br />

Processor on <strong>the</strong> access unit immediately<br />

reconfigures <strong>the</strong> switch according <strong>to</strong> a predefined<br />

configuration previously communicated<br />

<strong>to</strong> <strong>the</strong> Unit Processor by <strong>the</strong> Central<br />

Processor. The Central Processor is<br />

always informed of <strong>the</strong> resulting configuration.<br />

Unit Processors<br />

Unit Processors typically occupy part of a<br />

board in <strong>the</strong> SDXC. A unit in <strong>the</strong> SDXC normally<br />

consists of only one board. A Unit<br />

Processor includes a microprocessor chip<br />

and memory. Its current implementation is<br />

a Mo<strong>to</strong>rola 68 302.<br />

A Unit Processor continuously performs<br />

tasks such as moni<strong>to</strong>ring of hardware and<br />

calculation of bit errors, but at <strong>the</strong> same<br />

time it must react quickly <strong>to</strong> events such<br />

as incoming alarms from <strong>the</strong> transport network.<br />

The unit processor is <strong>the</strong>refore<br />

equipped with a real-time operating system<br />

kernel, OS 68, which gives response<br />

times on a microsecond level.<br />

SDXC CONTROL SYSTEM<br />

ARCHITECTURE<br />

General<br />

The SDXC control system may be composed<br />

of a central processor and up <strong>to</strong> a<br />

couple of 100 Unit Processors. It uses a<br />

packet-switched Internal Communication<br />

<strong>Network</strong> (ICN) which is integrated with <strong>the</strong><br />

switch.<br />

Purchased hardware and software is used;<br />

<strong>the</strong> Central Processor being a UNIX computer,<br />

for example.<br />

Central processor<br />

The Central Processor is <strong>the</strong> coordina<strong>to</strong>r<br />

and master of <strong>the</strong> complete control system.<br />

It continuously moni<strong>to</strong>rs <strong>the</strong> Internal<br />

Communication <strong>Network</strong> <strong>to</strong> find new Unit<br />

Processors. Local opera<strong>to</strong>rs have access<br />

<strong>to</strong> <strong>the</strong> SDXC system via graphical workstations.<br />

These are connected <strong>to</strong> <strong>the</strong> Central<br />

Processor via an E<strong>the</strong>rnet Local Area<br />

<strong>Network</strong>, Fig. 5. Both <strong>the</strong> Central Processor<br />

and <strong>the</strong> opera<strong>to</strong>r workstations are<br />

UNIX machines based on SPARC architecture,<br />

<strong>the</strong> Central Processor being a<br />

ERICSSON REVIEW No. 3, 1992

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