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84<br />

Fig. 4<br />

AXD 4/1 Devices<br />

Devices of AXD 4/1, Fig. 4, can be divided<br />

in<strong>to</strong> four different groups:<br />

- Terminal Access Units (TAU) interfacing<br />

plesiochronous transmission systems:<br />

• TAU 140, interfacing 140 Mbit/s signals<br />

• TAU 34, interfacing 34 Mbit/s signals<br />

• TAU 16x2, interfacing sixteen 2 Mbit/s<br />

signals<br />

- TAU interfacing transmission signals belonging<br />

<strong>to</strong> <strong>the</strong> Synchronous Digital Hierarchy<br />

(SDH) family:<br />

•TAU STM-1E, interfacing 155 Mbit/s<br />

electric signals<br />

• STM-1 and STM-4 optical TAU will be<br />

provided later on<br />

- Devices interfacing special external signals:<br />

• ESU, External Synchronisation Unit for<br />

2 MHz synchronisation signals<br />

- Devices for internal use:<br />

• CTU, Control Termination Unit, access<br />

unit for <strong>the</strong> Central Processor.<br />

Power distribution<br />

Power distribution in AXD 4/1 is decentralised.<br />

All boards containing electronic components<br />

are equipped with <strong>the</strong>ir own<br />

DC/DC converters, which produce <strong>the</strong> necessary<br />

voltages from <strong>the</strong> duplicated -48 V<br />

power source. This makes it possible <strong>to</strong><br />

have truly duplicated power supply all <strong>the</strong><br />

way from <strong>the</strong> exchange battery <strong>to</strong> <strong>the</strong> PBAs.<br />

Hardware Structure<br />

Basic Technology and Methodology<br />

The major part of <strong>the</strong> Hardware (HW) of<br />

AXD units is realised with Application Specific<br />

Integrated Circuits (ASIC). Texas BiC-<br />

MOS is used for high-speed applications.<br />

BiCMOS is a 0.8 micron process whose<br />

available speed in AXD applications exceeds<br />

200 MHz. Gate arrays with a maximum<br />

of 100,000 usable gates are available.<br />

Mo<strong>to</strong>rola HCMOS 0.7 micron circuits<br />

are used for o<strong>the</strong>r system parts. Max.<br />

speed in AXD applications is above 60<br />

MHz, and arrays with 127,000 usable<br />

gates are used.<br />

Structured HW design methodology has<br />

been used when designing ASICs. This<br />

means that functions are described in a<br />

High Level Language (Verilog); <strong>the</strong> code<br />

is <strong>the</strong>n syn<strong>the</strong>sised <strong>to</strong> gates and flip-flops<br />

by a syn<strong>the</strong>sis program (Synopsys). This<br />

procedure increases design efficiency and<br />

facilitates <strong>the</strong> structuring of large arrays.<br />

The occurrence of a number of high-speed<br />

signals between different units places extremely<br />

stringent requirements on <strong>the</strong> analog<br />

parts. <strong>An</strong>alog parts handle <strong>the</strong> termination,<br />

generation and regeneration of line<br />

signals, and phase and frequency control<br />

of signals. A library of analog blocks with<br />

schematics, component specifications<br />

and layouts has been created, which allows<br />

identical functions <strong>to</strong> be implemented<br />

in <strong>the</strong> same way in <strong>the</strong> different Devices.<br />

The use of one standard internal<br />

interface reduces <strong>to</strong> <strong>the</strong> absolute minimum<br />

<strong>the</strong> problems with analog design.<br />

A new metric building practice conforming<br />

<strong>to</strong> ETSI standard is used. Boards with 6 <strong>to</strong><br />

10 layers are placed in cabinets with a<br />

board spacing down <strong>to</strong> 16 mm. Circuit<br />

ERICSSON REVIEW No. 3, 1992

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