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88<br />

Fig. 8<br />

Protection Switch Unit structure<br />

The triplication of <strong>the</strong> Switch structure includes<br />

<strong>the</strong> TCUs<br />

ESU is used for synchronisation of <strong>the</strong><br />

AXD with external 2 MHz synchronisation<br />

signals. ESU compares <strong>the</strong> frequency of<br />

<strong>the</strong> incoming 2 MHz signal with <strong>the</strong> divided<br />

signal from AXD's internal clock. The<br />

result of this comparison is sent <strong>to</strong> <strong>the</strong> Central<br />

Processor (CP) for control of <strong>the</strong> clock<br />

modules. The generation of <strong>the</strong> 2 MHz timing<br />

information is also performed by <strong>the</strong><br />

ESU. Frequency division logic is performed<br />

in a Field Programmable Gate<br />

Array (FPGA), and one ASIC is used for<br />

SNI-3 communication.<br />

CTU is used for connection of <strong>the</strong> CP <strong>to</strong><br />

<strong>the</strong> AXD. The CP is connected via E<strong>the</strong>rnet,<br />

and control information is converted<br />

<strong>to</strong> <strong>the</strong> internal Basic Control Pro<strong>to</strong>col<br />

(BCP) embedded in SNI interfaces. One<br />

ASIC is used for SNI-3 communication.<br />

TAU 34, TAU 16x2, ESU and CTU are located<br />

in <strong>the</strong> same magazine. In this magazine<br />

<strong>the</strong>re are three TCUs used by <strong>the</strong><br />

SNI-3 Devices for communication <strong>to</strong>/from<br />

<strong>the</strong> Switching <strong>Network</strong>. Devices can be<br />

mixed arbitrarily, except for <strong>the</strong> CTUs,<br />

which have two specific slots. This flexibility<br />

permits efficient utilisation of available<br />

space when <strong>the</strong> exchange layout is made.<br />

Conclusions<br />

The AXD 4/1 system presented is a system<br />

with great flexibility and a functional<br />

distribution that makes it useful in a wide<br />

variety of network applications. High availability,<br />

thanks <strong>to</strong> <strong>the</strong> use of triplicated HW,<br />

as well as an open architecture have been<br />

key concepts in <strong>the</strong> system design.<br />

The system handles accesses ranging<br />

from 1.5 Mbit/s up <strong>to</strong> 155 Mbit/s, PDH (both<br />

NAS and CEPT) as well as SDH. Switching<br />

can be performed at all levels from<br />

576 kbit/s (9x64 kbit/s) <strong>to</strong> 155 Mbit/s in<br />

steps of 576 kbit/s including all standardised<br />

signal levels.<br />

References<br />

1 CCITT Rec. G.703<br />

2 CCITT Rec. G 707-709<br />

3 <strong>An</strong>dersson, JO.: Digital Cross-Connect<br />

Systems - a System Family for <strong>the</strong> <strong>Transport</strong><br />

<strong>Network</strong>. <strong>Ericsson</strong> Review 67<br />

(1990):2, pp. 72-83.<br />

4 Breuer, H-J. and Hellstrom, B.: Synchronous<br />

<strong>Transport</strong> <strong>Network</strong>s. <strong>Ericsson</strong> Review<br />

67(1990):2, pp. 60-71.<br />

ERICSSON REVIEW No. 3. 1992

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