Part 4 JPL Chips - Eric Fossum

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JPL/AT&T 1024 x 1024 CMOS APS

Closeup of pixels

Chip

Dickinson, Ackland, Azadet, Inglis, Mendis, Jones and Fossum 1995

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JPL/AT&T DIGITAL CMOS APS • 176x144 elements • 20 μm pixel pitch • Single-slope ADC per column • 176 ADCs per chip • 8 bit resolution • 35 mW at 30 Hz • 3.5 volt supply Mendis, Inglis, Dickinson, and Fossum 1995

JPL/AT&T 1024 x 1024 CMOS APS Closeup of pixels Chip Dickinson, Ackland, Azadet, Inglis, Mendis, Jones and Fossum 1995

Page 1 and 2: INITIAL CMOS APS DEVELOPMENT AT JPL
Page 3 and 4: CC128 - ANALOG OUTPUT JPL L A T C H
Page 5 and 6: MOTION DETECTION Motion to left Nor
Page 7 and 8: JPL/KODAK PPD CMOS APS • Pinned p
Page 9: JPL HIGH SPEED CMOS APS Timing i An
Page 13 and 14: 1024 x 1024 CMOS APS WITH 1024 ON-C
Page 15 and 16: PHOTOELECTRON COUNTING MUX Single-S
Page 17: B k R P i i M i St ll G J K lt Back

Part 4 JPL Chips - Eric Fossum

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