Part 4 JPL Chips - Eric Fossum

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CC256 - ANALOG OUTPUT Pixel size: 20.4 μm Pixel type: photogate Fill factor: 21% Technology: HP 1.2 μm n-well Array size: 256x256 Conv. Gain: 10.6 μV/e- Timing, control, CDS Saturation: 800 mV FPN suppression Noise: 13 e- rms Motion detection FPN: 0.15% sat Window readout Dyn. range: 76 dB Program. integration time Power: 3mW Nixon, Kemeny and <strong>Fossum</strong> 1995
MOTION DETECTION Motion to left Normal image Motion to right • Use floating diffusion i as analog frame memory • No change to pixel design, just timing
Page 1 and 2: INITIAL CMOS APS DEVELOPMENT AT JPL
Page 3: CC128 - ANALOG OUTPUT JPL L A T C H
Page 7 and 8: JPL/KODAK PPD CMOS APS • Pinned p
Page 9 and 10: JPL HIGH SPEED CMOS APS Timing i An
Page 11 and 12: JPL/AT&T 1024 x 1024 CMOS APS Close
Page 13 and 14: 1024 x 1024 CMOS APS WITH 1024 ON-C
Page 15 and 16: PHOTOELECTRON COUNTING MUX Single-S
Page 17: B k R P i i M i St ll G J K lt Back

Part 4 JPL Chips - Eric Fossum

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