Part 4 JPL Chips - Eric Fossum

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12 BIT Σ−Δ CURRENT MODE ADC I IN INTEGRATOR n-CCC p-CCC INTEGRATOR n-CCC COMPARATOR COMPARATOR a b DIGITAL FILTER D11 • 12 bit oversampled 2nd order ADC • Current mode implementation p-CCC • 2 μm m Olympus CMOS process D0 • 3 modulators in test chip I REF I REF • ADC is 80 μm x 1.9 mm 1 bit D/A 1 bit D/A er (DN) Output Data Numb 4000 3500 3000 2500 2000 1500 1000 Output vs. Input Performance • 5-10 kS/sec per channel •
B k R P i i M i St ll G J K lt Back Row: Panicacci, Mansoorian, Staller, Gee, Jones, Koulter Front Row: Nixon, Kim, <strong>Fossum</strong>, Pain, Zhou, Yadid-Pecht <strong>JPL</strong> CMOS APS TEAM
Page 1 and 2: INITIAL CMOS APS DEVELOPMENT AT JPL
Page 3 and 4: CC128 - ANALOG OUTPUT JPL L A T C H
Page 5 and 6: MOTION DETECTION Motion to left Nor
Page 7 and 8: JPL/KODAK PPD CMOS APS • Pinned p
Page 9 and 10: JPL HIGH SPEED CMOS APS Timing i An
Page 11 and 12: JPL/AT&T 1024 x 1024 CMOS APS Close
Page 13 and 14: 1024 x 1024 CMOS APS WITH 1024 ON-C
Page 15: PHOTOELECTRON COUNTING MUX Single-S

Part 4 JPL Chips - Eric Fossum

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