Part 4 JPL Chips - Eric Fossum

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JPL MULTIRESOLUTION SENSOR Imaging Array Analog Digital Control Process: HP 1.2 um n-well CMOS Pixel pitch: 24 um No. pixels: 128 x 128 Pwr suppy: 5 volts Saturation: 1200 mV Conv. gain: 8 uV/e- Noise: 116 uV rms 15 e- rms Dynamic 80 dB Range: FPN:
JPL HIGH SPEED CMOS APS Timing i Analog Pixel Array Digital • 128x128 elements • Photodiode active pixels • 16 μm pixel pitch • Analog output (top) • 1-bit Digital output (bottom) • 8,000 frames per second • On-chip timing and control Panicacci, Jones, Fossum 1994 Analog Output Digital Output
Page 1 and 2: INITIAL CMOS APS DEVELOPMENT AT JPL
Page 3 and 4: CC128 - ANALOG OUTPUT JPL L A T C H
Page 5 and 6: MOTION DETECTION Motion to left Nor
Page 7: JPL/KODAK PPD CMOS APS • Pinned p
Page 11 and 12: JPL/AT&T 1024 x 1024 CMOS APS Close
Page 13 and 14: 1024 x 1024 CMOS APS WITH 1024 ON-C
Page 15 and 16: PHOTOELECTRON COUNTING MUX Single-S
Page 17: B k R P i i M i St ll G J K lt Back

Part 4 JPL Chips - Eric Fossum

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