Digital IC Design

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Basic Standards of Timing Diagrams Basic I/O Signals 1. CS: Chip Select 2. Adr.: Address 3. WE: Write Enable 4. OE: Output Enable 5. Di: Data-input 6. Do: Data-output 7. RAS: Row Address Strobe 8. CAS: Column Address Strobe T.-C. Huang, NCUE Fall 2004 TCH NCUE Page 24
Basic Standards of Timing Diagrams Approaches 1. JEDEC (Joint Electronics Device Engineering) 2. EIAJ 3. IEC 1. JEDEC Standard Timing Symbol 2. Order notes in parentheses 3. Causal Arrows 4. Description T.-C. Huang, NCUE Fall 2004 TCH NCUE Page 25
Page 1 and 2: Digital IC Design Tsung-Chu Huang D
Page 3 and 4: Moore’s Law on Transistor Counts
Page 5 and 6: Moore’s Law on Memory 10 20 bits
Page 7 and 8: Taxonomy 1. by Access Structure 1.
Page 9 and 10: Basic Static RAM (SRAM) Bit Line Bi
Page 11 and 12: Amplification of SA T.-C. Huang, NC
Page 13 and 14: Basic SRAM Architecture Row/Column
Page 15 and 16: Basic SRAM Architecture An Embedded
Page 17 and 18: Related Techniques of DRAM 1. EDO:
Page 19 and 20: Write Historical Evolution of DRAM
Page 21 and 22: DRAM Cylindrical Stacked Cells T.-C
Page 23: Typical Storage Hierarchy FF Regist
Page 27 and 28: Write Cycle T.-C. Huang, NCUE Fall
Page 29 and 30: Address-Multiplexed Read Timing T.-
Page 31: Brief Introduction to Memory Test F

Digital IC Design

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