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April<br />
2013<br />
v5.0<br />
<strong>FPGA</strong> <strong>Boards</strong><br />
ASIC Prototyping<br />
<strong>FPGA</strong>-Based High Performance Computing<br />
Low Latency Trading
<strong>FPGA</strong><br />
Speed Grades<br />
(slowest to<br />
fastest)<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(18x18)<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
Xilinx<br />
Virtex-6<br />
Kintex-7 Virtex-7<br />
HXT SXT LXT LX<br />
VH V<br />
Spartan<br />
-6<br />
LX VX<br />
7V2000T -1,-2 2,443,200 23,455 14,070 1,200 2,160 2,584 46,512 5,814<br />
7V585T -1,-2,-3 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578<br />
7VX1140T -1,-2 1,424,000 13,670 8,200 1,100 3,360 3,760 67,680 8,460<br />
7VX980T -1,-2 1,224,000 11,750 7,050 880 3,600 3,000 54,000 6,750<br />
7VX690T -1,-2,-3 866,400 8,317 4,990 1,000 3,600 2,940 52,920 6,615<br />
7VX550T -1,-2,-3 692,800 6,651 3,990 600 2,880 2,360 42,480 5,310<br />
7VX485T -1,-2,-3 607,200 5,829 3,500 700 2,800 2,060 37,080 4,635<br />
7VX415T -1,-2,-3 515,200 4,946 2,970 600 2,160 1,760 31,680 3,960<br />
7VX330T -1,-2,-3 408,000 3,917 2,350 700 1,120 1,500 27,000 3,375<br />
7VH870T -1,-2 1,095,200 10,514 6,310 700 2,520 2,820 50,760 6,345<br />
7VH580T -1,-2 725,600 6,966 4,180 600 1,680 1,880 33,840 4,230<br />
7K480T -1,-2,-3 597,200 5,733 3,440 400 1,920 1,910 34,380 4,298<br />
7K420T -1,-2,-3 521,200 5,004 3,000 350 1,680 1,670 30,060 3,758<br />
7K410T -1,-2,-3 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578<br />
7K355T -1,-2,-3 445,200 4,274 2,560 300 1,440 1,430 25,740 3,218<br />
7K325T -1,-2,-3 407,600 3,913 2,350 500 840 890 16,020 2,003<br />
7K160T -1,-2,-3 202,800 1,947 1,170 400 600 650 11,700 1,463<br />
7K70T -1,-2,-3 82,000 787 470 300 240 270 4,860 608<br />
LX760 -1L,-1,-2 948,480 9,105 5,509 1,200 864 1,440 25,920 3,240<br />
LX550T -1L,-1,-2 687,360 6,599 4,000 1,200 864 1,264 22,752 2,844<br />
LX365T -1L,-1,-2,-3 455,040 4,368 2,621 600 576 832 14,976 1,872<br />
LX240T -1L,-1,-2,-3 301,440 2,894 1,736 600 768 832 14,976 1,872<br />
LX195T -1L,-1,-2,-3 249,600 2,396 1,438 600 640 688 12,384 1,548<br />
LX130T -1L,-1,-2,-3 160,000 1,536 922 600 480 528 9,504 1,188<br />
SX475T -1L,-1,-2 595,200 5,714 3,428 600 2,016 2,128 38,304 4,788<br />
SX315T -1L,-1,-2,-3 394,000 3,782 2,269 600 1,344 1,408 25,344 3,168<br />
HX565T -1,-2 708,000 6,797 4,078 720 864 1,824 32,832 4,104<br />
HX380T -1,-2,-3 478,000 4,589 2,753 720 864 1,536 27,648 3,456<br />
LX150T -2,-3N,-3,-4 184,464 1,771 1,063 540 180 268 4,824 603<br />
LX150 -1L,-2,-3N,-3 184,464 1,771 1,063 338 180 268 4,824 603<br />
LX100 -1L,-2,-3N,-3 126,576 1,215 729 326 180 268 4,824 603<br />
LX75 -1L,-2,-3N,-3 93,000 893 536 280 132 172 3,096 387<br />
LX45 -1L,-2,-3N,-3 54,576 524 314 316 58 116 2,088 261<br />
Virtex-5<br />
FXT SXT LXT LX<br />
LX330 -1,-2 207,360 3,320 1,990 1,200 192 576 10,368 1,296<br />
LX220 -1,-2 138,240 2,210 1,330 800 128 384 6,912 864<br />
LX155 -1,-2,-3 97,280 1,556 934 800 128 384 6,912 864<br />
LX110 -1,-2,-3 69,120 1,110 670 800 64 256 4,608 576<br />
LX155T -1,-2,-3 97,280 1,556 934 640 128 424 7,632 954<br />
LX110T -1,-2,-3 69,120 1,110 666 640 64 296 5,328 666<br />
LX85T -1,-2,-3 51,840 830 498 480 48 216 3,888 486<br />
LX50T -1,-2,-3 28,800 460 276 480 48 120 2,160 270<br />
LX30T -1,-2,-3 19,200 307 184 360 32 72 1,296 162<br />
SX95T -1,-2,-3 58,880 940 564 640 640 488 8,784 1,098<br />
SX50T -1,-2,-3 32,640 522 313 480 288 264 4,752 594<br />
SX35T -1,-2,-3 21,760 392 235 360 192 168 3,024 378<br />
FX100T -1,-2,-3 64,000 1,024 614 640 256 456 8,208 1,026<br />
FX70T -1,-2,-3 44,800 717 430 640 128 296 5,328 666<br />
FX30T -1,-2,-3 20,480 328 197 360 64 136 2,448 306<br />
<strong>FPGA</strong><br />
Speed Grades<br />
(slowest to<br />
fastest)<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(18x18)<br />
MLAB<br />
(640)<br />
M9K<br />
(9 kbit)<br />
Memory<br />
M144K<br />
(144 kbit)<br />
M20K<br />
(20 kbit)<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
Altera<br />
Stratix V<br />
GT GS GX E<br />
ArriaV GZ<br />
Stratix IV<br />
Stratix III<br />
Cyclone III<br />
5SEEB -4,-3,-2 1,437,000 13,795 8,280 840 704 15850 2,640 52,800 6,600<br />
5SEE9 -4,-3,-2 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600<br />
5SGXAB -4,-3,-2 1,437,000 13,795 8,280 840 704 17960 2,640 52,800 6,600<br />
5SGXA9 -4,-3,-2 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600<br />
5SGXA7 -4,-3,-2 939,000 9,014 5,410 840 512 11736 2,560 51,200 6,400<br />
5SGXB6 -4,-3,-2 902,000 8,659 5,200 600 798 11270 2,660 53,200 6,650<br />
5SGXB5 -4,-3,-2 740,000 7,104 4,260 600 798 9250 2,100 42,000 5,250<br />
5SGXA5 -4,-3,-2 740,000 7,104 4,260 840 512 8020 2,304 46,080 5,760<br />
5SGXA4 -4,-3,-2 634,000 6,086 3,650 696 512 5880 1,900 38,000 4,750<br />
5SGXA3 -4,-3,-2 513,000 4,925 2,960 696 512 3776 957 19,140 2,393<br />
5SGSD8 -4,-3,-2 1,050,000 10,080 6,050 840 3926 2624 2,567 51,340 6,418<br />
5SGSD6 -4,-3,-2 880,000 8,448 5,070 480 3550 2320 2,320 46,400 5,800<br />
5SGSD5 -4,-3,-2 690,000 6,624 3,970 696 3180 2014 3,180 63,600 7,950<br />
5SGSD4 -4,-3,-2 543,000 5,213 3,130 696 2088 1062 2,088 41,760 5,220<br />
5SGSD3 -4,-3,-2 356,000 3,418 2,050 432 1200 686 1,200 24,000 3,000<br />
5SGTC7 -4,-3,-2 939,000 9,014 5,410 600 512 2560 2,560 51,200 6,400<br />
5SGTC5 -4,-3,-2 642,000 6,163 3,700 600 512 2304 2,304 46,080 5,760<br />
5AGZME7 -4,-3 679,200 6,520 3,910 674 2278 5306 1700 34,000 4,250<br />
5AGZME5 -4,-3 603,840 5,797 3,480 674 2184 4718 1440 28,800 3,600<br />
5AGZME3 -4,-3 543,360 5,216 3,130 414 2088 1044 957 19,140 2,393<br />
5AGZME1 -4,-3 332,080 3,188 1,910 414 1600 800 585 11,700 1,463<br />
4SE820 -4,-3 650,440 10,407 6,504 1120 960 16261 1610 60 23,130 2,891<br />
4SE530 -4,-3,-2 424,960 6,799 4,080 960 1024 10624 1280 64 20,736 2,592<br />
3SL340 -4,-3,-2 270,000 4,320 2,592 1120 576 6750 1040 48 16,272 2,034<br />
3C120 -8,-7 119,088 1,667 1,000 288 0<br />
432<br />
3,888 486<br />
3C16 -8,-7,-6 15,408 216 134 56 0<br />
56<br />
504 63<br />
2<br />
www.dinigroup.com
WHO, WHAT, WHERE, WHY?<br />
Who are you?<br />
<strong>The</strong> DINI <strong>Group</strong> was formed in May of 1995. We started as a consulting organization<br />
specializing in <strong>FPGA</strong> and board-level design. We branched into ASIC design in 1998, with<br />
particular emphasis in PCI and PCI-X. Our standard products are the direct result of unmet<br />
<strong>FPGA</strong>-based product needs discovered in our consulting practice. At present we have 20<br />
employees.<br />
Measured in numbers of gates shipped, we are the world’s<br />
leading provider of ASIC prototyping hardware.<br />
What are your products?<br />
We make big <strong>FPGA</strong> boards. <strong>The</strong> most common application for big <strong>FPGA</strong> boards is ASIC<br />
and SOC prototyping. Big <strong>FPGA</strong> boards in specialized configurations can be used to<br />
accelerate certain types of algorithms. In other configurations, large <strong>FPGA</strong> boards can be<br />
used for high frequency, low-latency trading.<br />
Where?<br />
We are based in La Jolla,<br />
California. La Jolla is about<br />
10 miles north of San Diego.<br />
Why?<br />
<strong>FPGA</strong> Prototyping is rapidly<br />
becoming a requirement due<br />
to the complexity and costs<br />
of ASIC tapeouts and spins.<br />
But <strong>FPGA</strong> boards required<br />
specialized teams to design<br />
and build. It is much easier and cheaper to buy off-the-shelf <strong>FPGA</strong> boards from those of us<br />
that already have that specialized set of skills.<br />
858 . 454 . 3419 3
Feature Breakdown: DNV7F2A<br />
iPASS connectors for<br />
4-lane PCIe GEN2<br />
SFP+ for 10GbE<br />
QSPF+ for<br />
10 and 40 GbE<br />
Add 40 GbE, 10GbE<br />
PCIe et al with DNSEAM<br />
Expansion Cards<br />
(page 41)<br />
7V2000T Xilinx Virtex-7<br />
<strong>FPGA</strong>s.<strong>The</strong> largest <strong>FPGA</strong><br />
ever created. 14 million<br />
ASIC gates plus memory<br />
and multipliers each!<br />
POWER!<br />
75A per <strong>FPGA</strong><br />
for VCCINT<br />
4<br />
www.dinigroup.com
HOSTING THE LARGEST <strong>FPGA</strong> EVER!<br />
USB 3.0 / 2.0<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
72<br />
3<br />
DINAR1<br />
Expansion Connector<br />
1<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
0<br />
DINAR1<br />
Expansion Connector<br />
72<br />
2<br />
SATA II<br />
(device)<br />
4<br />
72<br />
72<br />
72<br />
72 72<br />
72<br />
2<br />
SATA II<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
10GbE<br />
Ethernet<br />
24<br />
MHz<br />
SMA<br />
JTAG<br />
0<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
G1<br />
Config Clk OSC<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
8<br />
1<br />
1<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
4<br />
G2<br />
<strong>FPGA</strong><br />
0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
RS232<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
Step Clock<br />
Config Clk OSC<br />
GTX<br />
10Gb/s<br />
NMB0<br />
YMB<br />
150<br />
150<br />
16<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
40<br />
NMB1<br />
40<br />
YMB<br />
NMB 1<br />
NMB 2<br />
<strong>FPGA</strong><br />
1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
40<br />
40<br />
SEAF<br />
DNNMB<br />
Connector<br />
(400 pins)<br />
5<br />
5<br />
5<br />
Global<br />
Clocks<br />
4<br />
8<br />
1<br />
4<br />
iPASS<br />
Stacking<br />
PCIe<br />
(GEN2)<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
QSFP+<br />
10GbE<br />
Ethernet<br />
40 GbE or<br />
4, 10 GbE<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G3<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G4<br />
10/100/1000 10/100/1000<br />
baseT<br />
Phy<br />
RJ45<br />
RS232<br />
USB 2.0<br />
(2X)<br />
RGMII<br />
2<br />
USB<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
PCIe<br />
Device Bus<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU FPU<br />
CPU CPU<br />
OSC<br />
64<br />
3<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
SATA II<br />
(host)<br />
2x<br />
RTC<br />
4-lanes<br />
PCIe (GEN1)<br />
8<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
Marvell Processor running Linux host this<br />
board via USB2.0, Ethernet, or PCIe GEN2<br />
5 Global Clocks programmable to<br />
any frequency 2KHz to 710 MHz<br />
DINAR1 Expansion Connectors<br />
Add memory (page 32)<br />
Add custom peripherals<br />
Add off-the-shelf boards (page 33)<br />
Stack two boards together (page 12)<br />
We don’t like hamsters and<br />
we don’t think hamster cages<br />
belong in engineering labs!<br />
858 . 454 . 3419 5
DNV7F4A: Godzilla’s Butcher<br />
Memory / Expansion / Stacking<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
3<br />
top<br />
DINAR1<br />
Expansion Connector<br />
1<br />
DINAR1<br />
Expansion Connector<br />
0<br />
top<br />
DINAR1<br />
Expansion Connector<br />
2<br />
72<br />
72 72 72 72<br />
72<br />
SATA<br />
(device)<br />
1<br />
72<br />
72<br />
1<br />
SMA<br />
4x 10GbE<br />
or<br />
1x 40GbE<br />
QSFP+<br />
GTX Expansion<br />
DNSEAM_NS<br />
- 8-lane PCIe(GEN1/GEN2)<br />
- 2x CX4 Ethernet<br />
XAUI<br />
Infiniband<br />
- 8x SFP+ 10GbE et al.<br />
- 2x QSFP+ 40GbE<br />
- 8x USB 3.0/2.0<br />
A, B, AB<br />
- 8x SATA II<br />
- 8x SMA<br />
4<br />
8<br />
GTX<br />
GTX<br />
GTX<br />
<strong>FPGA</strong> B<br />
Virtex-7<br />
7V2000T<br />
(FLG1925)<br />
1<br />
GTX<br />
150 150<br />
40<br />
YMB<br />
NMB1<br />
75<br />
1<br />
1<br />
150<br />
150<br />
GTX<br />
NMB2<br />
GTX<br />
1<br />
75<br />
GTX<br />
40<br />
YMB<br />
<strong>FPGA</strong> C<br />
Virtex-7<br />
7V2000T<br />
(FLG1925)<br />
150 150<br />
1 GTX<br />
GTX<br />
4<br />
8<br />
GTX<br />
GTX<br />
SFP+<br />
GTX Expansion<br />
DNSEAM_NS<br />
4x 10GbE<br />
- 8-lane PCIe(GEN1/GEN2)<br />
- 2x CX4 Ethernet<br />
XAUI<br />
Infiniband<br />
- 8x SFP+ 10GbE et al.<br />
- 2x QSFP+ 40GbE<br />
- 8x USB 3.0/2.0<br />
A, B, AB<br />
- 8x SATA II<br />
- 8x SMA<br />
4x 10GbE<br />
or<br />
1x 40GbE<br />
GTX Expansion<br />
DNSEAM_NS<br />
QSFP+<br />
SATA<br />
(host)<br />
8<br />
4<br />
1<br />
GTX<br />
GTX<br />
GTX<br />
<strong>FPGA</strong> A<br />
Virtex-7<br />
7V2000T<br />
(FLG1925)<br />
1<br />
NMB0<br />
75<br />
75<br />
150<br />
150<br />
GTX<br />
NMB3<br />
<strong>FPGA</strong> D<br />
Virtex-7<br />
7V2000T<br />
(FLG1925)<br />
8<br />
4<br />
1<br />
GTX<br />
GTX<br />
GTX Expansion<br />
DNSEAM_NS<br />
SMA<br />
iPASS<br />
PCIe (GEN1/GEN2)<br />
4-lanes<br />
72<br />
72<br />
72 72 72 72 72<br />
72<br />
DINAR1<br />
Expansion Connector<br />
3<br />
DINAR1<br />
Expansion Connector<br />
1<br />
DINAR1<br />
Expansion Connector<br />
0<br />
DINAR1<br />
Expansion Connector<br />
2<br />
bottom<br />
bottom<br />
Memory / Expansion / Stacking<br />
Memory / Expansion / Stacking<br />
SEAF<br />
RS232<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
Step Clock<br />
Config Clk<br />
OSC<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
YMB<br />
NMB 1<br />
NMB 2<br />
40<br />
40<br />
40<br />
DNNMB<br />
Connector<br />
(400 pins)<br />
5<br />
5<br />
5<br />
Global<br />
Clocks<br />
Stacking<br />
10/100/1000 10/100/1000<br />
baseT<br />
Phy<br />
RJ45<br />
RS232<br />
USB 2.0<br />
(2X)<br />
RGMII<br />
2<br />
USB<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
PCIe<br />
Device Bus<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU<br />
FPU<br />
CPU CPU<br />
OSC<br />
64<br />
3<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
SATA II<br />
(host)<br />
2x<br />
RTC<br />
4-lanes<br />
PCIe (GEN1)<br />
8<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
6<br />
www.dinigroup.com<br />
PCI EXPRESS<br />
Cable (GEN1)
four Virtex-7 <strong>FPGA</strong>s | 7V2000T-1 | 56 million ASIC gates | stackable<br />
Features<br />
• Hosted via<br />
- 4-lane GEN2 PCIe via iPASS cable, USB2.0<br />
- 10/100/1000BASE-T Ethernet, or Stand alone<br />
• Four Xilinx Virtex-7 <strong>FPGA</strong>s (FLG1925):<br />
- 7V2000T-2,-1 (fastest to slowest)<br />
• 56+ million ASIC gates (ASIC measure) when<br />
stuffed with four 7V2000Ts<br />
• Memory can be added using DINAR1_SODM204 on<br />
a DINAR1 expansion connector:<br />
- DNSODM204_SSRAM (1.8V version)<br />
- DNSODM204_QUADMIC (four mictor connectors)<br />
- DNSODM204_SE (mobile SDRAM)<br />
- DNSODM204_USB (USB2.0 PHY)<br />
- DNSODM204_DDR2_FAST<br />
- DNSODM204_QDRII+<br />
- DNSODM204_DDR2_2GB<br />
- DNSODM204_MICTOR_IO (dual Mictor connectors)<br />
• Marvel MV78200 Discovery Innovation Dual CPU<br />
- 1 GHz clock<br />
- Dual USB2.0 ports (Type B connector)<br />
- Dual Serial-ATA II connectors for 2 external hard<br />
drives (SATA II)<br />
- Gigabit Ethernet interface<br />
• 10/100/1000 GbE (RJ45 connector)<br />
- Sheeva CPU Core (ARM v5TE compliant)<br />
• Out-of-order execution<br />
• Single and double-precision IEEE compliant<br />
floating point<br />
• 16-bit Thumb instruction set increases code<br />
density<br />
• DSP instructions boosts performance for signal<br />
processing applications<br />
• MMU to support virtual memory features<br />
• Dual Cache: 32 KB for data and instruction,<br />
parity protected<br />
• L2 cache: 512 KB unified L2 cache per CPU<br />
(total of 1MB), ECC protected.<br />
- 1 GB external DDR2 SDRAM<br />
• Organized in a 128M x 64 configuration<br />
• 400 MHz (800 MHz data rate with DDR)<br />
- RS232 port for terminal-style observation<br />
- After configuration, both CPUs dedicated entirely<br />
to user application<br />
- Linux operating system<br />
• Source and examples provided via GPL license<br />
(no charge)<br />
• ~15 seconds to CPU boot<br />
• Five independent low-skew global clock networks<br />
and single fixed clock<br />
- Five, high-resolution, user-programmable synthe<br />
sizers for G0, G1, G2<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
- User configurable via Marvell uP RS232, USB,<br />
PCIe, or Ethernet<br />
- Global clocks networks distributed differentially<br />
and balanced<br />
• Flexible customization and stacking via 2 daughter<br />
cards positions per <strong>FPGA</strong><br />
- DINAR1 expansion connector<br />
• Connector: non-proprietary; readily available; cheap<br />
- 72 LVDS pairs + clocks (or 144 single-ended)<br />
- 700 MHz on all signals with source synchronous LVDS<br />
- Signal voltage set by daughter card (+1.2V to +1.8V)<br />
- Reset<br />
- Supplied power rails (fused):<br />
• +12V (24W max), +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using<br />
LVDS (up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- USB, cabled PCIe, Ethernet, JTAG<br />
- Stand-alone configuration with USB stick<br />
- Configuration Error reporting<br />
- Accelerated configuration readback for advanced debug<br />
• RS232 port for embedded <strong>FPGA</strong>-based SOC uP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via<br />
JTAG interface<br />
- ChipScope, Tektronix Veridae<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Enough multicolored LEDs to blind a hamster.<br />
Virtex-7<br />
<strong>FPGA</strong><br />
Speed Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
7V2000T -1,-2 6-input 2,443,200 23,455 14,070 1200 2,160 2,584 46,512 5,814<br />
858 . 454 . 3419 7
DNV7F2A: Twin of Godzilla’s Life Coach<br />
USB 3.0 / 2.0<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
72<br />
3<br />
DINAR1<br />
Expansion Connector<br />
2<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
0<br />
DINAR1<br />
Expansion Connector<br />
72<br />
1<br />
SATA II<br />
(device)<br />
4<br />
72<br />
72<br />
72<br />
72 72<br />
72<br />
2<br />
SATA II<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
10GbE<br />
Ethernet<br />
24<br />
MHz<br />
SMA<br />
JTAG<br />
0<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
G1<br />
Config Clk OSC<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
8<br />
1<br />
1<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
4<br />
G2<br />
<strong>FPGA</strong><br />
1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
RS232<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
Step Clock<br />
Config Clk OSC<br />
GTX<br />
10Gb/s<br />
NMB0<br />
YMB<br />
150<br />
150<br />
16<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
40<br />
NMB1<br />
40<br />
YMB<br />
NMB 1<br />
NMB 2<br />
<strong>FPGA</strong><br />
0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
40<br />
40<br />
SEAF<br />
DNNMB<br />
Connector<br />
(400 pins)<br />
5<br />
5<br />
5<br />
Global<br />
Clocks<br />
4<br />
8<br />
1<br />
4<br />
iPASS<br />
Stacking<br />
PCIe<br />
(GEN2)<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
QSFP+<br />
10GbE<br />
Ethernet<br />
40 GbE or<br />
4, 10 GbE<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G3<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G4<br />
10/100/1000 10/100/1000<br />
baseT<br />
Phy<br />
RJ45<br />
RS232<br />
USB 2.0<br />
(2X)<br />
RGMII<br />
2<br />
USB<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
PCIe<br />
Device Bus<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU<br />
FPU<br />
CPU CPU<br />
OSC<br />
64<br />
3<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
= LVDS when paired, but can be run<br />
single-ended at a reduced frequency<br />
SATA II<br />
(host)<br />
2x<br />
RTC<br />
4-lanes<br />
PCIe (GEN1)<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
8<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
Virtex-7<br />
V<br />
VX<br />
<strong>FPGA</strong><br />
Speed<br />
Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
(1761)<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total (kbits)<br />
Total (kbytes)<br />
7V2000T -1,-2 6-input 2,443,200 23,455 14,070 850 2,160 2,584 46,512 5,814<br />
7V585T -1,-2,-3 6-input 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578<br />
7VX690T -1,-2,-3 6-input 866,400 8,317 4,990 850 3,600 2,940 52,920 6,615<br />
7VX485T -1,-2,-3 6-input 607,200 5,829 3,500 750 2,800 2,060 37,080 4,635<br />
7VX330T -1,-2,-3 6-input 408,000 3,917 2,350 750 1,120 1,500 27,000 3,375<br />
8<br />
www.dinigroup.com
two Virtex-7 <strong>FPGA</strong>s | 7V2000T-1 | 28 million ASIC gates | stackable<br />
Features<br />
• Hosted via<br />
- 4-lane GEN2 PCIe via iPASS cable<br />
- USB2.0<br />
- 10/100/1000BASE-T Ethernet<br />
- Stand alone<br />
• Dual Xilinx Virtex-7 <strong>FPGA</strong>:<br />
- 7V2000T-2,-1 (fastest to slowest)<br />
- 7VX690T-3,-2,-1<br />
• 28+ million ASIC gates (ASIC measure) when<br />
stuffed with two 7V2000T<br />
• GTP low-powered transceivers (assumes -2 speed<br />
grade or faster for 10GbE):<br />
- <strong>FPGA</strong> 0:<br />
• 2 SFP+ sockets<br />
• 4 channels SATA II (device)<br />
• USB3.0<br />
• 2 channels using SMA connectors<br />
• 4-lane PCIe GEN1/GEN2 prototyping via<br />
iPASS cable<br />
• Dual SEARAY GTP Expansion headers,<br />
8-lanes each.<br />
• PCIe,CX4,4 SFP+ sockets or custom<br />
- <strong>FPGA</strong> 1:<br />
• QSFP+ socket<br />
• 4 lanes 10GbE or single lane 40 GbE Ethernet<br />
• 1 SFP+ socket<br />
• 2 channels SATA II (device)<br />
• 4-lane PCIe GEN1/GEN2 prototyping via<br />
iPASS cable<br />
• Dual SEARAY GTP Expansion headers,<br />
8-lanes each<br />
• PCIe,CX4,4 SFP+ sockets, SMA or custom<br />
- Marvel MV78200 Discovery Innovation Dual CPU<br />
• 1 GHz clock<br />
• Dual USB2.0 ports (Type B connector)<br />
• Dual Serial-ATA II connectors for 2 external<br />
hard drives (SATA II)<br />
• Gigabit Ethernet interface<br />
• 10/100/1000 GbE (RJ45 connector)<br />
• Sheeva CPU Core (ARM v5TE compliant)<br />
• Out-of-order execution<br />
• Single and double-precision IEEE compliant<br />
floating point<br />
• DSP instructions boosts performance for signal<br />
processing applications<br />
• MMU to support virtual memory features<br />
• Dual Cache: 32 KB for data and instruction,<br />
parity protected<br />
• L2 cache: 512 KB unified L2 cache per CPU<br />
(total of 1MB), ECC protected.<br />
• 1 GB external DDR2 SDRAM<br />
• Organized in a 128M x 64 configuration<br />
• 400 MHz (800 MHz data rate with DDR)<br />
• RS232 port for terminal-style observation<br />
• After configuration, both CPUs dedicated entirely<br />
to user application<br />
• Linux operating system<br />
• Source and examples provided via GPL license<br />
(no charge)<br />
• ~15 seconds to CPU boot<br />
- Five independent low-skew global clock networks<br />
• G0, G1, G2, G3, G4<br />
• Five, high-resolution, user-programmable syn<br />
thesizers for G0, G1, G2, G3 and G4<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
• User configurable via Marvell uP RS232, USB,<br />
PCIe, or Ethernet<br />
• Global clocks networks distributed differen<br />
tially and balanced<br />
- Flexible customization via 2 daughter cards positions<br />
per <strong>FPGA</strong><br />
• DINAR1 expansion connector<br />
• Connector is non-proprietary, readily available,<br />
and cheap<br />
• 72 LVDS pairs + clocks (or 150 single-ended)<br />
• 700 MHz on all signals with source synchronous<br />
LVDS<br />
• Signal voltage set by daughter card (+1.2V to +1.8V)<br />
• Reset<br />
• Supplied power rails (fused):<br />
• +12V (24W max)<br />
• +3.3V (10W max)<br />
• Pin multiplexing to/from daughter cards using<br />
LVDS (up to 10x)<br />
• Support FMC, logic analyzer, memory expansion<br />
- Fast and Painless <strong>FPGA</strong> configuration<br />
• USB, cabled PCIe, Ethernet, JTAG<br />
• Stand-alone configuration with USB stick<br />
• Configuration Error reporting<br />
• Accelerated configuration readback for advanced<br />
debug<br />
- RS232 port for embedded <strong>FPGA</strong>-based SOC µP debug<br />
• Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
- Full support for embedded logic analyzers via<br />
JTAG interface<br />
• ChipScope, Tektronix Veridae<br />
- Status <strong>FPGA</strong>-controlled LEDs<br />
• Enough multicolored LEDs to illuminate a<br />
medium sized dungeon<br />
858 . 454 . 3419 9
DNV7F1A: Godzilla’s Life Coach<br />
24<br />
MHz<br />
SMA<br />
24<br />
MHz<br />
SMA<br />
24<br />
MHz<br />
SMA<br />
DDR3<br />
IDELAY Refclk<br />
DDR3<br />
Refclk<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
OSC<br />
OSC<br />
G0<br />
G1<br />
G2<br />
RS232<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
10GBE<br />
Ethernet<br />
USB 3.0 / 2.0<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
SFP+ Socket<br />
SFP+ Socket<br />
SFP+ Socket<br />
SFP+ Socket<br />
PCIe<br />
2<br />
1<br />
0<br />
SMA<br />
SATA II<br />
(device)<br />
1<br />
0<br />
GTX Expansion<br />
DNSEAM_NS<br />
NMB<br />
JTAG<br />
OSC<br />
1<br />
1<br />
1<br />
1<br />
8<br />
Config Clk<br />
PCIe<br />
(GEN2)<br />
1<br />
3<br />
4<br />
8<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
iPASS<br />
EEPROM<br />
<strong>FPGA</strong><br />
Virtex-7<br />
7VX690T/7V585T/<br />
7V2000T<br />
[F(F/L/H)G1761]<br />
4<br />
4<br />
DDR3 UDIMM<br />
(16GB Max)<br />
SPI<br />
148<br />
8<br />
LED<br />
(x8)<br />
40<br />
34<br />
72<br />
72<br />
72<br />
72<br />
72<br />
72<br />
0<br />
1<br />
21<br />
DINAR1<br />
Expansion Connector<br />
DINAR1<br />
Expansion Connector<br />
DINAR1<br />
Expansion Connector<br />
Step Clock<br />
10/100/1000 10/100/1000<br />
baseT<br />
Phy<br />
RJ45<br />
RS232<br />
USB 2.0<br />
(2X)<br />
RGMII<br />
2<br />
USB<br />
DMA(4x)<br />
SATA<br />
EEPROM<br />
PCIe<br />
Device Bus<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU<br />
FPU<br />
CPU CPU<br />
OSC<br />
64<br />
3<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
MICTOR<br />
18<br />
40-pin<br />
IDC<br />
(0.1”)<br />
SATA II<br />
(host)<br />
2x<br />
RTC<br />
4-lanes<br />
PCIe (GEN1)<br />
8<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
Features<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
• Hosted via<br />
- 4-lane GEN1/2 PCIe (v1.1) via iPASS cable<br />
- USB2.0<br />
- 10/100/1000BASE-T Ethernet<br />
- Stand alone<br />
• Single Xilinx Virtex-7 <strong>FPGA</strong>:<br />
- 7V2000T-2,-1 (fastest to slowest)<br />
- 7VX690T-3,-2,-1<br />
- 7VX585T-3,-2,-1<br />
- 7VX485T-3,-2,-1<br />
- 7VX330T-3,-2,-1<br />
• 14+ million ASIC gates (ASIC measure) when<br />
stuffed with 7V2000T<br />
• GTP low-powered transceivers (assumes -2 speed<br />
grade or faster for 10GbE):<br />
10<br />
www.dinigroup.com
single Virtex-7 <strong>FPGA</strong> | 7V2000T-1 | 14 million ASIC gates<br />
- 4 SFP+ sockets supports modules for any of the<br />
following interfaces:<br />
• 10 Gigabit Optical Ethernet<br />
• 10GBase-SR 10GBASE-LR 10GBASE-LRM<br />
10GBase-ER<br />
• 10 Gigabit Copper Ethernet<br />
• 10GBASE-R direct attach<br />
• 10 Gigabit Sonet: 10GBase-LW<br />
• 10 Gigabit FibreChannel<br />
- SATA II (device)<br />
- USB3.0<br />
- 2 channels using SMA connectors<br />
- Dual, 4-lane PCIe GEN1/GEN2 prototyping via<br />
iPASS cable<br />
- Dual SEARAY GTP Expansion headers, 8-lanes each<br />
• PCIe<br />
• CX4<br />
• 4 SFP+ sockets<br />
• custom<br />
• 240-pin DDR3 UDIMM<br />
- 72-bit data width (64-bit with 8-bit ECC)<br />
- 800 MHz operation, PC3-12800<br />
- Addressing/power to support 16GB (+ ECC)<br />
- DDR3 Verilog/VHDL reference design provided<br />
(no charge)<br />
- Optional RLDRAM DIMM instead of DDR3 for<br />
ultra low latency<br />
- Alternate pin compatible memory cards available<br />
(consult factory for availability):<br />
• SRAM: QDR, ASYNC, STD, or PSRAM, Flash<br />
• DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2<br />
• Mictor, USB PHY, Extra Interconnect<br />
• Marvel MV78200 Discovery Innovation Dual CPU<br />
- 1 GHz clock<br />
- Dual USB2.0 ports (Type B connector)<br />
- Dual Serial-ATA II connectors for 2 external hard<br />
drives (SATA II)<br />
- Gigabit Ethernet interface<br />
• 10/100/1000 GbE (RJ45 connector)<br />
- Sheeva CPU Core (ARM v5TE compliant)<br />
• Out-of-order execution<br />
• Single and double-precision IEEE compliant<br />
floating point<br />
• 16-bit Thumb instruction set increases code density<br />
• DSP instructions boosts performance for signal<br />
processing applications<br />
• MMU to support virtual memory features<br />
• Dual Cache: 32 KB for data and instruction,<br />
parity protected<br />
Virtex-7<br />
V<br />
VX<br />
<strong>FPGA</strong><br />
Speed<br />
Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Max<br />
(100% util)<br />
(1000's)<br />
• L2 cache: 512 KB unified L2 cache per CPU<br />
(total of 1MB), ECC protected.<br />
- 1 GB external DDR2 SDRAM<br />
• Organized in a 128M x 64 configuration<br />
• 400 MHz (800 MHz data rate with DDR)<br />
- RS232 port for terminal-style observation<br />
- After configuration, both CPUs dedicated entirely<br />
to user application<br />
- Linux operating system<br />
• Source and examples provided via GPL license<br />
(no charge)<br />
• ~15 seconds to CPU boot<br />
• Three independent low-skew global clock networks<br />
- G0, G1, G2<br />
- Three, high-resolution, user-programmable synthesizers<br />
for G0, G1, G2<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
- User configurable via Marvell uP RS232, USB,<br />
PCIe, or Ethernet<br />
- Global clocks networks distributed differentially<br />
and balanced<br />
• Flexible customization via 3 daughter cards positions<br />
- DINARI expansion connector<br />
• Connector is non-proprietary, readily available,<br />
and cheap<br />
- 72 LVDS pairs + clocks (or 150 single-ended)<br />
- 700 MHz on all signals with source synchronous LVDS<br />
- Signal voltage set by daughter card (+1.2V to +1.8V)<br />
- Reset<br />
- Supplied power rails (fused):<br />
• +12V (24W max)<br />
• +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using<br />
LVDS (up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- USB, cabled PCIe, Ethernet, JTAG<br />
- Stand-alone configuration with USB stick<br />
- Configuration Error reporting<br />
- Accelerated configuration readback for advanced debug<br />
• RS232 port for embedded <strong>FPGA</strong>-based SOC µP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via<br />
JTAG interface<br />
- ChipScope, Veridae, and other third-party debug<br />
solutions<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Enough multicolored LEDs to light a fish tank.<br />
Gate Estimate<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
(1761)<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total (kbits)<br />
Total (kbytes)<br />
7V2000T -1,-2 6-input 2,443,200 23,455 14,070 850 2,160 2,584 46,512 5,814<br />
7V585T -1,-2,-3 6-input 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578<br />
7VX690T -1,-2,-3 6-input 866,400 8,317 4,990 850 3,600 2,940 52,920 6,615<br />
7VX485T -1,-2,-3 6-input 607,200 5,829 3,500 750 2,800 2,060 37,080 4,635<br />
7VX330T -1,-2,-3 6-input 408,000 3,917 2,350 750 1,120 1,500 27,000 3,375<br />
858 . 454 . 3419 11
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
Stacking the DNV7F2A<br />
Stacking two DINI Virtex-7 <strong>FPGA</strong> boards<br />
Two boards can be ganged together to increase the amount of available <strong>FPGA</strong> resources.<br />
This example uses the DNV7F2A. In this example, shown in figure 1, two DNV7F2A<br />
cards are ganged together, seamlessly doubling the functionality. A DDR3 memory module<br />
is added to each of the <strong>FPGA</strong> cards.<br />
<strong>The</strong> cable<br />
We use a custom Samtec cable, DINAR1_CBL to connect the signals across the connectors<br />
of the two boards. You get these cables from us. <strong>The</strong> DINAR1_CLB is a high<br />
speed coax cable designed specifically to connect two 400-pin Samtec SEAM connectors<br />
together. Initially these cables are 30”, but eventually we will have several different<br />
lengths.<br />
<strong>The</strong> busses: YMB and NMB<br />
<strong>The</strong> first cable, marked in Figure 1 with as ‘1’, is required. This cable connects the YMB<br />
busses together and adds a bus between the Config <strong>FPGA</strong>s on the two boards. <strong>The</strong> second<br />
bus is used to connect the NMB busses from the slave <strong>FPGA</strong> card to the master <strong>FPGA</strong><br />
card. Full NMB functionality is maintained including DMA data movement between all<br />
<strong>FPGA</strong>s. Also, the host system sees all <strong>FPGA</strong>s as if they were placed on a single circuit<br />
board. <strong>The</strong> data from the NMB busses on the slave card must be re-clocked in the slave’s<br />
Config <strong>FPGA</strong>, so this adds a few clock cycles of latency. <strong>The</strong> raw performance measured<br />
in terms of GB/s is not compromised. <strong>FPGA</strong> and other configuration data of the slave<br />
DNV7F2A is transferred over this second bus. Configuration of the slave <strong>FPGA</strong> board is<br />
also transparent to the host system and software.<br />
<strong>FPGA</strong> to <strong>FPGA</strong> Interconnect between boards<br />
<strong>The</strong> DNV7F2A has 4 expansion connectors, two per <strong>FPGA</strong>. <strong>The</strong>se connectors are yellow<br />
in the block diagram and labeled 0 thru 3. When stacking two DNV7F2As, you can<br />
connect ANY DINAR1 expansion connector to any other DINAR1 Expansion connector<br />
using a DINAR1_CBL. It is perfectly reasonable to connect all four DINAR1 cables between<br />
the two DNV7F2As, but that would leave no expansion position open for memory<br />
or external peripherals. In the example shown in v 1, I connected three of the expansion<br />
connectors together:<br />
<strong>FPGA</strong> 0 DINAR1 3 (master DNV7F2A) → <strong>FPGA</strong> 1 DINAR1 0 (slave)<br />
<strong>FPGA</strong> 1 DINAR1 0 (master DNV7F2A) → <strong>FPGA</strong> 0 DINAR1 1 (slave)<br />
<strong>FPGA</strong> 1 DINAR1 2 (master DNV7F2A) → <strong>FPGA</strong> 0 DINAR1 3 (slave)<br />
I choose these connections because it was easy to draw and not for any practical reason.<br />
Each of these cables carries 72 LVDS pairs, along with clocks, IDs and resets. I will state<br />
again: You can connect ANY DINAR1 connector to any other DINAR1 connector. Note<br />
that if you want to increase the interconnect between the <strong>FPGA</strong>s on a stand-alone DN-<br />
V7F2A, you would not use the DINAR1_CBL. Use the DINAR1_INTERCON instead.<br />
DDR3 Memory<br />
I added a DINAR1_SODM204 to the spare DINAR1 connector on each DNV7F2A. This<br />
card hosts a 204-pin SODIMM memory module. In the block diagram, I put an 8 GB<br />
DDR3 memory module in the socket. You aren’t limited to DDR3. We have several other<br />
SODIMMs that work fine in this slot:<br />
• DNSODM204_SSRAM (1.8V version) (SSRAM)<br />
• DNSODM204_QUADMIC (4 Mictor connectors)<br />
• DNSODM204_SE (Flash and Mobile SDRAM)<br />
• DNSODM204_USB (USB2.0 Phy)<br />
• DNSODM204_DDR2_FAST (DDR2)<br />
• DNSODM204_QDRII+ (QDRII+ SSRAM)<br />
• DNSODM204_DDR2_2GB (more DDR2, larger)<br />
• DNSODM204_MICTOR_IO (2 Mictors)<br />
Overview<br />
Figure 2 shows the final functionality of the two DNV7F2As as seen from the host.<br />
12<br />
www.dinigroup.com<br />
DINAR1_CABLE<br />
24<br />
MHz<br />
24<br />
MHz<br />
YMB + NMB<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
G3<br />
40 GbE or<br />
4, 10 GbE<br />
10GbE<br />
Ethernet<br />
24<br />
MHz<br />
24<br />
MHz<br />
Figure 1<br />
10GbE<br />
Ethernet<br />
USB 3.0 / 2.0<br />
SATA II<br />
(device)<br />
JTAG<br />
SATA II<br />
0<br />
1<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
QSFP+<br />
SFP+ Socket<br />
DNSEAM_NS<br />
GTX Expansion<br />
G1<br />
G4<br />
2<br />
4<br />
5<br />
6<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
24<br />
MHz<br />
1<br />
Config Clk<br />
DINAR1_SODM204<br />
DINAR1_SODM204<br />
10/100/1000<br />
baseT<br />
USB 2.0<br />
(2X)<br />
Stacking<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
4<br />
DINAR1<br />
Expansion Connector<br />
OSC<br />
114.285 MHz<br />
1<br />
8<br />
8<br />
1<br />
1<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
4<br />
RJ45<br />
RS232<br />
SATA II<br />
(host)<br />
2x<br />
Global<br />
Clocks<br />
72<br />
72<br />
DINAR1<br />
Expansion Connector<br />
DDR 3<br />
DDR 3<br />
72<br />
72<br />
4<br />
G2<br />
3<br />
10/100/1000<br />
Phy<br />
6Mb<br />
FLASH<br />
oot<br />
8Mb<br />
SPI<br />
FLASH<br />
x 64<br />
DR2<br />
5<br />
5<br />
5<br />
DNNMB<br />
onnector<br />
400 pins)<br />
T<br />
T<br />
761]<br />
A<br />
0<br />
r<br />
Ex<br />
FP<br />
7V<br />
7V<br />
[F(F/H<br />
GEN1<br />
Step Clo<br />
RGM<br />
2<br />
R
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
four Virtex-7 <strong>FPGA</strong>s | 7V2000T-1 | 56 million ASIC gates<br />
Memory / Expansion / Stacking<br />
Memory / Expansion / Stacking<br />
DINAR1<br />
Expansion Connector<br />
3<br />
DINAR1<br />
Expansion Connector<br />
2<br />
DINAR1<br />
Expansion Connector<br />
0<br />
DINAR1<br />
Expansion Connector<br />
1<br />
USB 3.0 / 2.0<br />
72<br />
72<br />
SATA II<br />
(device)<br />
4<br />
72<br />
72<br />
72<br />
72 72<br />
72<br />
2<br />
SATA II<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
10GbE<br />
Ethernet<br />
24<br />
MHz<br />
JTAG<br />
0<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
G1<br />
24<br />
MHz<br />
Config Clk OSC<br />
8<br />
1<br />
1<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
4<br />
G2<br />
<strong>FPGA</strong><br />
1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
Step Clock<br />
RS232<br />
Config Clk OSC<br />
GTX<br />
10Gb/s<br />
NMB0<br />
YMB<br />
150<br />
150<br />
16<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
40<br />
NMB1<br />
40<br />
YMB<br />
NMB 1<br />
NMB 2<br />
40<br />
40<br />
<strong>FPGA</strong><br />
0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
SEAF<br />
DNNMB<br />
Connector<br />
(400 pins)<br />
5<br />
5<br />
5<br />
Global<br />
Clocks<br />
8<br />
1<br />
4<br />
4<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
Stacking<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
QSFP+<br />
10GbE<br />
Ethernet<br />
40 GbE or<br />
4, 10 GbE<br />
25<br />
NAND<br />
B<br />
Boot<br />
128M<br />
D<br />
12<br />
8<br />
3<br />
64<br />
OSC<br />
CPU<br />
4-lanes<br />
PCIe (GEN1)<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
CPU<br />
FPU FPU<br />
Device Bus<br />
PCIe<br />
Marvell MV78200<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
RTC<br />
USB<br />
2<br />
RGMII<br />
Step Clock<br />
10/100/1000<br />
Phy<br />
SATA II<br />
(host)<br />
2x<br />
RS232<br />
RJ45<br />
USB 2.0<br />
(2X)<br />
10/100/1000<br />
baseT<br />
G4<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
24<br />
MHz<br />
G3<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
24<br />
MHz<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G3<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
= LVDS when paired, but can be run<br />
single-ended at a reduced frequency<br />
G4<br />
10/100/1000<br />
baseT<br />
RJ45<br />
USB 2.0<br />
(2X)<br />
RS232<br />
SATA II<br />
(host)<br />
2x<br />
10/100/1000<br />
Phy<br />
RGMII<br />
2<br />
USB<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
RTC<br />
PCIe<br />
Device Bus<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU FPU<br />
CPU CPU<br />
4-lanes<br />
PCIe (GEN1)<br />
OSC<br />
64<br />
3<br />
8<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
40<br />
40<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
Config Clk<br />
OSC<br />
NMB0<br />
GTX<br />
10Gb/s<br />
YMB<br />
NMB1<br />
YMB<br />
SEAF<br />
JTAG<br />
RS232<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
Config Clk<br />
OSC<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
NMB 1<br />
40<br />
150<br />
16<br />
150<br />
USB 3.0 / 2.0<br />
SATA II<br />
(device)<br />
10GbE<br />
Ethernet<br />
FPG<br />
0<br />
7VX690<br />
7V2000<br />
[F(F/H)G1<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
24<br />
MHz<br />
0<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G1<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G2<br />
NMB 2<br />
C<br />
(<br />
1<br />
72 72<br />
DINAR1<br />
Expansion Connecto<br />
4<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
40<br />
8<br />
1<br />
72<br />
4<br />
72<br />
DINAR1<br />
Expansion Connector<br />
<strong>FPGA</strong><br />
1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
72<br />
72<br />
2<br />
DINAR1<br />
Expansion Connector<br />
3<br />
<strong>FPGA</strong> to <strong>FPGA</strong><br />
Interconnect<br />
DINAR1_CABLE<br />
2 3 4<br />
<strong>FPGA</strong> to <strong>FPGA</strong><br />
Interconnect<br />
DINAR1_CABLE<br />
<strong>FPGA</strong> to <strong>FPGA</strong><br />
Interconnect<br />
DINAR1_CABLE<br />
SLAVE<br />
DINAR1<br />
pansion Connector<br />
2<br />
DINAR1<br />
Expansion Connector<br />
0<br />
DINAR1<br />
Expansion Connector<br />
1<br />
72<br />
GA<br />
1<br />
X690T<br />
2000T<br />
)G1761]<br />
PCIe<br />
(Cabled<br />
/GEN2)<br />
Config Clk OSC<br />
II<br />
S232<br />
ck<br />
72<br />
USB<br />
72<br />
EEPROM<br />
DMA(4x)<br />
SATA<br />
RTC<br />
GTX<br />
10Gb/s<br />
NMB0<br />
PCIe<br />
Device Bus<br />
YMB<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCI EXPRESS<br />
Cable (GEN1)<br />
150<br />
150<br />
16<br />
40<br />
PCIe<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
4-lanes<br />
PCIe (GEN1)<br />
NMB1<br />
40<br />
YMB<br />
Marvell MV78200<br />
FPU FPU<br />
CPU CPU<br />
NMB 1<br />
NMB 2<br />
72 72<br />
40<br />
40<br />
OSC<br />
<strong>FPGA</strong><br />
0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
64<br />
3<br />
8<br />
SEAF<br />
DNNMB<br />
Connector<br />
(400 pins)<br />
5<br />
5<br />
5<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
72<br />
Global<br />
Clocks<br />
8<br />
1<br />
4<br />
4<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
Stacking<br />
2<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
QSFP+<br />
SATA II<br />
10GbE<br />
Ethernet<br />
40 GbE or<br />
4, 10 GbE<br />
MASTER<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
40 GbE or<br />
4, 10 GbE<br />
10GbE<br />
Ethernet<br />
10GbE<br />
Ethernet<br />
24<br />
MHz<br />
JTAG<br />
SATA II<br />
USB 3.0 / 2.0<br />
SATA II<br />
(device)<br />
0<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
QSFP+<br />
SFP+ Socket<br />
DNSEAM_NS<br />
GTX Expansion<br />
G1<br />
2<br />
4<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
24<br />
MHz<br />
Config Clk<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
4<br />
OSC<br />
1<br />
8<br />
8<br />
1<br />
1<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
4<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
4<br />
G2<br />
<strong>FPGA</strong><br />
S0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
PCIe<br />
(Cabled<br />
GEN1/GEN2)<br />
4GB SODIMM<br />
<strong>FPGA</strong><br />
M1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
RS232<br />
Config Clk<br />
OSC<br />
16<br />
40<br />
SNMB1<br />
YMB<br />
NMB0<br />
GTX<br />
10Gb/s<br />
NMB1<br />
150<br />
150<br />
40 40<br />
YMB<br />
NMB0<br />
72 72<br />
144 144<br />
DDR 3<br />
SNMB0<br />
150<br />
150<br />
GTX<br />
10Gb/s<br />
NMB1<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
PCIe<br />
YMB<br />
16<br />
40<br />
<strong>FPGA</strong><br />
S1<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
4GB SODIMM<br />
DDR 3<br />
<strong>FPGA</strong><br />
M0<br />
7VX690T<br />
7V2000T<br />
[F(F/H)G1761]<br />
4<br />
PCIe<br />
(GEN2)<br />
iPASS<br />
4<br />
1<br />
1<br />
8<br />
8<br />
1<br />
OSC<br />
4<br />
iPASS<br />
PCIe<br />
(GEN2)<br />
Config Clk<br />
SFP+ Socket<br />
DNSEAM_NS<br />
GTX Expansion<br />
4<br />
2<br />
GTX Expansion<br />
DNSEAM_NS<br />
SFP+ Socket<br />
QSFP+<br />
SATA II<br />
(device)<br />
USB 3.0 / 2.0<br />
SATA II<br />
10GbE<br />
Ethernet<br />
10GbE<br />
Ethernet<br />
40 GbE or<br />
4, 10 GbE<br />
SLAVE<br />
SMA<br />
SMA<br />
SMA<br />
Step Clock<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G3<br />
24<br />
MHz<br />
SMA<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G4<br />
10/100/1000<br />
baseT<br />
RJ45<br />
USB 2.0<br />
(2X)<br />
RS232<br />
10/100/1000<br />
Phy<br />
RGMII<br />
2<br />
USB<br />
EEPROM<br />
PCIe OSC<br />
(Gen1)<br />
4 - lanes<br />
Device Bus<br />
Marvell MV78200 64<br />
FPU FPU<br />
DMA(4x)<br />
CPU CPU 3<br />
SATA PCIe<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
= LVDS when paired, but can be run<br />
single-ended at a reduced frequency<br />
Figure 2<br />
SATA II<br />
(host)<br />
2x<br />
RTC<br />
PCI EXPRESS<br />
Cable (GEN1)<br />
4-lanes<br />
PCIe (GEN1)<br />
8<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
MASTER<br />
858 . 454 . 3419 13
DNS5GX_F2: Monster’s Evil Interior Decorator<br />
DC0<br />
MEG Array Expansion<br />
connector (400-pin)<br />
180<br />
unidirectional LVDs when paired.<br />
Can be used single-ended at<br />
reduced frequencies.<br />
DC1<br />
MEG Array Expansion<br />
connector (400-pin)<br />
180<br />
NMB0<br />
40<br />
DDR3 SODIMM<br />
(4GB Max)<br />
140<br />
<strong>FPGA</strong><br />
0<br />
Stratix-5<br />
5SGXA5, A7, A9, AB<br />
5SGSD6, D8<br />
(F1932)<br />
96<br />
96<br />
96<br />
96<br />
<strong>FPGA</strong><br />
1<br />
Stratix-5<br />
5SGXA5, A7, A9, AB<br />
5SGSD6, D8<br />
(F1932)<br />
140<br />
DDR3 SODIMM<br />
(4GB Max)<br />
iPASS<br />
NMB1<br />
40<br />
14.1 GHz XCVR<br />
24<br />
OOB<br />
32<br />
14.1 GHz XCVR<br />
OOB<br />
24 32<br />
14.1 GHz XCVR<br />
OOB<br />
24 32<br />
14.1 GHz XCVR<br />
OOB<br />
24 32<br />
PCIe<br />
Cable<br />
(GEN 2)<br />
Expansion<br />
Header<br />
4<br />
segm<br />
8<br />
GTX<br />
<strong>FPGA</strong><br />
Config<br />
Stratix-5<br />
5SGXA3, A4, A5,<br />
A7, 5SGSD5, D6, D8<br />
(F1517)<br />
8<br />
GTX<br />
Expansion<br />
Header<br />
IOB0<br />
IOB1<br />
IOB2<br />
IOB3<br />
segm<br />
10/100/1000 10/100/1000<br />
baseT<br />
Phy<br />
RJ45<br />
RS232<br />
USB<br />
2.0<br />
(2x)<br />
SATA II<br />
(host)<br />
2x<br />
RGMII<br />
USB<br />
DMA(4x)<br />
SATA<br />
RTC<br />
MPP Bus<br />
PCIe<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
FPU<br />
CPU CPU<br />
4-lanes<br />
PCIe (GEN1)<br />
FPU<br />
OSC<br />
64<br />
3<br />
8<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
IOB Options (each position):<br />
100 Gigabit Ethernet (via CFP)<br />
40 Gigabit Ethernet (via CFP)<br />
Quad QSFP+ (10 GbE)<br />
Octal SFP+ (10GbE)<br />
GEN1 / GEN2 / GEN 3 PCIe<br />
USB3<br />
SMAs<br />
iPASS<br />
14<br />
www.dinigroup.com<br />
PCI Express Cable<br />
(GEN 1)<br />
Features<br />
• Cabled PCIe-hosted logic prototyping system<br />
- 2 - Altera Stratix V <strong>FPGA</strong>s<br />
• 5SGXAB,A9,A7,A5 (largest to smallest)<br />
-for logic prototyping<br />
• 5SGSD8,D6<br />
-for signal processing<br />
- 100% <strong>FPGA</strong> resources available for user application<br />
• 16.6M+ ASIC gates (reasonable ASIC measure) with<br />
two 5SGXAB<br />
- 7,852 - 18x18 multipliers with dual 5SGSD8 (8M<br />
gates of logic)<br />
• 4 configurable high speed serial interface card slots<br />
(IOB), 2 per <strong>FPGA</strong><br />
- 12 - 14.1 GHz serial links per slot<br />
- 32 - general purpose I/O for out of band signaling (OOB)<br />
- Options interfaces include:<br />
• 100 GbE Ethernet (via CFP module)<br />
• 40 GbE Ethernet, Quad QSFP+, Octal SFP+<br />
• GEN1/GEN2 PCIe, USB3, SMAs
dual Altera Stratix V <strong>FPGA</strong>s | 5SGXAB | 16.5 million ASIC gates<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is single-ended or LVDS<br />
- 700 MHz LVDS chip-to-chip DDR with -2 speed<br />
grade (1.4 Gb/s)<br />
- Reference designs for integrated I/O pad shift registers<br />
• 10x <strong>FPGA</strong> to <strong>FPGA</strong> pin multiplexing per<br />
LVDS pair<br />
• Greatly simplified logic partitioning<br />
• Source synchronous clocking for LVDS<br />
• 2 separate DDR3 SODIMMs, PC3-8500<br />
- 64-bit data with addressing/power to support 4GB<br />
- DDR3 Verilog reference design provided (no charge)<br />
• VHDL on special request<br />
• Marvel MV78200 Discovery Innovation Dual CPU<br />
- 1 GHz clock<br />
- Dual USB2.0 ports (Type B connector)<br />
- Dual Serial-ATA II connectors for 2 external hard<br />
drives (SATA II)<br />
- Gigabit Ethernet interface<br />
• 10/100/1000 GbE (RJ45 connector)<br />
- Sheeva CPU Core (ARM v5TE compliant)<br />
• Out-of-order execution<br />
• Single and double-precision IEEE compliant<br />
floating point<br />
• 16-bit Thumb instruction set increases code density<br />
• DSP instructions boosts performance for signal<br />
processing applications<br />
• MMU to support virtual memory features<br />
• Dual Cache: 32 KB for data and instruction,<br />
parity protected<br />
• L2 cache: 512 KB unified L2 cache per CPU<br />
(total of 1MB), ECC protected.<br />
- 1 GB external DDR2 SDRAM<br />
• Organized in a 128M x 64 configuration<br />
• 400 MHz (800 MHz data rate with DDR)<br />
- RS232 port for terminal-style observation<br />
- After configuration, both CPUs dedicated entirely<br />
to user application<br />
- Linux operating system<br />
• Source and examples provided via GPL license<br />
(no charge)<br />
• ~15 seconds to CPU boot<br />
• 3 board-level global clock networks (GCLK[2:0])<br />
- Separate programmable synthesizers for each<br />
network (Si5326)<br />
• Ultra-low jitter<br />
• 2 kHz - 710 MHz<br />
• User configurable via USB, PCIe, et al.<br />
- Alternate clock sources:<br />
• Config <strong>FPGA</strong><br />
-single-step, divide<br />
• SMA for external clock insertion<br />
- 2 Daughter Card global clock networks<br />
• Allows insertion of global clock from daughter card<br />
• 2x 400-pin MEG-Array connectors for daughter<br />
card expansion<br />
- 180 signals<br />
- 700MHz on all signals with source synchronous LVDS<br />
- Reset, presence detect<br />
- Supplied power rails (fused):<br />
• +12V (24W max), +5V (10W max), +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards with<br />
LVDS (up to 10x)<br />
• Auspy AES models for partitioning assistance<br />
- Hooks and models for other third-party<br />
partitioning solutions<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- USB, PCIe, Ethernet et al.<br />
- Integrated sanity checks on configuration files<br />
• Custom base plate (standard) and optional rackmount<br />
chassis<br />
- Provides protection from those drooling engineers<br />
• Full support for embedded logic analyzers via<br />
JTAG interface<br />
- SignalTap, Veridae, and other third party debug tools<br />
• Convert MEG-Array expansion connectors to<br />
interconnect with the DNMEG_Intercon.<br />
• Enough status LEDs to function as a bathroom nightlight<br />
Stratix-5<br />
GS GX<br />
<strong>FPGA</strong><br />
Gate Estimate<br />
Memory<br />
Speed Grades<br />
LUT<br />
Max Practical<br />
(slowest to<br />
FF's<br />
Size<br />
MLAB M20K Total Total<br />
(100% util) (60% util)<br />
fastest)<br />
(1000's) (1000's)<br />
(640) (20 kbit) (kbits) (kbytes)<br />
5SGXAB -4,-3,-2 6-input 1,437,000 13,795 8,280 840 704 17960 2,640 52,800 6,600<br />
5SGXA9 -4,-3,-2 6-input 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600<br />
5SGXA7 -4,-3,-2 6-input 939,000 9,014 5,410 840 512 11736 2,560 51,200 6,400<br />
5SGXA5 -4,-3,-2 6-input 740,000 7,104 4,260 840 512 8020 2,304 46,080 5,760<br />
5SGXA4 -4,-3,-2 6-input 634,000 6,086 3,650 696 512 5880 1,900 38,000 4,750<br />
5SGXA3 -4,-3,-2 6-input 513,000 4,925 2,960 696 512 3776 957 19,140 2,393<br />
5SGSD8 -4,-3,-2 6-input 1,050,000 10,080 6,050 840 3926 2624 2,567 51,340 6,418<br />
5SGSD6 -4,-3,-2 6-input 880,000 8,448 5,070 480 3550 2320 2,320 46,400 5,800<br />
5SGSD5 -4,-3,-2 6-input 690,000 6,624 3,970 696 3180 2014 3,180 63,600 7,950<br />
Max I/O's<br />
Multiplier<br />
s (18x18)<br />
858 . 454 . 3419 15
DNPCIe_10G_K7_LL<br />
Xilinx Kintex-7<br />
Son of Godzilla’s Bad Hair Day<br />
PC3-10600<br />
DDR3 DIMM<br />
(512M x 72)<br />
123<br />
10GBASE-ER<br />
10 GBASE-SR<br />
10GBASE-KR<br />
Fiber:<br />
COPPER:<br />
10GbE SFP+<br />
10GbE SFP+<br />
GPS<br />
<strong>FPGA</strong><br />
Xilinx<br />
Kintex-7<br />
7K325T / 7K410T<br />
(FFG 676)<br />
control<br />
18<br />
QDRII+<br />
SRAM<br />
(4Mx18)<br />
D in D Out<br />
FLASH<br />
(1Gbit)<br />
18<br />
Time Sync<br />
4<br />
Cost Effective<br />
Low Latency<br />
Networking!<br />
4-Lane PCIe<br />
GEN1 / GEN2<br />
4-lane electrical<br />
16-lane mechanical<br />
16<br />
www.dinigroup.com
single Xilinx Kintex-7 <strong>FPGA</strong> | QDRII+ and DDR3<br />
Features<br />
• 2 separate 10GbE LAN/WAN using SFP+ modules<br />
- Customized IP for packet analysis with minimum latency<br />
• Hosted in a 4-lane GEN1 or GEN2 PCIe slot<br />
- 16-lane mechanical<br />
- Low profile, short length form factor<br />
• Fully compatible with our TCP Offload Engine (TOE)<br />
• FIX board support package (DN_FBSP). Functioning reference design with:<br />
- 10-Gigabit Ethernet MAC<br />
- TCP/IP Offload Engine (TOE)<br />
- FIX protocol parser<br />
- Tick Filter (optional)<br />
- PCIe Interface (4-lane, GEN2)<br />
- Memory<br />
• QDR2 II+ Controller<br />
• DDR3 Controller<br />
• Xilinx Kintex-7 <strong>FPGA</strong> (FFG676) :<br />
- 7K410T-3,-2,-2L (fastest to slowest)<br />
- 7K325T-3,-2,-2L<br />
- 3M ASIC gates (ASIC measure) when stuffed with Kintex-7 7K410T<br />
• 254k flip-flop/6-input LUTs (708k total FFs)<br />
• 3.578 Kbytes total <strong>FPGA</strong> block memory (1590, 18 kbit blocks)<br />
• 1540, 25x18 multipliers<br />
• Bulk memory: DDR3 Mini-uDIMM<br />
- 72-bit data width (64-bit with 8-bit ECC)<br />
- 666.5MHz operation, PC3-10600 (single rank)<br />
- Addressing/power to support 4GB<br />
- DDR3 Verilog/VHDL reference design provided (no charge)<br />
• Optimized DDR3 controller for lowest latency bulk memory access<br />
- Optional RLDRAM Mini-DIMM instead of DDR3 for ultra low latency<br />
• QDRII+ SRAM memory: 2M x 18 (72Mb)<br />
- Separate 18-bit read and write ports<br />
- 500 MHz bus operation, DDR (double data rate)<br />
• Fast enough to be clocked at 312.50 MHz<br />
• Eliminates clock synchronization delays between memory and Ethernet clock<br />
• SMBus-based thermal management<br />
• GPS input for precise message time stamping and tracking<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope and other third-party debug solutions:<br />
• Veridae, SpringSoft<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Enough light to make your houseplants happy<br />
Kintex-7<br />
<strong>FPGA</strong><br />
Speed Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
7K410T -1,-2,-3 6-input 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578<br />
7K325T -1,-2,-3 6-input 407,600 3,913 2,350 500 840 890 16,020 2,003<br />
7K160T -1,-2,-3 6-input 202,800 1,947 1,170 400 600 650 11,700 1,463<br />
858 . 454 . 3419 17
DNPCIe_10G_K7_LL_QSFP Xilinx Kintex-7<br />
Daughter of Godzilla’s Bad Hair Day<br />
PC3-10600<br />
DDR3 VLP Mini-uDIMM<br />
(512M x 64)<br />
4x 10GbE<br />
or<br />
1x 40GbE<br />
USB 2.0<br />
QSFP+<br />
GPS<br />
Time Sync<br />
GTX 4<br />
2<br />
RS232<br />
GTX<br />
<strong>FPGA</strong><br />
Xilinx<br />
7K325T / 7K410T<br />
(FFG 676)<br />
control<br />
18<br />
QDRII+<br />
SRAM<br />
(4Mx18)<br />
D in D Out<br />
FLASH<br />
(1Gbit)<br />
18<br />
(Type B)<br />
USB<br />
JTAG / UART<br />
<strong>FPGA</strong><br />
LED<br />
(X8)<br />
JTAG<br />
( +1.8V)<br />
QDRII+<br />
CPLD<br />
4-Lane PCIe<br />
GEN1 / GEN2 / GEN3<br />
4-lane electrical<br />
16-lane mechanical<br />
18<br />
www.dinigroup.com
single Xilinx Kintex-7 <strong>FPGA</strong> | QDRII+ and DDR3 | QSFP+<br />
Features<br />
• QSFP+ socket<br />
- 4 ports 10GbE LAN/WAN using SFP+ modules OR<br />
- 1 port 40 GbE<br />
• Hosted in a 4-lane GEN1/GEN2/GEN3 PCIe slot<br />
- 16-lane mechanical<br />
- Low profile, short length form factor<br />
- GEN1/GEN2 PCIe bridge provided<br />
• GEN3 supplied by user<br />
• Fully compatible with our TCP Offload Engine (TOE)<br />
• FIX board support package (DN_FBSP). Functioning reference design with:<br />
- 10-Gigabit Ethernet MAC and 40 GbE MAC<br />
- TCP/IP Offload Engine (TOE)<br />
- FIX protocol parser<br />
- Tick Filter (optional)<br />
- PCIe Interface (4-lane, GEN2)<br />
- Memory<br />
• QDR2 II+ Controller<br />
• DDR3 Controller<br />
• Xilinx Kintex-7 <strong>FPGA</strong> (FFG676) :<br />
- 7K410T-3,-2,-2L (fastest to slowest)<br />
- 7K325T-3,-2,-2L<br />
- 3M ASIC gates (ASIC measure) when stuffed with Kintex-7 7K410T<br />
• 254k flip-flop/6-input LUTs (708k total FFs)<br />
• 3.578 Kbytes total <strong>FPGA</strong> block memory (1590, 18 kbit blocks)<br />
• 1540, 25x18 multipliers<br />
• Bulk memory: DDR3 VLP Mini-uDIMM<br />
- 72-bit data width (64-bit with 8-bit ECC)<br />
- 666.5MHz operation, PC3-10600 (single rank)<br />
- Addressing/power to support 4GB<br />
- DDR3 interface compatible with Vivado MIG<br />
• Optimized DDR3 controller for lowest latency bulk memory access<br />
- Optional RLDRAM Mini-UDIMM instead of DDR3 for ultra low latency<br />
• QDRII+ SRAM memory: 4M x 18 (72Mb)<br />
- Separate 18-bit read and write ports<br />
- 500 MHz bus operation, DDR (double data rate)<br />
• Fast enough to be clocked at 312.50 MHz<br />
• Eliminates clock synchronization delays between memory and Ethernet clock<br />
• SMBus-based thermal management<br />
• GPS input for precise message time stamping and tracking<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope and other third-party debug solutions:<br />
• Tektronix Certus<br />
• Eight <strong>FPGA</strong>-controlled LEDs<br />
- Enough light to make your houseplants happy<br />
Kintex-7<br />
<strong>FPGA</strong><br />
Speed Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
7K410T -1,-2,-3 6-input 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578<br />
7K325T -1,-2,-3 6-input 407,600 3,913 2,350 500 840 890 16,020 2,003<br />
7K160T -1,-2,-3 6-input 202,800 1,947 1,170 400 600 650 11,700 1,463<br />
858 . 454 . 3419 19
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
LED<br />
(x4)<br />
Config PROM<br />
Frequency<br />
Synths (Si5326)<br />
Frequency<br />
Synths (Si5326)<br />
Frequency<br />
Synths (Si5326)<br />
COMPACT FLASH<br />
<strong>FPGA</strong><br />
CONFIGURATION<br />
Stratix IV<br />
DN7020K10<br />
+1.5V to +3.3V I/O<br />
DC0<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
DIMM_F1<br />
DDR2 SODIMM<br />
(4GB max)<br />
DIMM_F2<br />
DDR2 SODIMM<br />
(4GB max)<br />
DIMM_F3<br />
DDR2 SODIMM<br />
(4GB max)<br />
+1.5V to +3.3V I/O<br />
DC2<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
MICTOR<br />
Boot<br />
EPROM<br />
RS232<br />
serial<br />
port<br />
SMA<br />
SMA<br />
SMA<br />
SMA<br />
12<br />
12<br />
12<br />
62 24 61<br />
190 120 120 120 190<br />
SPI Flash<br />
SPI Flash<br />
SPI Flash<br />
(16Mb)<br />
(16Mb)<br />
(16Mb)<br />
Stratix IV<br />
50 Stratix IV<br />
51 Stratix IV<br />
50 Stratix IV<br />
50 Stratix IV<br />
<strong>FPGA</strong> F0 <strong>FPGA</strong> F1 <strong>FPGA</strong> F2 <strong>FPGA</strong> F3 <strong>FPGA</strong> F4<br />
50<br />
4SE820<br />
4SE820<br />
62 24 61<br />
62 24 61<br />
62 24 61<br />
184<br />
188<br />
186<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
46 50<br />
44 51<br />
46 50<br />
46<br />
4SE820<br />
4SE820<br />
4SE820<br />
50<br />
51<br />
50<br />
50<br />
51<br />
50<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
138<br />
140<br />
138<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
38<br />
39<br />
38<br />
38<br />
<strong>FPGA</strong> F5 <strong>FPGA</strong> F6 <strong>FPGA</strong> F7 <strong>FPGA</strong> F8 <strong>FPGA</strong> F9<br />
38<br />
39<br />
38<br />
38<br />
4SE820<br />
4SE820<br />
4SE820<br />
4SE820<br />
4SE820<br />
38<br />
48<br />
48<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
Stratix IV<br />
<strong>FPGA</strong> F10<br />
38<br />
<strong>FPGA</strong> F11<br />
39<br />
<strong>FPGA</strong> F12<br />
38<br />
<strong>FPGA</strong> F13<br />
37<br />
<strong>FPGA</strong> F14<br />
38<br />
39<br />
38<br />
36<br />
4SE820<br />
4SE820<br />
4SE820<br />
4SE820<br />
4SE820<br />
38<br />
48<br />
48<br />
Stratix IV<br />
50 Stratix IV<br />
50<br />
<strong>FPGA</strong> F15 <strong>FPGA</strong> F16 <strong>FPGA</strong> F17 <strong>FPGA</strong> F18 <strong>FPGA</strong> F19<br />
4SE820<br />
4SE820<br />
40 50<br />
40 40 46<br />
Stratix IV<br />
51 Stratix IV<br />
51 Stratix IV<br />
51<br />
51<br />
51<br />
51 4SE820<br />
51 4SE820<br />
51 4SE820<br />
SPI Flash<br />
(16Mb)<br />
38<br />
38<br />
50<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
39<br />
39<br />
SPI Flash<br />
(16Mb)<br />
39<br />
39<br />
51<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
138<br />
140<br />
138<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
38<br />
38<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
SPI Flash<br />
(16Mb)<br />
38<br />
38<br />
51<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
24 23 24<br />
140<br />
140<br />
138<br />
48<br />
48<br />
48<br />
48<br />
48<br />
48<br />
50<br />
50<br />
38<br />
36<br />
50<br />
48<br />
48<br />
38<br />
48<br />
48<br />
37<br />
48<br />
48<br />
50<br />
21 21 21<br />
21 21 21<br />
21 21 21<br />
21 21 21<br />
MBUS48B<br />
180<br />
184<br />
180<br />
Bus<br />
Switch<br />
47<br />
47<br />
48<br />
48<br />
Bus<br />
Switch<br />
47<br />
47<br />
48<br />
48<br />
Bus<br />
Switch<br />
47<br />
47<br />
48<br />
48<br />
47<br />
47<br />
48<br />
48<br />
Bus<br />
Switch<br />
DC3<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
DC4<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
DC5<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
DC6<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O<br />
34<br />
Main Bus<br />
Connector<br />
SMA<br />
SMA<br />
F4<br />
40<br />
40<br />
MICTOR<br />
MBUS48A<br />
MBUS48B<br />
MBCLK<br />
GCLK0<br />
(to all <strong>FPGA</strong>’s)<br />
GCLK1<br />
(to all <strong>FPGA</strong>’s)<br />
GCLK2<br />
(to all <strong>FPGA</strong>’s)<br />
DCGCLK0<br />
(to all <strong>FPGA</strong>’s)<br />
CY7C68013<br />
uP Configuration<br />
controller<br />
SRAM<br />
128Kb x 8<br />
Flash<br />
1 M x 8<br />
Config<br />
<strong>FPGA</strong><br />
48 MHz<br />
8<br />
LCD<br />
Control<br />
Panel<br />
USB 2.0<br />
(type b)<br />
RS232<br />
Reset<br />
96<br />
96<br />
SMA<br />
C<strong>FPGA</strong> Div Clk<br />
C<strong>FPGA</strong> Step Clk<br />
<strong>FPGA</strong> F19<br />
SMA<br />
C<strong>FPGA</strong> Div Clk<br />
C<strong>FPGA</strong> Step Clk<br />
<strong>FPGA</strong> F19<br />
SMA<br />
C<strong>FPGA</strong> Div Clk<br />
C<strong>FPGA</strong> Step Clk<br />
<strong>FPGA</strong> F19<br />
G0 Si5326<br />
<strong>FPGA</strong> F1<br />
4 Serial<br />
Ports<br />
(Tx/Rx)<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
SMA<br />
PLL<br />
DC10<br />
SMA<br />
DC0<br />
DC3<br />
+1.5V to +3.3V I/O<br />
Features<br />
20<br />
JTAG<br />
www.dinigroup.com<br />
0<br />
5<br />
1<br />
6<br />
2<br />
7<br />
10 11 12 13 14<br />
15<br />
16<br />
17<br />
3<br />
8<br />
18<br />
4<br />
9<br />
19<br />
190 120 120 48<br />
DC1<br />
DIMM F16<br />
DIMM F17<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
• USB2.0-hosted logic prototyping system<br />
with 2-20 Altera Stratix IV <strong>FPGA</strong>s<br />
- Stratix IV 4SE530 or 4SE820 in high I/O<br />
package (FF1760)<br />
- Backwards compatible with the Stratix-3,<br />
3SL340<br />
- 100% <strong>FPGA</strong> resources available for user application<br />
• 130M+ ASIC gates (reasonable ASIC<br />
measure) with twenty 4SE820s<br />
- 82M+ with twenty 4SE530s<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is single-ended or LVDS<br />
- 600 MHz LVDS chip-to-chip DDR (1.2 Gb/s)<br />
- Reference designs for integrated I/O pad<br />
ISERDES/OSERDES<br />
• 10x <strong>FPGA</strong> to <strong>FPGA</strong> pin multiplexing<br />
per LVDS pair<br />
• Greatly simplified logic partitioning<br />
• Source synchronous clocking for LVDS<br />
• Main Busses for global connectivity:<br />
- Main Bus A (MBUS48A), all <strong>FPGA</strong>s: 48<br />
single-ended signals<br />
- Main Bus B (MBUS48B), all <strong>FPGA</strong>s: 48<br />
single-ended signals<br />
• Auspy AES models for partitioning assistance<br />
- Hooks for other third-party partitioning solutions<br />
• 6 separate DDR2 SODIMMs (350MHz)<br />
- 64-bit data width, 350MHz operation<br />
- PC2-5300<br />
- Addressing/power to support 4GB in each<br />
socket<br />
- DDR2 Verilog/VHDL reference design<br />
provided (no charge)<br />
- DDR2 SODIMM data transfer rate: 32Gb/s<br />
- Alternate pin compatible memory cards<br />
available:<br />
• QDR SSRAM, Mictor, RLDRAM I,<br />
RLDRAM II, SSRAM, DDR3, DDR1,<br />
interconnect, SDRAM DRAM,<br />
FLASH, USB PHY, and others<br />
• SODIMM Daughtercard expansion<br />
- DNSODM200_Mictor - Mictor + 0.1” breakout<br />
- DNSODM200_Flash - two 4M x 32 flash chips<br />
DDR2 SODIMM<br />
(4GB max)<br />
DDR2 SODIMM<br />
(4GB max)<br />
= LVDS when paired, but can be used<br />
single-ended at reduced frequency<br />
120 190<br />
DIMM F18<br />
DDR2 SODIMM<br />
(4GB max)<br />
- DNSODM200_Quadmic - Mictors<br />
- More...<br />
• 3 board-level global clock networks (GCLK[2:0])<br />
- Separate programmable synthesizers for<br />
each network (Si5326)<br />
• Ultra-low jitter<br />
• 2 kHz – 710 MHz<br />
• User configurable via Compact FLASH or USB<br />
- Alternate clock sources:<br />
• Config <strong>FPGA</strong><br />
- single-step<br />
- Divide<br />
• SMA for external clock insertion<br />
• 4 Daughter Card global clock networks<br />
(DC_GCLK[3:0]). Select from:<br />
- Clock from daughter card with PLL for<br />
zero-delay (ICS8745B-21)<br />
• DC_GCLK0: Select DC0 or DC3 as source<br />
• DC_GCLK1: Select DC2 or DC4 as source<br />
• DC_GCLK2: Select DC5 or DC7 as source<br />
• DC_GCLK3: Select DC1 or DC8 as source<br />
- SMA for external clock insertion<br />
- Selected <strong>FPGA</strong> outputs<br />
• DC_GCLK0: Select GCLK0 or<br />
<strong>FPGA</strong>1 as source<br />
• DC_GCLK1: Select GCLK1 or<br />
<strong>FPGA</strong>8 as source<br />
• DC_GCLK2: Select GCLK2 or<br />
<strong>FPGA</strong>13 as source<br />
• DC_GCLK3: Select <strong>FPGA</strong>14 or<br />
<strong>FPGA</strong>13 as source<br />
• 8, 400-pin MEG-Array connectors (FCI) for<br />
daughter card (DC) expansion<br />
- 190 single-ended on DC0,1,2,7<br />
- 47 LVDS pairs (<strong>FPGA</strong> -> DC), 48 LVDS<br />
pairs (DC -> <strong>FPGA</strong>) on DC[6:3]<br />
• Can be used as 190 single ended signals<br />
- 600MHz on all signals with LVDS<br />
- Reset, presence detect<br />
- Supplied power rails (fused):<br />
• +12V (24W max)<br />
• +5V (10W max)<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
DC7<br />
Bus<br />
Switch<br />
34<br />
F19<br />
DCGCLK1<br />
(to all <strong>FPGA</strong>’s)<br />
DCGCLK2<br />
(to all <strong>FPGA</strong>’s)<br />
DCGCLK3<br />
(to all <strong>FPGA</strong>’s)<br />
G1 Si5326<br />
<strong>FPGA</strong> F8<br />
G2 Si5326<br />
<strong>FPGA</strong> F13<br />
<strong>FPGA</strong> F13<br />
<strong>FPGA</strong> F14<br />
• +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards<br />
using ISERDES/OSERDES and LVDS<br />
(up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- Compact FLASH, and/or USB<br />
- Integrated sanity checks on configuration files<br />
- Accelerated configuration readback<br />
• Custom base plate (standard) and optional<br />
rackmount chassis<br />
- Provides protection from those drooling<br />
engineers<br />
• 4, RS232 ports for embedded uP debug<br />
- Accessible from all <strong>FPGA</strong>s<br />
• Full support for embedded logic analyzers<br />
via JTAG interface<br />
- SignalTap, and other third party tools<br />
• Convert a pair of MEG-Array expansion<br />
connectors to interconnect with the<br />
DNMEG_Intercon.<br />
• MEG-Array Daughtercard Expansion<br />
- DNMEG_Obs - breakout/observation<br />
- DNMEG_Intercon - more interconnect<br />
- More...<br />
• Enough status LEDs to adequately illuminate<br />
a Twisted Sister concert.<br />
PLL<br />
SMA<br />
PLL<br />
SMA<br />
PLL<br />
DC2<br />
DC4<br />
DC5<br />
DC7<br />
DC1<br />
DC6
A<br />
B<br />
C<br />
D<br />
F<br />
A B C<br />
F<br />
E<br />
D<br />
F<br />
D<br />
<strong>FPGA</strong> A<br />
LED’s<br />
<strong>FPGA</strong> D<br />
LED’s<br />
18<br />
11<br />
<strong>FPGA</strong> B<br />
LED’s<br />
<strong>FPGA</strong> E<br />
LED<br />
<strong>FPGA</strong> F<br />
LED’s<br />
<strong>FPGA</strong> C<br />
LED’s<br />
DN7406K10PCIe-8T<br />
JTAG<br />
RJ45<br />
D<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
connector (400-pin)<br />
RJ45<br />
F<br />
RS232<br />
2<br />
(bussed)<br />
ALL <strong>FPGA</strong>s<br />
10/100/1000<br />
ETHERNET<br />
(VSC8601)<br />
125<br />
MHz<br />
48 48<br />
47 47<br />
48 48<br />
47 47<br />
9<br />
48 48<br />
47 47<br />
125<br />
MHz<br />
125 MHz<br />
10/100/1000<br />
ETHERNET<br />
(VSC8601)<br />
Config<br />
USB 2.0<br />
(480 Mb/s)<br />
RS232<br />
Reset<br />
COMPACT<br />
FLASH<br />
config<br />
ALL <strong>FPGA</strong>s<br />
Configuration<br />
<strong>FPGA</strong><br />
uP Config<br />
Control<br />
clock config<br />
Ethernet<br />
JTAG<br />
16<br />
MB [35:0]<br />
config data<br />
DDR2 SODIMM<br />
(4GB Max)<br />
QL5064<br />
122<br />
+2.5V<br />
I/O<br />
mac addr<br />
Flash<br />
(24C64)<br />
36<br />
8<br />
User<br />
Serial Flash<br />
(16 Mbit)<br />
1<br />
17<br />
2<br />
5<br />
<strong>FPGA</strong> D<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
62 62<br />
62 62<br />
46<br />
2<br />
clock input<br />
14<br />
9<br />
9<br />
184<br />
9<br />
9<br />
48 48<br />
48<br />
48<br />
x14<br />
<strong>FPGA</strong> E<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
MB [95:0]<br />
96<br />
9<br />
clock input<br />
1<br />
9<br />
9<br />
clock input<br />
186<br />
9<br />
9<br />
9<br />
9<br />
<strong>FPGA</strong> F<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
62 62<br />
62 62<br />
62 62 62 62<br />
46<br />
1<br />
2<br />
5<br />
14<br />
17<br />
mac addr<br />
Flash<br />
(24C64)<br />
8<br />
User<br />
Serial Flash<br />
(16 Mbit)<br />
x14<br />
122<br />
+2.5V<br />
I/O<br />
Main Bus<br />
Connector<br />
DDR2 SODIMM<br />
(4GB Max)<br />
114.285MHz<br />
<strong>FPGA</strong><br />
clock<br />
sourcing<br />
clk_TP<br />
single step clock<br />
(from config<br />
<strong>FPGA</strong>)<br />
clk_G0<br />
from config <strong>FPGA</strong><br />
48 MHz<br />
24<br />
MHz<br />
24<br />
MHz<br />
24<br />
MHz<br />
Clock Synth<br />
Si5326<br />
2Khz to 600MHz<br />
114.285MHz<br />
Clock Synth<br />
Si5326<br />
2Khz to 600MHz<br />
114.285MHz<br />
Clock Synth<br />
Si5326<br />
2Khz to 600MHz<br />
MB clock<br />
clk_G0<br />
(General<br />
clocking)<br />
clk_G1<br />
(DDR2)<br />
clk_G2<br />
(LVDS)<br />
clk_MB48<br />
DDR2 SODIMM<br />
(4GB Max)<br />
QL5064<br />
122<br />
89 89<br />
PCIe Express<br />
Endpoint<br />
<strong>FPGA</strong> A<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
(250 MHz)<br />
clock input<br />
184<br />
9<br />
9<br />
9<br />
9<br />
3<br />
User<br />
Serial Flash<br />
(16 Mbit)<br />
x3<br />
5<br />
1<br />
<strong>FPGA</strong> B<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
MICTOR<br />
clock input<br />
184<br />
x11<br />
clock input<br />
45<br />
User<br />
Serial Flash<br />
(16 Mbit)<br />
45<br />
45<br />
45<br />
21<br />
1<br />
21<br />
5<br />
21<br />
21<br />
<strong>FPGA</strong> C<br />
Stratix 4<br />
4SE820<br />
(FF1760)<br />
11<br />
x11<br />
34<br />
122<br />
MICTOR<br />
DDR2 SODIMM<br />
(4GB Max)<br />
Daughter card D<br />
clk_EXT0<br />
sma<br />
Daughter card F<br />
Daughter card E<br />
clk_EXT1<br />
PCI Express<br />
8 - lane<br />
GEN1 - 2.5 Gb/s (8-lanes)<br />
GEN2 - 5.0 Gb/s (4-lanes)<br />
= LVDS when paired, but can be used<br />
single-ended at reduced frequency<br />
Features<br />
PCIe endpoint<br />
clk_ref<br />
Global Clocks to all <strong>FPGA</strong>’s<br />
• PCI Express (8-lane) logic prototyping system with 2-6<br />
Altera Stratix-4 <strong>FPGA</strong>s<br />
- EP4SE820-3, -2 (slowest to fastest)<br />
- EP4SE530-3, -2<br />
• FF1760 package: 1,120 I/Os (with 4SE820)<br />
• Fixed 8-lane PCIe interface and controller provided<br />
- PCIe GEN1 rev 1.1<br />
- PCIe GEN2 with upgrade<br />
• 40+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix-4 4SE820s<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is a mix of single-ended and LVDS<br />
- 600 MHz LVDS chip to chip (1.2 Gb/s)<br />
- LVDS pairs can be used as two single-ended signals at<br />
reduced frequency (~225MHz)<br />
- Reference designs for integrated I/O pad ISERDES/OSERDES<br />
- 10x pin multiplexing per LVDS pair<br />
- Greatly simplified logic partitioning<br />
- Source synchronous clocking for LVDS<br />
• Main Bus (MB) connects all Stratix-4 <strong>FPGA</strong>s (96 signals)<br />
- Single-ended<br />
• Auspy models for partitioning assistance<br />
• 4 separate DDR2 SODIMMs (350MHz)<br />
- Direct connection to <strong>FPGA</strong>s A, C, F, D<br />
- PC2-4200 or better<br />
- Addressing/power to support 4GB in each socket<br />
- DDR2 Verilog/VHDL reference design provided (no charge)<br />
- DDR2 SODIMM data transfer rate: 32Gb/s<br />
- Alternate pin compatible memory cards available<br />
(consult factory for availability):<br />
• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH<br />
• DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR3<br />
• Mictor, USB PHY, Extra Interconnect<br />
• Seven independent low-skew global clock networks<br />
- G0, G1, G2, M48, EXT0, EXT1, REF<br />
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2<br />
- User configurable via CompactFLASH, USB, and/or PCIe<br />
- All seven global clocks networks distributed differentially and balanced<br />
• Two independent single-step clocks<br />
- Seven independent external clocks inputs (single-ended<br />
or differential) can be injected onto low-skew global clock networks<br />
Stratix IV<br />
<strong>FPGA</strong><br />
Speed<br />
Grades<br />
(slowest to<br />
fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate Estimate<br />
Max<br />
(100% util)<br />
(1000's)<br />
Practical<br />
(60% util)<br />
(1000's)<br />
• Flexible customization via daughter cards using expansion connectors<br />
- 3 daughter card locations: <strong>FPGA</strong>s D, E, F<br />
- 400-pin FCI MEG-Array connectors<br />
- 93 LVDS unidirectional pairs + clocks (or 186 single-ended)<br />
- 450MHz on all signals with source synchronous LVDS<br />
- Signal voltage set by daughter card (1.2v to 3.3V)<br />
- Reset<br />
- Supplied power rails (fused):<br />
• +12v (24W max)<br />
• +5V (10W max)<br />
• +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- CompactFLASH, USB, PCIe, JTAG<br />
- Configuration Error reporting<br />
- Accelerated configuration readback<br />
• RS232 port for embedded uP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- SignalTap, and other third-party debug solutions<br />
• 54 status <strong>FPGA</strong>-controller LEDs: bright enough to<br />
illuminate airplane landing strips<br />
Max I/O's<br />
MLAB<br />
(640)<br />
M9K<br />
(9 kbit)<br />
M144K<br />
(144 kbit)<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
4SE820 -4,-3 6-input 656,000 10,496 6,508 1120 960 16261 1610 60 23,130 2,891<br />
4SE530 -4,-3,-2 6-input 424,960 6,799 4,080 960 1024 10624 1280 64 20,736 2,592<br />
Multipliers<br />
(18x18)<br />
Memory<br />
858 . 454 . 3419 21
Stratix IV<br />
DN7002K10MEG<br />
COMPACT FLASH<br />
<strong>FPGA</strong><br />
CONFIGURATION<br />
Config<br />
2<br />
Config<br />
<strong>FPGA</strong><br />
36<br />
Main Bus (MB)<br />
Main Bus<br />
Connector<br />
RS232<br />
SSRAM<br />
FLASH<br />
72<br />
USB 2.0<br />
(type b)<br />
2<br />
uP<br />
Config<br />
Controller<br />
DDR2 SODIMM<br />
(4GB max)<br />
DDR2 SODIMM<br />
(4GB max)<br />
from <strong>FPGA</strong> A<br />
from <strong>FPGA</strong> B<br />
osc<br />
24<br />
MHz<br />
CLK_G2<br />
osc<br />
24<br />
MHz<br />
TP<br />
Config <strong>FPGA</strong><br />
osc<br />
24<br />
MHz<br />
Clock from<br />
daughter card A0<br />
48<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
ClockGen<br />
(Mult/Div)<br />
0-delay PLL<br />
CLK_G0<br />
48 MHz<br />
(MB Clock)<br />
CLK_G1<br />
(2KHz to 945 MHz)<br />
CLK_G2<br />
CLK_DC_A0<br />
A0<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
23 23 24 24<br />
90<br />
94<br />
24 24 23 23<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
122<br />
Stratix IV<br />
<strong>FPGA</strong><br />
A<br />
4SE820<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
AB<br />
AB6BUS<br />
LED<br />
(x8)<br />
BA<br />
182 182<br />
62<br />
62<br />
62<br />
62<br />
38<br />
Stratix IV<br />
<strong>FPGA</strong><br />
B<br />
4SE820<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
B0<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
23 23 24 24<br />
A1 A2 B2 B1<br />
LED<br />
(x8)<br />
122<br />
24 24 23 23<br />
92<br />
94<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
SMA<br />
Clock from<br />
daughter card B0<br />
ClockGen<br />
(Mult/Div)<br />
0-delay PLL<br />
CLK_DC_B0<br />
JTAG<br />
A<br />
B<br />
= LVDS when paired, but can be used<br />
single-ended at reduced frequency<br />
SMA<br />
CLK_DC_A2<br />
CLK_DC_B1<br />
ClockGen<br />
(Mult/Div)<br />
0-delay PLL<br />
CLK_DC_A2<br />
RS232<br />
2<br />
<strong>FPGA</strong>s<br />
CLK_DC_B2<br />
CLK_DC_A1<br />
Features<br />
22<br />
ClockGen<br />
(Mult/Div)<br />
0-delay PLL<br />
www.dinigroup.com<br />
CLK_DC_B2<br />
• USB2.0-hosted logic prototyping system with<br />
1-2 Altera Stratix 4 <strong>FPGA</strong>s<br />
- Stratix IV 4SE530 or 4SE820 in high I/O package (FF1760)<br />
• -30A VCCINT power per <strong>FPGA</strong><br />
• 13M+ ASIC gates (LSI measure) with two Stratix IV 4SE820<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is single-ended or LVDS<br />
- 600 MHz LVDS DDR chip-to-chip (1.2 Gb/s)<br />
• Characterized and tested<br />
- Reference designs for integrated I/O pad shift registers<br />
• 10x <strong>FPGA</strong> to <strong>FPGA</strong> pin multiplexing per LVDS pair<br />
• Greatly simplified logic partitioning<br />
• Source synchronous clocking for LVDS<br />
• 72-bit main busses for global connectivity:<br />
• Auspy AES models for partitioning assistance<br />
- Hooks for other third-party partitioning solutions<br />
• 2 separate DDR2 SODIMMs (350MHz)<br />
- 64-bit data width, 350MHz operation<br />
- PC2-5300<br />
- Addressing/power to support 4GB in each socket<br />
- DDR2 Verilog/VHDL reference design provided (no charge)<br />
- DDR2 SODIMM data transfer rate: 45Gb/s<br />
- Alternate pin compatible memory cards available:<br />
• QDR SSRAM, Mictor, RLDRAM I,<br />
RLDRAM II, SSRAM, DDR3, DDR1,<br />
IDC interconnect, SDRAM DRAM,<br />
FLASH, USB PHY, mobile SDRAM, & others<br />
• 3 low-skew global clock networks (GCLK[2:0])<br />
- Matched length and differentially distributed to each <strong>FPGA</strong><br />
- Separate programmable synthesizers for each network (Si5326)<br />
• Ultra-low jitter (as low as 0.3 ps)<br />
• 2 kHz – 710 MHz<br />
• User configurable via Compact FLASH or USB<br />
- Alternate clock sources:<br />
• Configuration <strong>FPGA</strong> for generation of single-step or divided clock<br />
• SMA for external clock insertion<br />
• 4 Daughter Card global clock networks (DC_GCLK[3:0])<br />
• 6, 400-pin MEG-Array connectors (FCI) for Daughter Card (DC) expansion<br />
- 1,116 total single-ended signals for daughter card expansion<br />
• 47/46 LVDS pairs (<strong>FPGA</strong> -> DC), 46/47 LVDS pairs (DC -> <strong>FPGA</strong>)<br />
• Can be used as 186 single-ended signals per connector<br />
• 600MHz (1.2Gb/s)<br />
• Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x)<br />
- Supplied power rails (fused):<br />
• +12V (24W max)<br />
• +5V (10W max)<br />
• +3.3V (10W max)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- Compact FLASH, USB, and/or JTAG<br />
- Integrated sanity checks on configuration files<br />
- Accelerated configuration readback<br />
• RS232 port for embedded uP debug<br />
- Accessible from both <strong>FPGA</strong>s<br />
• Full support for embedded logic analyzers via<br />
JTAG interface<br />
- SignalTap and other third party tools<br />
• Convert a pair of MEG-Array expansion<br />
connectors to interconnect with the<br />
DNMEG_Intercon.<br />
• Enough status LEDs to adequately direct traffic.
Alternate Memory: 200-pin SODIMM<br />
SODIMM OPTIONS<br />
DNSODM200_RLDRAM-II SODIMM<br />
<strong>The</strong> DNSODM200_RLDRAM-II is a<br />
SODIMM module that can be installed in<br />
a 200-pin DDR2 SODIMM socket. This<br />
module contains two RLDRAM II chips<br />
in a 32M x 36-bit configuration for a total<br />
of 144 megabytes.<br />
DNSODM200_DDR3 SODIMM<br />
<strong>The</strong> DNSODM200_DDR3 is a SODIMM.<br />
Provides 512MB of DRAM memory<br />
(DDR3 interface arranged as x64).<br />
DNSODM200_SSRAM SODIMM<br />
<strong>The</strong> DNSODM200_SSRAM is an<br />
SODIMM module that can be installed in<br />
a 200-pin DDR2 SODIMM socket. This<br />
module contains two SSRAM chips in a<br />
2M x 64 configuration for a total of 16<br />
megabytes.<br />
DNSODM200_SSRAMx4 SODIMM<br />
<strong>The</strong> DNSODM200_SSRAMx4 is a<br />
SODIMM module that can be installed in<br />
a 200-pin DDR2 SODIMM socket. This<br />
module contains four SSRAMs chips in a<br />
8M x 18 configuration.<br />
DNSODM200_INTERCON SODIMM<br />
<strong>The</strong> DNSODM200_INTERCON is a<br />
SODIMM compatible with all “DDR2”<br />
SODIMM slots on <strong>Dini</strong> <strong>Group</strong> products.<br />
This module provides up to 122 signals<br />
on 2mm headers for access. <strong>The</strong> signals<br />
can be used single-ended or differential.<br />
Termination resistors are provided to allow<br />
the use of standard IDC cabling<br />
DNSODM200_FLASH SODIMM<br />
<strong>The</strong> DNSODM200_FLASH is an<br />
SODIMM that can be installed in a 200-<br />
pin DDR2 SODIMM socket. This module<br />
contains two flash chips in a 4M x 32 configuration<br />
for a total of 16 megabytes.<br />
DNSODM200_MICTOR SODIMM<br />
<strong>The</strong> DNSODM200_MICTOR is a<br />
SODIMM module that can be installed in<br />
a 200-pin DDR2 SODIMM socket. This<br />
module contains two Mictor connectors<br />
and three, 12-pin IDC-type headers. Logic<br />
analyzers from Tektronix and Agilent can<br />
be directly connected to <strong>FPGA</strong> pins enabling<br />
direct high-speed observation.<br />
DNSODM200_QUADMIC SODIMM<br />
<strong>The</strong> DNSODM200_QUADMIC is a<br />
SODIMM module that can be installed in<br />
a 200-pin “DDR2” SODIMM socket. This<br />
module contains four Mictor connectors.<br />
Logic analyzers from Tektronix and Agilent<br />
can be directly connected to <strong>FPGA</strong><br />
pins enabling direct high-speed observation.<br />
DNSODM200_RLDRAM SODIMM<br />
<strong>The</strong> DNSODM200_RLDRAM is a<br />
SODIMM module that can be installed in<br />
a 200-pin DDR2 SODIMM socket. This<br />
module contains two RLDRAM chips in<br />
an 8M x 64-bit configuration for a total of<br />
64 megabytes.<br />
DNSODM200_USB SODIMM<br />
<strong>The</strong> DNSODM200_USB is a SODIMM.<br />
Provides a USB OTG physical interface<br />
(Standard ULPI). Also provides PCB audio,<br />
DIP switches, LEDs, SD card, 512k<br />
serial non-volatile memory.<br />
DNSODM200_DDR1 SODIMM<br />
<strong>The</strong> DNSODM200_DDR is a DDR2-to-<br />
PC2700 adapter card compatible with<br />
<strong>Dini</strong> <strong>Group</strong> products with DDR2 memory<br />
sockets. It allows a standard PC2700<br />
SODIMM (up to 512MB) to connect to<br />
the SODIMM slot of your <strong>Dini</strong> <strong>Group</strong><br />
Emulation board.tt<br />
DNSODM200_SDR SODIMM<br />
<strong>The</strong> DNSODM200_SDR is a DDR2-to-<br />
PC100 adapter card compatible with <strong>Dini</strong><br />
<strong>Group</strong> products with DDR2 sockets. It<br />
allows a standard PC133 SODIMM (up<br />
to 512MB of Single-Data rate memory)<br />
to connect to the DDR2 slot of your <strong>Dini</strong><br />
<strong>Group</strong> Emulation board.<br />
DNSODM200_SE SODIMM<br />
<strong>The</strong> DNSODM200_SE is a SODIMM module<br />
compatible with all 200-pin DIMM<br />
slots on <strong>Dini</strong> <strong>Group</strong> products. <strong>The</strong> module<br />
contains one 256Mb flash and two Micron<br />
32Mb SDRAM chips. An EPROM socket<br />
can hold a serial prom with densities up to<br />
512Kb. <strong>The</strong> DNSODM200_SE is compatible<br />
with all <strong>Dini</strong> <strong>Group</strong> products equipped<br />
with DDR2-SODIMM sockets.<br />
DNSODM200_QDR SODIMM<br />
<strong>The</strong> DNSODM204_QDR II+ is a<br />
SODIMM that can be installed in a 204-<br />
pin DDR3 SODIMM socket.<br />
858 . 454 . 3419 23
116<br />
116<br />
A<br />
G<br />
B<br />
F<br />
38<br />
C<br />
E<br />
38 39<br />
D<br />
39 38<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
38 59<br />
59<br />
FPU<br />
FPU<br />
4 4<br />
1<br />
4<br />
4<br />
4<br />
4<br />
4<br />
4<br />
iPASS Cable (3’-18’)<br />
4<br />
Host Computer<br />
PCIe Slot (8-lane)<br />
Virtex - 6<br />
DN2076K10<br />
18<br />
18<br />
MEG Array Expansion MEG Array Expansion<br />
connector (400-pin)<br />
connector (400-pin)<br />
96<br />
96<br />
96<br />
96<br />
<strong>FPGA</strong><br />
A<br />
Virtex-6<br />
LX550T / LX760<br />
38<br />
38<br />
117<br />
117<br />
DDR3 SODIMM<br />
(4GB Max)<br />
130<br />
<strong>FPGA</strong><br />
B<br />
Virtex-6<br />
LX550T / LX760<br />
SPI<br />
Flash<br />
137<br />
137<br />
IDC Connector<br />
16<br />
<strong>FPGA</strong><br />
C<br />
Virtex-6<br />
LX550T / LX760<br />
96 96<br />
117<br />
117<br />
DDR3 SODIMM<br />
(4GB Max)<br />
130<br />
<strong>FPGA</strong><br />
G<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
(FF1759)<br />
SX475T/LX550T<br />
GTX Expansion<br />
Header<br />
10GbE<br />
to<br />
XAUI<br />
QT2225<br />
10GbE<br />
to<br />
XAUI<br />
QT2225<br />
SFP+ Socket<br />
SFP+ Socket<br />
SFP+ Socket<br />
SFP+ Socket<br />
USB 3.0/2.0<br />
10GbE<br />
Ethernet<br />
10GbE<br />
Ethernet<br />
MEG Array Expansion<br />
connector (400-pin)<br />
96<br />
96<br />
<strong>FPGA</strong><br />
D<br />
Virtex-6<br />
LX550T / LX760<br />
157<br />
157<br />
117 117<br />
168 168<br />
<strong>FPGA</strong><br />
E<br />
Virtex-6<br />
LX550T / LX760<br />
160<br />
160<br />
<strong>FPGA</strong><br />
F<br />
Virtex-6<br />
LX550T / LX760<br />
MAIN BUS [51:0]<br />
SEARAY<br />
RGMII 10/100/1000<br />
Phy<br />
RJ45<br />
SFP<br />
10/100/1000<br />
base - T<br />
sma<br />
1 2 3<br />
0<br />
SMA<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> D<br />
<strong>FPGA</strong> G<br />
<strong>FPGA</strong> B<br />
<strong>FPGA</strong> C<br />
<strong>FPGA</strong> E<br />
<strong>FPGA</strong> A<br />
USER_T<br />
USER_R<br />
130<br />
DDR3 SODIMM<br />
(4GB Max)<br />
JTAG<br />
37<br />
37<br />
NMB<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> B<br />
<strong>FPGA</strong> C<br />
<strong>FPGA</strong> D<br />
<strong>FPGA</strong> E<br />
<strong>FPGA</strong> F<br />
<strong>FPGA</strong> G<br />
Config <strong>FPGA</strong><br />
Virtex-6<br />
(FF1156)<br />
SPI<br />
Flash<br />
4<br />
52<br />
PCI Express<br />
Cable<br />
(GEN 2)<br />
PCIe (GEN1 / GEN2)<br />
PCIe Cable Adapter<br />
Board<br />
Features<br />
• Hosted via<br />
Config <strong>FPGA</strong><br />
24<br />
MHz<br />
24<br />
MHz<br />
24<br />
MHz<br />
<strong>FPGA</strong> F<br />
<strong>FPGA</strong> D<br />
<strong>FPGA</strong> B<br />
CLK_25<br />
(25 MHz)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
USER_L<br />
G0<br />
(2KHz<br />
to 700 MHz)<br />
G1<br />
(2KHz<br />
to700 MHz)<br />
G2<br />
(2KHz<br />
to 700 MHz)<br />
10/100/1000<br />
baseT<br />
RJ45<br />
USB<br />
2.0<br />
(3x)<br />
RS232<br />
10/100/1000<br />
Phy<br />
SATA II<br />
(host)<br />
2x<br />
RGMII<br />
OSC<br />
USB<br />
DMA(4x)<br />
SATA<br />
RTC<br />
MPP Bus<br />
PCIe<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
4-lanes<br />
PCIe (GEN1)<br />
PCI Express Cable<br />
(GEN 1)<br />
- 4-lane GEN1 PCIe (v1.1) slot<br />
- USB2.0<br />
- 10/100/1000BASE-T Ethernet<br />
- Stand alone<br />
• Up to seven of the largest Xilinx Virtex-6 <strong>FPGA</strong>s<br />
- Six Xilinx Virtex-6 <strong>FPGA</strong>s (FF1760) from the following list:<br />
• LX760-2,-1,-1L(fastest to slowest), LX550T-2,-1,-1L<br />
- One Xilinx Virtex-6T <strong>FPGA</strong> (FF1759) from the following list:<br />
• LX550T-2,-1,-1L, SX475T-2,-1,-1L,SX315T-3,-2,-1,-1L<br />
• LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L<br />
- 50A VCCINT power per <strong>FPGA</strong><br />
• 37+ million ASIC gates (ASIC measure) when<br />
stuffed with 6 Virtex-6 LX760 and 1 LX550T<br />
• 24, GTX low-powered transceivers:<br />
- 65 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1<br />
- Dual AMCC QT2225-2 Dual Port Serial 10Gbps-to-XAUI Transceivers<br />
• Four SFP+ sockets for any of the following interfaces:<br />
- 10 Gigabit Optical Ethernet<br />
• 10GBase-SR 10GBASE-LR 10 GBASE-LRM 10GBASE-ER<br />
• 10 Gigabit Copper Ethernet: 10GBASE-R direct attach<br />
- 10 Gigabit Sonet: 10GBase-LW<br />
- 10 Gigabit FibreChannel<br />
- SFP socket<br />
- 4 channels using SMA connectors<br />
- 16 SMAs in total<br />
- 4-lane PCIe GEN1/GEN2 prototyping via iPASS cable<br />
- 2 SATA II ports: 1 host and 1 device<br />
CPU CPU<br />
64<br />
3<br />
8<br />
Third Party<br />
debug<br />
connector<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
(host)<br />
SATA II<br />
(device)<br />
= LVDS when paired, but can be run<br />
single-ended at reduced frequency<br />
- GTX Expansion header with LX550T/SX475T (SEARAY connector)<br />
- 8-lanes<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is LVDS<br />
- 1.3 Gb/s when using DDR with -2 speed grade<br />
• 1.0 Gb/s with -1 speed grade<br />
- LVDS pairs are length balanced and tested<br />
- LVDS pairs can be used as two single-ended<br />
signals at reduced frequency (~225MHz)<br />
- Reference designs for integrated I/O pad ISERDES/OSERDES<br />
- 10x pin multiplexing per LVDS pair, greatly simplified logic partitioning<br />
- Source synchronous clocking for LVDS<br />
• 52-pin Main Bus (MB[51:0]) connects all LX <strong>FPGA</strong>s<br />
• Auspy board interconnect models for logic partitioning assistance<br />
• Marvell MV78200 Discovery Innovation Dual CPU<br />
- 1 GHz clock<br />
- Dual USB2.0 ports (Type B connector)<br />
- Dual Serial-ATA II connectors (SATA II)<br />
- Gigabit Ethernet interface<br />
• 10/100/1000 GbE (RJ45 connector)<br />
- 1 GB external DDR2 SDRAM<br />
• Organized in a 128M x 64 configuration<br />
• 400 MHz (800 MHz data rate with DDR)<br />
- RS232 port for terminal-style observation<br />
- After configuration, both CPUs dedicated<br />
entirely to user application<br />
- LINUX operating system<br />
• Source and examples provided via GPL<br />
license (no charge)<br />
• ~15 seconds to CPU boot<br />
Virtex-6<br />
LX<br />
LXT<br />
SXT<br />
<strong>FPGA</strong><br />
Speed<br />
Grades<br />
(slowest<br />
to fastest)<br />
LUT<br />
Size<br />
FF's<br />
Gate<br />
Max<br />
(100% u<br />
(1000's<br />
LX760 -1,-2 6-input 948,480 9,105<br />
LX550(T) -1,-2 6-input 687,360 6,599<br />
LX365T -1,-2,-3 6-input 455,040 4,368<br />
LX240T -1,-2,-3 6-input 301,440 2,894<br />
LX195T -1,-2,-3 6-input 249,600 2,396<br />
LX130T -1,-2,-3 6-input 160,000 1,536<br />
SX475T -1,-2 6-input 595,200 5,714<br />
SX315T -1,-2 6-input 394,000 3,782<br />
24<br />
www.dinigroup.com
DNV6F2PCIe<br />
JTAG<br />
A<br />
DDR3 SODIMM<br />
(4GB Max)<br />
DDR3 SODIMM<br />
(4GB Max)<br />
130<br />
130<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> B<br />
CONFIG <strong>FPGA</strong><br />
SMA<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> B<br />
CONFIG <strong>FPGA</strong><br />
SMA<br />
CONFIG <strong>FPGA</strong><br />
24<br />
MHz<br />
24<br />
MHz<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
G0<br />
(2KHz<br />
to 700 MHz)<br />
G1<br />
(2KHz<br />
to 700 MHz)<br />
G2<br />
(2KHz<br />
to 700 MHz)<br />
B<br />
SFP<br />
SATA II<br />
(device)<br />
SATA II<br />
(host)<br />
Cabled<br />
PCIe<br />
(4-lane)<br />
iPASS<br />
Virtex-6<br />
Config <strong>FPGA</strong><br />
4<br />
Device Bus<br />
PCIe<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
60<br />
60<br />
NMB A<br />
NMB B<br />
OSC<br />
40<br />
<strong>FPGA</strong><br />
A<br />
Virtex-6<br />
LX760 / LX550T<br />
(FFG1760)<br />
94 94<br />
MEG Array Expansion<br />
connector (400-pin)<br />
AB<br />
40 40<br />
LEDs (8)<br />
322<br />
322<br />
<strong>FPGA</strong><br />
B<br />
Virtex-6<br />
LX760 / LX550T<br />
(FFG1760)<br />
94 94<br />
MEG Array Expansion<br />
connector (400-pin)<br />
35<br />
LEDs (8)<br />
MICTOR<br />
125 MHz<br />
150 MHz<br />
OSC<br />
250 MHz<br />
312.5 MHz<br />
125 MHz<br />
150 MHz<br />
OSC<br />
250 MHz<br />
312.5 MHz<br />
SFP<br />
Clock<br />
SATA<br />
Clock<br />
10/100/1000 10/100/1000<br />
Phy<br />
baseT<br />
RJ45<br />
RS232<br />
USB 2.0<br />
(2X)<br />
SATA II<br />
(host)<br />
2x<br />
RGMII<br />
USB<br />
DMA(4x)<br />
SATA<br />
Marvell MV78200<br />
RTC<br />
PCIe<br />
PCI EXPRESS<br />
FPU<br />
CPU CPU<br />
4-lanes<br />
PCIe (GEN1)<br />
FPU<br />
64<br />
3<br />
8<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
Battery<br />
Encryption<br />
Key Voltage<br />
= LVDS when paired,<br />
but can be used<br />
single-ended at a<br />
reduced frequency<br />
Features<br />
• Hosted via<br />
- 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T Ethernet<br />
- Stand alone<br />
• 2 Xilinx Virtex-6 <strong>FPGA</strong>s (FF1760) from the following list:<br />
- LX760-2,-1,-1L, LX550T-2,-1,-1L (fastest to slowest)<br />
- 50A VCCINT power per <strong>FPGA</strong><br />
• 11+ million ASIC gates (ASIC measure) when stuffed with 2 Virtex-6 LX760s<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is LVDS and GTX Rocket I/O<br />
- 1.3 Gb/s when using DDR with -2 speed grade<br />
• 1.0 Gb/s with -1 speed grade<br />
- Reference designs for integrated I/O pad ISERDES/OSERDES<br />
- 10x pin multiplexing per LVDS pair<br />
- Greatly simplified logic partitioning<br />
- Source synchronous clocking for LVDS<br />
• Bus connecting Config <strong>FPGA</strong> with each field <strong>FPGA</strong><br />
- 40 signals, single-ended (NMB[A:B])<br />
• RocketIO GTX Transceivers (Configuration <strong>FPGA</strong>)<br />
- PCI Express Cable (x4), SATA – Host (x1), SATA – Device (x1), SFP (x1)<br />
• Auspy board interconnect models for logic partitioning assistance<br />
• 2 separate DDR3 SODIMMs, one for each <strong>FPGA</strong> (AB)<br />
- 533MHz, 1066 MB/s, PC3-8500 or better<br />
- 64-bit, with addressing/power to support 4GB in each socket<br />
- DDR3 Verilog/VHDL reference design provided (no charge)<br />
- DDR3 SODIMM data transfer rate: 68Gb/s<br />
- Alternate pin compatible memory cards<br />
available (consult factory for availability):<br />
• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH<br />
• DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2<br />
• Mictor, USB PHY, Extra Interconnect<br />
• Three independent low-skew global clock networks<br />
- G0, G1, G2<br />
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
- User configurable via Marvell uP RS232,<br />
USB, PCIe, or Ethernet<br />
- Global clocks networks distributed differentially and balanced<br />
• Flexible customization via daughter cards using two expansion connectors<br />
- 400-pin FCI MEG-Array connector<br />
• Non proprietary, readily available, and cheap<br />
- 96 LVDS pairs + clocks (or 186 single-ended)<br />
- 650 MHz on all signals with source<br />
synchronous LVDS (with -2 speed grade)<br />
- Signal voltage set by daughter card (+1.2v to +2.5V)<br />
- Reset<br />
- Supplied power rails (fused):<br />
• +12v (24W max), +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- USB, PCIe, Ethernet, JTAG<br />
- Stand-alone configuration with USB stick or on-board NAND FLASH<br />
- Configuration Error reporting<br />
- Accelerated configuration readback for advanced debug<br />
• RS232 port for embedded <strong>FPGA</strong>-based SOC uP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope and other third-party debug solutions<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Enough illumination to sterilize refrigerator door handles.<br />
til)<br />
)<br />
Estimate<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
5,509 1,200 864 1,440 25,920 3,240<br />
3,959 1,200 864 1,264 22,752 2,844<br />
2,621 600 576 832 14,976 1,872<br />
1,736 600 768 832 14,976 1,872<br />
1,438 600 640 688 12,384 1,548<br />
922 600 480 528 9,504 1,188<br />
3,428 600 2,016 2,128 38,304 4,788<br />
2,269 600 1,344 1,408 25,344 3,168<br />
858 . 454 . 3419 25
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
Virtex - 6<br />
DNV6F6PCIe<br />
Features<br />
• Hosted via<br />
Config <strong>FPGA</strong><br />
10/100/1000<br />
baseT<br />
RJ45<br />
USB 2.0<br />
(3x)<br />
24<br />
MHz<br />
125 MHz<br />
150 MHz<br />
OSC<br />
250 MHz<br />
312.5 MHz<br />
G0<br />
- 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T<br />
Ethernet, or Stand alone<br />
• Six Xilinx Virtex-6 <strong>FPGA</strong>s (FF1759) from the<br />
following list:<br />
- LX550T-2,-1,-1L, SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L<br />
- LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L<br />
- 30A VCCINT power per <strong>FPGA</strong><br />
• 24+ million ASIC gates (ASIC measure) when stuffed with 6<br />
Virtex-6 LX550T<br />
• 21+ million ASIC gates and 12,096, 25x18 multipliers with 6<br />
Virtex-6 SX475T<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is LVDS and GTX RocketI/O<br />
- 710 MHz LVDS chip to chip with -3 speed<br />
grade (1.4Gb/s with DDR)<br />
• 650MHz with -2 (1.3 Gb/s with DDR), 500MHz with -1 (1.0 Gb/s<br />
with DDR)<br />
- Pairs are length balanced and tested!<br />
- LVDS pairs can be used as two single-ended signals at reduced<br />
frequency (~225MHz)<br />
• Reference designs for integrated I/O pad ISERDES/OSERDES<br />
• 10x pin multiplexing per LVDS pair. Source synchronous clock<br />
ing for LVDS<br />
- GTX Transceivers <strong>FPGA</strong> to <strong>FPGA</strong><br />
• 6.5 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1/-1L<br />
• Data examples provided using Aurora protocol<br />
• Bus connecting Config <strong>FPGA</strong> with each field <strong>FPGA</strong><br />
- 40 signals, single-ended (NMB[F..A])<br />
- Full PCI Express throughput to user design<br />
• Auspy board description models for logic partitioning assistance<br />
• 4 separate DDR3 SODIMMs, one for each corner Virtex-6 <strong>FPGA</strong> (ACFD)<br />
- 533MHz, 1066 MB/s with -2 and -3 speed grades (PC3-8500)<br />
• 400MHz, 800 Mb/s with -1 speed grade (PC3-6400)<br />
- 64-bit, with addressing/power to support 4GB in each socket<br />
- DDR3 Verilog/VHDL reference design provided (no charge)<br />
- DDR3 SODIMM data transfer rate: 68Gb/s<br />
- Alternate pin compatible memory cards available (consult factory<br />
for availability):<br />
• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH DRAM: SDR,<br />
DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra<br />
Interconnect<br />
SMA<br />
24<br />
MHz<br />
24<br />
MHz<br />
RS232<br />
SATA II<br />
(host)<br />
2x<br />
<strong>FPGA</strong> C<br />
<strong>FPGA</strong> E<br />
<strong>FPGA</strong> F<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> D<br />
<strong>FPGA</strong> B<br />
10/100/1000<br />
Phy<br />
CLK_25<br />
(25 MHz)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
RGMII<br />
USB<br />
USER_R<br />
USER_L<br />
G0<br />
(2KHz<br />
to 700 MHz)<br />
G1<br />
(2KHz<br />
to700 MHz)<br />
G2<br />
(2KHz<br />
to 700 MHz)<br />
MGT Clock<br />
DMA(4x)<br />
SATA<br />
RTC<br />
<strong>FPGA</strong> Q<br />
Virtex-5<br />
Config <strong>FPGA</strong><br />
MPP Bus<br />
PCIe<br />
PCIe<br />
(Gen1)<br />
4 - lanes<br />
Marvell MV78200<br />
PCIe<br />
PCI EXPRESS<br />
FPU FPU<br />
CPU CPU<br />
4-lanes<br />
PCIe (GEN1)<br />
SFP<br />
or<br />
SFP+<br />
SATA II<br />
(device)<br />
(host)<br />
NMB<br />
OSC<br />
64<br />
3<br />
8<br />
10/100/1000<br />
Phy<br />
DDR3 SODIMM<br />
(4GB Max)<br />
DDR3 SODIMM<br />
(4GB Max)<br />
128M x 64<br />
DDR2<br />
128Mb<br />
SPI<br />
Boot FLASH<br />
256Mb<br />
NAND FLASH<br />
Boot<br />
GTX<br />
1<br />
130<br />
130<br />
MEG Array Expansion<br />
connector (400-pin)<br />
40<br />
96 96<br />
<strong>FPGA</strong><br />
F<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
40 74` 74<br />
<strong>FPGA</strong><br />
C<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
8<br />
GTX<br />
GTX<br />
8<br />
GTX Expansion<br />
Header<br />
GTX<br />
12<br />
128Mb<br />
Flash<br />
4<br />
4<br />
58<br />
58<br />
20<br />
20<br />
4<br />
4<br />
120<br />
120<br />
20<br />
20<br />
40<br />
40<br />
GTX<br />
GTX<br />
GTX<br />
GTX<br />
MEG Array Expansion<br />
connector (400-pin)<br />
96 96<br />
<strong>FPGA</strong><br />
E<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
95<br />
95<br />
<strong>FPGA</strong><br />
B<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
128Mb<br />
FLASH<br />
GTX<br />
16<br />
128Mb<br />
Flash<br />
4<br />
4<br />
60<br />
60<br />
40<br />
40<br />
4<br />
4<br />
100<br />
100<br />
40<br />
40<br />
GTX<br />
GTX<br />
GTX<br />
GTX<br />
= LVDS when paired, but can be run<br />
single-ended at reduced frequency<br />
GTX--> Packet I/O Transceivers<br />
6.5 Gb/s per channel<br />
bidirectional (13 Gb/s max)<br />
MEG Array Expansion<br />
connector (400-pin)<br />
96 96<br />
<strong>FPGA</strong><br />
D<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
20 20 73 73<br />
<strong>FPGA</strong><br />
A<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
8<br />
GTX<br />
GTX<br />
GTX Expansion<br />
Header<br />
• Three independent low-skew global clock networks: G0, G1, G2<br />
- Three, high-resolution, user-programmable synthesizers for G0, G1, G2<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
- User configurable via Marvell uP RS232, USB, PCIe, or Ethernet<br />
- Global clocks networks distributed differentially and balanced<br />
• Add 8 SFP sockets to GTX Expansion Header with DNSEAM_SFP<br />
• Flexible customization via daughter cards using expansion connector<br />
- Daughter card location on <strong>FPGA</strong> D,E,F<br />
• 400-pin FCI MEG-Array connector - Non proprietary, readily<br />
available, and cheap<br />
- 96 LVDS pairs + clocks (or 186 single-ended)<br />
- 710 MHz (1/4 Gb/s) on all signals with source<br />
synchronous LVDS (assuming -3 speed grade)<br />
- Signal voltage set by daughter card (+1.2v to +2.5V)<br />
- Supplied power rails (fused): +12v (24W max), +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)<br />
• High Speed expansion via GTX connector<br />
- Connector for each <strong>FPGA</strong> A, C, F, 8 GTX lanes per connector<br />
- 6.5 Gb/s per lane, each direction (with -3)<br />
• 5.- Gb/s with -1 and 01L speed grade<br />
• Fast and Painless <strong>FPGA</strong> configuration via USB, PCIe, Ethernet, JTAG<br />
• Stand-alone configuration with USB stick or on-board NAND FLASH<br />
- Configuration Error reporting<br />
- Accelerated configuration readback for advanced debug<br />
• RS232 port for embedded <strong>FPGA</strong>-based SOC uP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope and other third-party debug solutions<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Enough illumination to act as automobile fog lights<br />
Virtex-6<br />
LX<br />
LXT<br />
SXT<br />
<strong>FPGA</strong><br />
Speed<br />
Grades<br />
(slowest<br />
to fastest)<br />
4<br />
8<br />
GTX<br />
12<br />
GTX<br />
130<br />
130<br />
GTX Expansion<br />
Header<br />
DDR3 SODIMM<br />
(4GB Max)<br />
DDR3 SODIMM<br />
(4GB Max)<br />
128Mb<br />
Flash<br />
LUT<br />
Size<br />
FF's<br />
Gate<br />
Max<br />
(100% u<br />
(1000's<br />
LX760 -1,-2 6-input 948,480 9,105<br />
LX550(T) -1,-2 6-input 687,360 6,599<br />
LX365T -1,-2,-3 6-input 455,040 4,368<br />
LX240T -1,-2,-3 6-input 301,440 2,894<br />
LX195T -1,-2,-3 6-input 249,600 2,396<br />
LX130T -1,-2,-3 6-input 160,000 1,536<br />
SX475T -1,-2 6-input 595,200 5,714<br />
SX315T -1,-2 6-input 394,000 3,782<br />
26<br />
www.dinigroup.com
DN-DualV6-PCIe-4<br />
from <strong>FPGA</strong> A<br />
from <strong>FPGA</strong> B<br />
TP<br />
osc<br />
24<br />
MHz<br />
CLK_G0<br />
osc<br />
24<br />
MHz<br />
Config <strong>FPGA</strong><br />
osc<br />
24<br />
MHz<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
CLK_G0<br />
CLK_G1<br />
(2KHz to 945 MHz)<br />
CLK_G2<br />
(iDELAY)<br />
SPI<br />
<strong>FPGA</strong> Q<br />
Virtex-5T<br />
LX50T<br />
Config <strong>FPGA</strong><br />
100<br />
100 20<br />
QA 20<br />
2 GTX<br />
DDR3 SODIMM<br />
(4GB max)<br />
122<br />
<strong>FPGA</strong> A<br />
Virtex-6<br />
SX475T / SX315T<br />
LX365T / LX240T<br />
LX195T / LX130T<br />
(FF1156)<br />
AB<br />
GTX (6.5 Gb/s)<br />
1<br />
1<br />
79<br />
79<br />
4<br />
DDR3 SODIMM<br />
(4GB max)<br />
122<br />
<strong>FPGA</strong> B<br />
Virtex-6<br />
SX475T / SX315T<br />
LX365T / LX240T<br />
LX195T / LX130T<br />
(FF1156)<br />
99<br />
99<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
RS232<br />
(device)<br />
PCIe<br />
LEDs<br />
(x8)<br />
(host)<br />
A<br />
JTAG<br />
SATA II<br />
B<br />
QB<br />
20<br />
OSC<br />
PCIe<br />
20<br />
JTAG Q<br />
(4-lanes)<br />
GTX 2<br />
MPP Bus<br />
1 1<br />
LEDs<br />
(x8)<br />
(device)<br />
(host)<br />
SATA II<br />
10/100/1000<br />
baseT<br />
RJ45<br />
USB 2.0<br />
(2x)<br />
RS232<br />
10/100/1000<br />
Phy<br />
RGMII<br />
USB<br />
DMA(4x)<br />
SATA<br />
Marvell MV78200<br />
PCIe<br />
FPU FPU<br />
CPU CPU<br />
64<br />
3<br />
128M x 64<br />
DDR2<br />
SPI<br />
Boot FLASH<br />
= LVDS when paired, but can be run<br />
single-ended at reduced frequency<br />
RTC<br />
4-lanes<br />
PCIe (GEN1)<br />
8<br />
NAND FLASH<br />
Boot<br />
PCI EXPRESS<br />
Features<br />
• Hosted in a 4-lane GEN1 PCIe (v1.1) slot, USB 2.0, 10/100/1000<br />
baseT Ethernet, stand alone<br />
• 1-2 Xilinx Virtex-6 <strong>FPGA</strong>s from the following list:<br />
- SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L, LX365T-3,-2,-1,-1L<br />
- LX240T-3,-2,-1,-1L, LX195T-3,-2,-1,-1L, LX130T-3,-2,-1,-1L<br />
- 50A VCCINT power shared between both <strong>FPGA</strong>s<br />
• FF1156 package with 600 I/Os, all utilized<br />
• 10+ million ASIC gates (ASIC measure) when<br />
stuffed with 2 Virtex-6 SX475T<br />
- 2016, 25 x 18 multipliers (with accumulator) per SX475<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is LVDS<br />
- 710 MHz LVDS chip to chip with -3 speed grade (1.4 Gb/s with DDR)<br />
• 650 MHz with -2 (1.3 Gb/s with DDR), 500 MHz with -1 (1.0<br />
Gb/s with DDR)<br />
- Pairs are length balanced and tested!<br />
- LVDS pairs can be used as two single-ended<br />
signals at reduced frequency (~225MHz)<br />
- Reference designs for integrated I/O pad ISERDES/OSERDES<br />
- 10x pin multiplexing per LVDS pair. Source synchronous clocking for LVDS<br />
• RocketI/O GTX Transceivers<br />
- 6.5 Gb/s (with -3, -2 speed grade), 5.0 Gb/s with -1<br />
- 4-lanes connected between <strong>FPGA</strong> A and <strong>FPGA</strong> B<br />
- 2 lanes connected from Config <strong>FPGA</strong> Q to <strong>FPGA</strong> A<br />
- 2 lanes connected from Config <strong>FPGA</strong> Q to <strong>FPGA</strong> B<br />
- Data examples provided using Aurora protocol<br />
• Auspy models for logic partitioning assistance<br />
• 2 separate DDR3 SODIMMs, one for each<br />
Virtex-6 <strong>FPGA</strong> (AB)<br />
- 533MHz, 1066 MB/s, PC3-8500 or better<br />
- 64-bit, with addressing/power to support 4GB in each socket<br />
- DDR3 Verilog/VHDL reference design provided (no charge)<br />
- DDR3 SODIMM data transfer rate: 68Gb/s<br />
- Alternate pin compatible memory cards<br />
available (consult factory for availability):<br />
• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH, DRAM: SDR,<br />
DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra<br />
Interconnect<br />
• Seven independent low-skew global clock networks: G0, G1, G2<br />
- High-resolution, user-programmable synthesizers for G0, G1, G2<br />
• Silicon Labs Si5326: 2kHz to 945 MHz<br />
- User configurable via Marvell uP RS232, USB, PCIe, or Ethernet<br />
- Global clocks networks distributed differentially and balanced<br />
• Single-step clock<br />
- External clock input can be injected onto low-skew global clock networks<br />
- single-ended or differential<br />
• Flexible customization via daughter cards using expansion connector<br />
- Daughter card location on <strong>FPGA</strong> B<br />
- 400-pin FCI MEG-Array connector<br />
• Non proprietary, readily available, and cheap<br />
- 93 LVDS unidirectional pairs + clocks (or 186 single-ended)<br />
- 710 MHz on all signals with source synchronous LVDS(with -3 speed grade)<br />
- Signal voltage set by daughter card (+1.2v to +3.3V)<br />
• Supplied power rails (fused): +12v (24W max) and +3.3V (10W max)<br />
- Pin multiplexing to/from daughter cards using LVDS (up to 10x)<br />
• Fast and Painless <strong>FPGA</strong> configuration<br />
- USB, PCIe, Ethernet, JTAG. Stand-alone configuration with USB stick<br />
- Configuration Error reporting<br />
- Accelerated configuration readback for<br />
advanced debug<br />
• RS232 port for embedded <strong>FPGA</strong>-based SOC uP debug<br />
- Accessible from all <strong>FPGA</strong>s via separate 2-signal bus<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope and other third-party debug solutions<br />
• Status <strong>FPGA</strong>-controlled LEDs<br />
- Bright enough to see from a low-space orbit, but won’t blind airline pilots.<br />
til)<br />
)<br />
Estimate<br />
Practical<br />
(60% util)<br />
(1000's)<br />
Max I/O's<br />
Multipliers<br />
(25x18)<br />
Blocks<br />
(18kbits)<br />
Memory<br />
Total<br />
(kbits)<br />
Total<br />
(kbytes)<br />
5,509 1,200 864 1,440 25,920 3,240<br />
3,959 1,200 864 1,264 22,752 2,844<br />
2,621 600 576 832 14,976 1,872<br />
1,736 600 768 832 14,976 1,872<br />
1,438 600 640 688 12,384 1,548<br />
922 600 480 528 9,504 1,188<br />
3,428 600 2,016 2,128 38,304 4,788<br />
2,269 600 1,344 1,408 25,344 3,168<br />
858 . 454 . 3419 27
Bottom<br />
Virtex - 6<br />
DNMEG_V6HXT<br />
4x 10 GbE<br />
or<br />
1x 40 GbE<br />
QSFP<br />
(40G)<br />
QSFP<br />
(40G)<br />
4<br />
4<br />
GTH<br />
GTH<br />
CPLD<br />
(SFP Control<br />
Signals)<br />
10 GbE<br />
to 6 GbE<br />
10/100/1000<br />
GbE<br />
100 GbE /<br />
40 GbE<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
SFP+<br />
CFP<br />
(40G / 100G)<br />
4<br />
8<br />
SATA II<br />
Device<br />
Host<br />
Device<br />
Host<br />
sma<br />
GTH<br />
GTX<br />
GTX<br />
GTX<br />
GTH 10<br />
GTH<br />
DDR3 UDIMM<br />
(16 GB Max)<br />
LED<br />
(4)<br />
72-bit Data<br />
Virtex-6 HXT<br />
<strong>FPGA</strong><br />
HT380T / 565T<br />
(FF1923)<br />
2<br />
8<br />
GTX<br />
150<br />
4<br />
GTX<br />
GTX<br />
110<br />
110<br />
GTX<br />
96<br />
96<br />
10<br />
FMC<br />
(Vita 57)<br />
Top<br />
MEG Array Expansion<br />
connector (400-pin)<br />
JTAG<br />
2<br />
2<br />
FMC<br />
RS232<br />
(x2)<br />
SMA<br />
28<br />
SPI Flash<br />
SPI Flash<br />
Debug<br />
(JTAG)<br />
Control<br />
2<br />
Config<br />
MCU<br />
LPC1754<br />
25 MHz<br />
Quad<br />
Clock<br />
Synthe<br />
-sizer<br />
Si5338<br />
www.dinigroup.com<br />
0<br />
1<br />
CLK_CFP<br />
CLK_QSFP<br />
CLK_SFP+HS<br />
CLK_SFP+LS<br />
<strong>FPGA</strong> Config<br />
GTX Expansion<br />
Header<br />
USB 2.0<br />
SEARAY<br />
Features<br />
• ASIC prototyping daughter card, stand-alone, or PCIe-hosted Serial I/O<br />
- 10GbE/40GbE/100GbE<br />
• Xilinx Virtex-6 HXT <strong>FPGA</strong> (FF1923)<br />
- HX565T-2,-1 or HX380T-3,-2,-1 (fastest to slowest)<br />
• 24 GTH transceivers (to ~11 Gb/s)<br />
• 40 GTX transceivers (to 6.5 Gb/s)<br />
• Virtex-6 HX565T resources:<br />
- 2M ASIC gates (ASIC measure)<br />
- 354k flip-flop/6-input LUTs (708k total FFs)<br />
- 4MB embedded memory (1824, 18 kbit blocks)<br />
- 864, 25x18 multipliers<br />
• Multiple High speed serial I/O Interfaces:<br />
- CFP Module – 10 lanes (GTH):<br />
• Single 40GbE (IEEE 802.3bg) or 100GbE<br />
- IEEE 802.3ba and IEEE 802.3bg<br />
- CAUI, XLAUI, OTL4.10, OTL3.4, and STL256.4 et al.<br />
- 2 – QSFP+ Modules (GTH)<br />
• Single 40GbE or 4 channels of 10GBASE<br />
- 4 – SFP+ Modules (GTH)<br />
• 4 channels 10GbE<br />
- 8 – SFP+ Modules (GTX)<br />
• 8 channels 10/100/1000GbaseT<br />
- Dual Serial ATA II (SATA II) Host/Device<br />
- 8 channels on GTX Expansion header<br />
- 2 GTH channels on SMAs<br />
• Bulk memory: 240-pin DDR3 uDIMM<br />
- 72-bit data width (64-bit with 8-bit ECC), 533MHz operation, PC3-8500<br />
- Addressing/power to support 16GB (+ ECC)<br />
RS232<br />
(LCD)<br />
JTAG<br />
CPLD<br />
<strong>FPGA</strong><br />
4<br />
4<br />
iPASS Cable (3’-18’)<br />
iPASS Connector<br />
PCIe Cable Adapter<br />
Board<br />
Cray/Sun/Intel/HP/et al.<br />
PCIe Slot (8-lane)<br />
- DDR3 Verilog/VHDL reference design provided (no charge)<br />
- Optional RLDRAM DIMM instead of DDR3 for ultra low latency<br />
• Optional cabled PCIe GEN1/GEN2 hosting (with DNMEG_CBL_GEN2)<br />
- Dual 1-lane, Dual 4-lane or single 8-lane<br />
- (Optional) PCIe clock slow down IP<br />
• Allows clocking the PIPE interface as slowly as 35 MHz<br />
- PCIe PIPE Slowdown Core<br />
• Flexible, abundant clock resources<br />
- 4 board-level clocks configurable clocks<br />
• Silicon Image Si5338: 0.16 to 710MHz<br />
- Fixed 150MHz oscillator for SATA II. Fixed 100MHZ oscillator for PCIe<br />
• Mount to DINI products with 400-pin MEG-Array connectors<br />
- 96 LVDS pairs + clocks (or 192 single-ended)<br />
• 550MHz on all signals with source synchronous LVDS. Slower<br />
when used single-ended<br />
- Pin multiplexing to/from motherboard using ISERDES/OSERDES<br />
and LVDS (up to 10x)<br />
• Supplied power rails (fused): +12V (24W max), +5V (10W<br />
max), +3.3V (10W max)<br />
- Reference designs for integrated I/O pad ISERDES/OSERDES<br />
• FMC (Vita 57) interface for use with off-the-shelf I/O boards<br />
- A/D-D/A, CameraLink, DSP, and RF Transceivers<br />
• Fast and Painless <strong>FPGA</strong> configuration with integrated uC and EEPROM<br />
• Dual RS232 ports for embedded uP debug and monitoring<br />
• Battery socket for configuration bitfile encryption<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope, ChipScope Pro, Veridae, and other third party solutions<br />
• Enough status LEDs to mystify a small trout
Specialty 204-pin SODIMM<br />
DNSODM204_SSRAM<br />
SSRAM: Pipeline or NoBL<br />
A [22:0]<br />
DQ [35:0]<br />
ADV / LD<br />
BW [A, B, C, D]<br />
23<br />
36<br />
SSRAM<br />
A [22:0]<br />
DQ [35:0]<br />
ADV / LD<br />
BW [3:0]<br />
DNSODM204_SE<br />
Mobile SDRAM, Flash<br />
Ck0<br />
RAS<br />
*<br />
CAS<br />
*<br />
WE<br />
*<br />
address<br />
15<br />
Mobile SDRAM<br />
WE<br />
CE [1:0]<br />
CEN<br />
ZZ<br />
OE<br />
CLK 0<br />
WE<br />
CE [1:0]<br />
CEN<br />
ZZ<br />
OE<br />
data<br />
Ck1<br />
16<br />
16M x 16<br />
Mobile SDRAM<br />
DQ [71:36]<br />
SSRAM<br />
A [22:0]<br />
DQ [35:0]<br />
BW [E, F, G, H]<br />
ADV / LD<br />
BW [3:0]<br />
data<br />
16<br />
WE<br />
CE [1:0]<br />
16M x 16<br />
CEN<br />
CLK 1<br />
ZZ<br />
OE<br />
8<br />
control<br />
address 25<br />
Flash<br />
(28F256)<br />
A [24:23]<br />
NC (future expansion)<br />
CS, SI, SO, RST, WP, SCK<br />
6<br />
Data Flash<br />
data<br />
16<br />
16M x 16<br />
DNSODM204_SSRAM1_8V<br />
SSRAM: Pileline or NoBL, 16M x 72<br />
+1.8V for Virtex-7, 144MB<br />
24FC256 IIC<br />
Serial EEPROM<br />
5<br />
SCL,SDA,SA0,SA1,VDDSPD<br />
204<br />
USB2.0 Phy, SPI Flash, NAND Flash<br />
5 Cntl[CKEn,Wn,En,Gn,BWxn,ADV,ZZ,LBOn]<br />
23<br />
A[22:0]<br />
4<br />
CLK[3:0]<br />
BA0<br />
Bank 0 only<br />
8 Data (12 Control)<br />
Nand Flash<br />
GS81284Z18-xxxV<br />
144Mb SSRAM<br />
8M x 18 NBT<br />
DQ[54:71]<br />
204-pin<br />
“DD3” SODIMM<br />
8 Data (5 Control)<br />
USB PHY USB 2.0<br />
(480Mb/s)<br />
To<br />
<strong>FPGA</strong><br />
32 Data<br />
Header<br />
GS81284Z18-xxxV<br />
144Mb SSRAM<br />
8M x 18 NBT<br />
DQ[36:53]<br />
32 Data<br />
Header<br />
SPI Flash<br />
GS81284Z18-xxxV<br />
144Mb SSRAM<br />
8M x 18 NBT<br />
DQ[18:35]<br />
1 Data (3 Control)<br />
GS81284Z18-xxxV<br />
144Mb SSRAM<br />
8M x 18 NBT<br />
DQ[17:0]<br />
DNSODM204_QUADMIC<br />
4 Mictors<br />
MICTOR<br />
DNSODM204_DDR2_FAST<br />
DQ [63:0]<br />
64<br />
Ck Ck<br />
30<br />
DDR2<br />
64M x 8<br />
DDR2<br />
64M x 8<br />
MICTOR<br />
8<br />
8<br />
34<br />
DDR2<br />
64M x 8<br />
DDR2<br />
64M x 8<br />
MICTOR<br />
8<br />
8<br />
34<br />
DDR2<br />
64M x 8<br />
DDR2<br />
64M x 8<br />
MICTOR<br />
8<br />
8<br />
34<br />
Addr<br />
8<br />
DDR2<br />
64M x 8<br />
18<br />
8<br />
DDR2<br />
64M x 8<br />
Control<br />
(RAS, CAS, WE)<br />
858 . 454 . 3419 29
Virtex - 7 (using DINAR1_SODM204) | Virtex - 6<br />
DNSODM204_DDR2_2GB<br />
DNSODM204_ARMDEBUG<br />
ARM Debug and Trace Interfaces<br />
DQ [63:0]<br />
ck ck<br />
64<br />
MT47H256M8<br />
MT47H256M8<br />
DDR2<br />
256M x 8<br />
DDR2<br />
256M x 8<br />
8<br />
8<br />
MT47H256M8<br />
MT47H256M8<br />
8<br />
DDR2<br />
256M x 8<br />
MT47H256M8<br />
DDR2<br />
256M x 8<br />
8<br />
DDR2<br />
256M x 8<br />
MT47H256M8<br />
DDR2<br />
256M x 8<br />
COMING SOON.<br />
consult factory for details<br />
8<br />
8<br />
MT47H256M8<br />
MT47H256M8<br />
DDR2<br />
256M x 8<br />
DDR2<br />
256M x 8<br />
8<br />
8<br />
Addr<br />
control<br />
(RAS, CAS, WE)<br />
DNSODM204_QDRII+<br />
QDRII+: 4M x 32<br />
DNSODM204_MICTOR_IO<br />
Mictor, DIP Switch, I/O, +5V tolerant, EEPROM, I2C<br />
C,C*<br />
18-pin IDC Connector<br />
CQ,CQ*<br />
D<br />
(17:0)<br />
DQ[15:0]<br />
18<br />
(16)<br />
4M x 18 QDR II+ SSRAM<br />
16<br />
16<br />
Level<br />
Trans<br />
(+5V Tolerant)<br />
A<br />
(19:0)<br />
CK*<br />
CK<br />
20<br />
K<br />
K<br />
Address<br />
Register<br />
CLK.<br />
Gen.<br />
Write Add. Decode<br />
Write Write Write Write<br />
Reg Reg Reg Reg<br />
Read Add. Decode<br />
1M x 18 Array<br />
1M x 18 Array<br />
1M x 18 Array<br />
1M x 18 Array<br />
Read Data Reg.<br />
Address<br />
Register<br />
Control<br />
Logic<br />
A<br />
20 (19:0)<br />
RPS<br />
C<br />
C<br />
CQ<br />
8<br />
8<br />
DIP<br />
Switches<br />
(2)<br />
72<br />
CQ<br />
WPS<br />
BWS<br />
[1:0]<br />
DK[47:32]<br />
Control<br />
Logic<br />
36<br />
36<br />
Reg.<br />
Reg.<br />
Reg.<br />
18<br />
18<br />
Q<br />
(16) [17:0]<br />
MICTOR<br />
16<br />
34<br />
DQ[31:16]<br />
D<br />
(17:0)<br />
A<br />
(19:0) 20<br />
CK* K<br />
CK K<br />
18<br />
Address<br />
Register<br />
CLK.<br />
Gen.<br />
(16)<br />
Write Add. Decode<br />
Write<br />
Reg<br />
1M x 18 Array<br />
Write<br />
Reg<br />
1M x 18 Array<br />
Write<br />
Reg<br />
1M x 18 Array<br />
Read Data Reg.<br />
Write<br />
Reg<br />
1M x 18 Array<br />
Read Add. Decode<br />
4M x 18 QDR II+ SSRAM<br />
Address<br />
Register<br />
Control<br />
Logic<br />
20<br />
RPS<br />
C<br />
C<br />
A<br />
(19:0)<br />
CQ<br />
2<br />
Ck1P<br />
EVENTn<br />
LED<br />
(2)<br />
SMA<br />
External Clock Input<br />
WPS<br />
BWS<br />
[1:0]<br />
DQ[63:48]<br />
RPS*<br />
Control<br />
Logic<br />
72<br />
36<br />
36<br />
Reg.<br />
Reg.<br />
Reg.<br />
18<br />
CQ<br />
18<br />
Q<br />
(16) [17:0]<br />
RSTn<br />
A0, A1<br />
SCL<br />
SDA<br />
EEPROM<br />
(24LC01)<br />
CQ,CQ*<br />
C,C*<br />
SCL<br />
I 2C<br />
Level<br />
Translator<br />
SDA<br />
I 2C Header<br />
+2.5V<br />
+3.3V<br />
30<br />
www.dinigroup.com
DINAR1 Daughter Cards<br />
DINAR1_SOC<br />
18<br />
RGMII<br />
KSZ9031RNX<br />
10/100/1000<br />
RGMII Ethernet<br />
Transceiver<br />
+5VDC<br />
RJ45<br />
10/100/1000<br />
Base-T<br />
Ethernet<br />
14<br />
ULPI<br />
USB3317<br />
USB 2.0<br />
Transceiver<br />
2<br />
Power<br />
Switch<br />
USB 2.0<br />
4<br />
Serial Data<br />
LTC2804CGN<br />
Dual RS232<br />
Transceiver<br />
4<br />
4<br />
Dual DB9<br />
Dual<br />
RS-232<br />
5<br />
4<br />
Serial Audio Data<br />
SPI/I2C<br />
PCM3793ARHBR<br />
Stereo Audio<br />
CODEC<br />
Mic In (2)<br />
Line Out<br />
Speaker Out<br />
(Stereo)<br />
DINAR1 Motherboard Header<br />
(400 pins)<br />
12<br />
2<br />
2<br />
8<br />
8<br />
2<br />
2<br />
12<br />
SD Bus<br />
Clock Inputs<br />
Clock Outputs<br />
8 GPIO + OE/DIR<br />
1.8V3.3V<br />
Translators<br />
(with bypass<br />
for 1.8V<br />
operation)<br />
IP4855CX25<br />
SD Card Voltage<br />
Translator<br />
GP SPI Bus 0<br />
GP SPI Bus 1<br />
GP IIC Bus 0<br />
GP IIC Bus 1<br />
GP Inputs/Outputs<br />
SD/SDHC/<br />
SDXC/SDIO<br />
Clock Inputs<br />
Clock Outputs<br />
9<br />
ARM JTAG<br />
8<br />
DQ<br />
8 Controls<br />
16 DQ<br />
26 Address<br />
8 Controls<br />
2 x MT29F16G08<br />
2 GB (16 Gb)<br />
NAND Flash<br />
2 x 28F00AP30<br />
128 MB (1Gb)<br />
NOR Flash<br />
2<br />
8<br />
AT24C512<br />
IIC Bus<br />
64KB (512Kb)<br />
EEPROM<br />
SPI Bus (3 Chip Selects)<br />
Features<br />
• 10Base-T/100Base-T/1000Base-T Ethernet Transceiver (802.3)<br />
- RGMII bus interface<br />
• USB2.0 Transceiver<br />
- Device, host, or On-<strong>The</strong>-Go device (OTG)<br />
- ULPI bus interface<br />
• 2 – RS232 ports<br />
- DB9 connector<br />
• 16-Bit, Low-Power Stereo Audio CODEC (PCM3793)<br />
- Microphone Bias<br />
- Headphone<br />
- Digital Speaker Amplifier<br />
• Secure Digital Card Interface Connector (SDIO)<br />
- I/O Voltage translation<br />
- Power – 100ma@3.3V<br />
• Single channel external clock input<br />
- Via dual SMAs<br />
• Single channel clock output<br />
- Via dual SMAs<br />
AT25512<br />
64KB (512Kb)<br />
EEPROM<br />
AT25DL081<br />
1MB (8Mb)<br />
Serial Flash<br />
N25Q256A11E<br />
64MB (256Mb)<br />
Serial NOR Flash<br />
• Miscellaneous general purpose I/O (+3.3V)<br />
- 8-bits on 16-pin 0.1” IDC connector (2 sets)<br />
• Intended for SPI<br />
- 2-bits on 8-pin 0.1” IDC connector (2 sets)<br />
• Intended for I2C<br />
- 12-bits on 20-pin 0.1” IDC connector (2 sets)<br />
• Intended for GPIO of any sort<br />
• ARM JTAG Connector<br />
• NAND Flash – MT29F16G08<br />
- 16 Gb with 8-bit data<br />
• NOR Flash -- 28F00AP30<br />
- 1 Gb with 16-bit data<br />
• EEPROM – AT24C512<br />
- I2C interface, 512 Kb<br />
• Bussed on a shared SPI<br />
- EEPROM - AT25512, 512 Kb<br />
- Serial Flash - AT25DL081, 8Mb<br />
- Serial NOR Flash N25Q256A11E<br />
858 . 454 . 3419 31
LED<br />
(x8)<br />
LEDs<br />
(X8)<br />
DINAR1 Daughter Cards<br />
DINAR1_LOOPBACK<br />
38<br />
38<br />
Loopback adapter card intended for manufacturing<br />
test of the DINAR1 expansion connector<br />
DINAR1<br />
Resistor<br />
Array<br />
38<br />
38<br />
DINAR1_SODM204<br />
Add a 204-SODIMM memory module to any<br />
DINAR1 expansion connector<br />
DINAR1 Expansion<br />
Connector<br />
8<br />
10 pin IDC<br />
130<br />
64-bit<br />
data<br />
DDR3 SODIMM<br />
(4GB Max)<br />
204-pin module<br />
options are on page<br />
29 - 30<br />
Regulator<br />
DDR3<br />
VTT<br />
+12V 1.5V<br />
Regulator<br />
4.3A<br />
DIMM<br />
VDD<br />
DINAR1_CBL<br />
30”<br />
Connect two cards together via a cable<br />
DINAR1 Connector<br />
DINAR1 Connector<br />
SEAM<br />
SEAM<br />
DINAR1_OBS<br />
+3.3V<br />
+12V<br />
Power<br />
LEDs<br />
Linear<br />
Reg<br />
Linear<br />
Reg<br />
Linear<br />
Reg<br />
Linear<br />
Reg<br />
Linear<br />
Reg<br />
+12V +3.3V<br />
32<br />
DDR3<br />
IODELAY<br />
Calibration<br />
Clock In<br />
VCCO_0<br />
(+1.8V)<br />
VCCO_1<br />
(+1.8V)<br />
VCCO_2<br />
(+1.8V)<br />
2.5V<br />
2.55V<br />
SMA<br />
OSC<br />
8<br />
200 MHz<br />
Clock Out<br />
SMA<br />
www.dinigroup.com<br />
2<br />
DINAR1 Expansion<br />
Connector<br />
4<br />
34<br />
19<br />
34<br />
19<br />
Voltage<br />
Translate<br />
MICTOR 0<br />
MICTOR 1<br />
8-pin IDC<br />
+3.3V<br />
User<br />
DIP Switch<br />
+1.8V<br />
+1.8V<br />
+3.3V<br />
LED<br />
VCCO_0<br />
VCCO_1<br />
GPIO 0<br />
GPIO 1<br />
40-pin 0.1”<br />
IDC Connector<br />
+1.8V<br />
40-pin 0.1”<br />
IDC Connector<br />
+1.8V<br />
Miscellaneous useful interfaces<br />
• Adjustable I/O voltages via on-board regulators<br />
- 3 separate banks individually configurable to +1.2V to +1.8V<br />
• Status LEDs:<br />
- Power: +12V, +3.3V, +2.5V<br />
- 8 user-controlled via <strong>FPGA</strong> pin<br />
• Two Mictor connectors: 34 single-ended signals each<br />
• Two 40-pin dual row IDC headers<br />
- 19 single-ended signals<br />
- +1.8V<br />
• Two 8-pin single row headers<br />
- 8 single-ended signals<br />
- +3.3V<br />
• Differential external clocks input via SMAs<br />
• Differential external clocks output via SMAs<br />
• 4 position DIP switch<br />
- 1 position with LED<br />
• Linear regulator for setting I/O bank voltage<br />
- 1 per bank (total of 3)
DINAR1 Daughter Cards | DNNMB<br />
DINAR1_FMC-LPC<br />
Low pin count FMC card transposer<br />
DINAR1_K7_FMC-HPC<br />
COMING SOON.<br />
consult factory for details<br />
DINAR1_INTERCON<br />
Add more <strong>FPGA</strong> to <strong>FPGA</strong> Interconnect<br />
DINAR1<br />
75<br />
75<br />
• Converts two, 400-pin, DINAR1 Expansion connectors into <strong>FPGA</strong> to <strong>FPGA</strong> interconnect<br />
- 75 pairs of length matched LVDS or 150 signals single-ended<br />
LVDS when paired, but<br />
can be run single-ended<br />
at a reduced frequency<br />
- LEDs indicate status for resets, power rails, and VCC voltages<br />
- VccI/O regulators<br />
DINAR1<br />
- Topside, Dual 400-pin, connectors for DINAR1_Obs Observation Daughter card<br />
DNNMB_CONNECTOR<br />
QSE<br />
Stacking transposer for NMB connector<br />
NMB CONNECTOR<br />
NMB1<br />
YMB<br />
NMB2<br />
CLKS<br />
CLKS<br />
CLKS<br />
40<br />
40<br />
40<br />
5<br />
5<br />
5<br />
QSE<br />
QSE<br />
QSE<br />
QSE<br />
QSE<br />
858 . 454 . 3419 33
HPI<br />
connector<br />
40-pin<br />
smc connector<br />
40-pin<br />
10-pin<br />
IDC<br />
IDC<br />
SMA<br />
38<br />
38<br />
10<br />
11<br />
sel<br />
+3.3V<br />
5<br />
6-pin<br />
1.8v<br />
1.8v<br />
1.8v<br />
1.8v<br />
3.3v<br />
+3.3v<br />
3.3v<br />
+3.3v<br />
DNMEG Daughter Cards<br />
DNMEG_OBS_III<br />
EXT_osc<br />
Aux<br />
(3.3v tolerant)<br />
SDIO<br />
ARM JTAG<br />
Header<br />
(+3.3v tolerant)<br />
GPIO<br />
(1.8v tolerant)<br />
MEG-Array Expansion<br />
Connector (400-pin)<br />
Debug Header (Mictor for Logic Analyzer)<br />
I 2 S<br />
Audio<br />
Codec<br />
PCM3793<br />
MIC (L & R)<br />
Speaker (L)<br />
Speaker (R)<br />
SPI<br />
Reset<br />
Button<br />
SPI<br />
MAX<br />
3107<br />
MAX<br />
3205<br />
RS232<br />
Reset<br />
Switch<br />
SDIO - MicroSD<br />
Card Adapter<br />
DNMEG_ETHERNET<br />
Analog In DC<br />
SMA<br />
Phono<br />
Jack<br />
SMA<br />
MEG Array<br />
14.18<br />
MHz<br />
THS4509<br />
Diff. Amp<br />
SMA<br />
xfrmr<br />
couple<br />
ADC_Clkout<br />
DC<br />
13/14-bit ADC<br />
ADC<br />
ADS5474 (14 bits)<br />
or<br />
ADS5440 (13 bits)<br />
24<br />
24<br />
5<br />
LED<br />
(5)<br />
MEG Array Expansion Connector<br />
(400 - pin)<br />
2<br />
RGMII<br />
5<br />
Video DAC<br />
ADV7127<br />
10-bits<br />
RS232<br />
10/100/1000<br />
Base-T<br />
Phy<br />
(RTL8251CL) 10/100/1000<br />
Base-T<br />
Ethernet<br />
10-pin<br />
IDC Header<br />
Phono<br />
Jack<br />
Add multiple high speed<br />
Ethernet connections to<br />
<strong>Dini</strong> <strong>Group</strong> <strong>FPGA</strong> boards<br />
with this adapter.<br />
68-pin<br />
SCSI Style<br />
20<br />
40-pin<br />
IDC<br />
DNMEG_HAAPS<br />
MEG Array<br />
Virtex-6 and Stratix-4<br />
(28 diff pairs) Altera Banks 0-2<br />
(2 diff pairs Rx CLK) or 4 LVCMOS signals<br />
I 2 C Interface<br />
+2.5V PSU<br />
+3.3V Power<br />
FETs<br />
HAPPS Connector<br />
(Samtec)<br />
Connect third party peripheral<br />
boards using the<br />
Samtec ASP-125521-03 to<br />
<strong>Dini</strong> <strong>Group</strong> <strong>FPGA</strong> cards using<br />
this handi transposer.<br />
DNMEG_LCDDRIVER<br />
<strong>The</strong> DNMEG_LCDDRIV-<br />
ER board is a converter<br />
from lvcmos to 7x datarate<br />
LVDS signals with an appropriate<br />
pattern for LCD<br />
panels.<br />
34<br />
www.dinigroup.com
SMA<br />
DNMEG Daughter Cards<br />
DNMEG_SODIMM4_FLASHSOCKET<br />
MEG - Array Expansion<br />
Connector (400-pin)<br />
Addr 9<br />
Data 16<br />
Control 13<br />
120<br />
DDR2 SODIMM<br />
(2GB Max)<br />
FLASH<br />
Socket<br />
(48TSOP)<br />
DNMEG_EXT<br />
Addr<br />
Data<br />
Control<br />
MICTOR<br />
MICTOR<br />
<strong>The</strong> DNMEG_SODIMM_4FLASH<br />
is a daughter card intended to add<br />
four Hynix FLASH memories and<br />
a DDR2 SODIMM to any expansion<br />
slot on an <strong>FPGA</strong> board from<br />
<strong>The</strong> <strong>Dini</strong> <strong>Group</strong>. A 48-pin TSOP<br />
socket is used, allowing the FLASH<br />
memories to be programmed by an<br />
off-the-shelf FLASH programmer.<br />
<strong>The</strong> Hynix HY28UG088g is the target<br />
FLASH device, but connections<br />
are provided to allow the use of almost<br />
any FLASH chip in a 48-pin TSOP<br />
package. <strong>The</strong> interface to all FLASH<br />
memories is easily debugged using a<br />
logic analyzer cabled to two mictor<br />
connectors. <strong>The</strong> two mictors are connected<br />
to all four of the FLASH memory’s<br />
address, data, clock, and control<br />
signals. A wide variety of SODIMMs<br />
can be used with this daughter card.<br />
<strong>The</strong> DNMEG_EXT riser card is a<br />
passive card that allows all signals to<br />
pass through. It raises a daughtercard<br />
by 14mm and is also useful for<br />
connecting multiple daughtercards.<br />
It is compatible with all <strong>Dini</strong> <strong>Group</strong><br />
<strong>FPGA</strong> boards and daughtercards with<br />
MEG-Array connectors.<br />
DNMEG_FLASHSOCKET<br />
External<br />
Clock Input<br />
MEG - Array Expansion<br />
Connector (400-pin)<br />
Addr (Control) 22<br />
Data<br />
Addr (SDRAM) 5<br />
DNMEG_OBS<br />
+3.3V<br />
32<br />
32<br />
7<br />
Control (SDRAM) 10<br />
Clk<br />
= LVDS when paired,<br />
but can be used<br />
single-ended at a<br />
reduced frequency<br />
I/O Voltage Control<br />
(1.2V to +3.3V)<br />
Bank 0<br />
Bank 1<br />
Linear<br />
Regulator<br />
+3.3V<br />
20-pin<br />
Header<br />
MICTOR<br />
Linear<br />
Regulator<br />
I/O Voltage Control<br />
Rocket I/O<br />
(1 Channel)<br />
MGTCLK input<br />
16<br />
VCC_B0<br />
v11<br />
SMA<br />
(Rx/Tx)<br />
SMA<br />
4<br />
26<br />
16<br />
(8 Pairs<br />
LVDS)<br />
VCC_B1<br />
1<br />
FLASH<br />
Socket<br />
(TSOP48)<br />
I/O<br />
68-pin<br />
‘SCSI-Style’<br />
Connector<br />
Micron<br />
Mobile<br />
SDRAM<br />
I/O<br />
FCI<br />
MEG-array<br />
Ball Grid<br />
Connector<br />
300-pin<br />
+12V<br />
16<br />
+5V<br />
+3.3V<br />
26<br />
36<br />
(18 Pairs<br />
LVDS)<br />
3<br />
clk 2<br />
GCA<br />
GCB<br />
20<br />
Addr (Control)<br />
Addr (SDRAM)<br />
Data<br />
22<br />
5<br />
16<br />
Control (SDRAM) 10<br />
40-pin<br />
IDC Connector<br />
40-pin<br />
20<br />
IDC Connector<br />
40-pin<br />
11<br />
IDC Connector<br />
v10<br />
MICTOR<br />
(4A)<br />
(4A)<br />
(6A)<br />
40-pin Header<br />
(0.1" pin spacing)<br />
4<br />
Samtec<br />
(3 Rocket I/O<br />
channels)<br />
MICTOR<br />
MICTOR<br />
+12V +5V +3.3V<br />
GCC<br />
Power<br />
LEDs<br />
<strong>The</strong> DNMEG_Flashsocket is a daughter<br />
card intended to add a single Hynix<br />
FLASH to any expansion slot on <strong>FPGA</strong><br />
boards from <strong>The</strong> <strong>Dini</strong> <strong>Group</strong>. A 48-pin<br />
TSOP socket is used, allowing the<br />
FLASH memory to be programmed<br />
by an off-the-shelf FLASH programmer.<br />
<strong>The</strong> Hynix HY28UG088G is the<br />
target FLASH device. We also provide<br />
connections to enable use of almost<br />
any FLASH chip in a 48-pin TSOP<br />
package.<br />
<strong>The</strong> DNMEG_Obs Observation<br />
Daughter card is a complete solution<br />
for observation of signals on a<br />
300-pin or 400-pin FCI MEG-Array<br />
connector and is used with the<br />
DN8000K10-series, DN7000K10-<br />
series, DN9000K10-series, and other<br />
<strong>FPGA</strong>-based products from <strong>The</strong> <strong>Dini</strong><br />
<strong>Group</strong>.<br />
+3.3V<br />
Linear<br />
Regulator<br />
VCC_B2<br />
<strong>FPGA</strong>_clk_OUT [P,N]<br />
2<br />
Resistor<br />
Select<br />
Resistor<br />
Select<br />
Bank 2<br />
I/O Voltage<br />
Control<br />
40-pin<br />
Header<br />
4<br />
24<br />
(12 Pairs<br />
LVDS)<br />
400-pin<br />
36<br />
(18 Pairs<br />
LVDS)<br />
4<br />
40-pin Header<br />
2<br />
2<br />
2<br />
125MHz<br />
v1.01<br />
858 . 454 . 3419 35
PROM<br />
<strong>FPGA</strong><br />
LEDs<br />
(8)<br />
Bottom<br />
Top<br />
(From <strong>FPGA</strong>)<br />
114.285MHz<br />
Clock Synth<br />
Si5326<br />
2KHz to 600MHz<br />
114.285MHz<br />
Clock Synth<br />
Si5326<br />
2KHz to 600MHz<br />
114.285MHz<br />
Clock Synth<br />
Si5326<br />
2KHz to 600MHz<br />
= LVDS when paired, but can be used<br />
single-ended at reduced frequency<br />
93<br />
93<br />
SMA<br />
clkmult 0<br />
clkmult 1<br />
clkmult 2<br />
XCF32<br />
Config<br />
PROM<br />
SPI<br />
Flash<br />
(16Mb)<br />
EXT_clk<br />
123<br />
8 2<br />
User<br />
LED's<br />
(8)<br />
17 11<br />
RS232<br />
4<br />
4<br />
1<br />
SMA<br />
DisplayPort<br />
(Source)<br />
4 pairs<br />
DisplayPort<br />
(Sink)<br />
4 pairs<br />
SFP Socket<br />
4<br />
4<br />
3<br />
2<br />
1<br />
0<br />
iPASS Cable (3’-18’)<br />
iPASS Connector<br />
Cray/Sun/Intel/HP/et al.<br />
PCIe Slot (8-lane)<br />
DNMEG Daughter Cards<br />
DNMEG_V5T_PCIe<br />
JTAG<br />
MEG Array Expansion<br />
connector (400-pin)<br />
Daughter Card to all:<br />
DN8000<br />
-- FX70T<br />
DN9000 Series Products<br />
} SX95T<br />
DN7000<br />
FX100T only<br />
LX110T<br />
}<br />
LX155T<br />
200 MHz<br />
step<br />
200 MHz<br />
100 MHz<br />
200 MHz<br />
100 MHz<br />
DDR2 SODIMM<br />
(4GB Max)<br />
DNMEG_AD_DA<br />
Aux Power JTAG<br />
+5V<br />
+12V<br />
sma<br />
sma<br />
AD8351<br />
ADC0 Clock<br />
AD8351<br />
ADC1 Clock<br />
EE<br />
ADC0<br />
AID<br />
Converter<br />
12-bit<br />
210 MSPS<br />
(AD9430)<br />
ADC1<br />
AID<br />
Converter<br />
12-bit<br />
210 MSPS<br />
(AD9430)<br />
<strong>FPGA</strong><br />
8<br />
RS232<br />
AD Data 0<br />
Serial Flash<br />
(4 mbit)<br />
AD Data 1<br />
Config<br />
EEPROM<br />
13<br />
1<br />
6<br />
13<br />
1<br />
2<br />
DDR2<br />
PCIe<br />
<strong>FPGA</strong><br />
Virtex-5T<br />
LX50T/LX85T/SX50T/<br />
FX70T/SX95T/FX100T<br />
LX110T/LX155T<br />
(FF1136)<br />
GTP<br />
OSC<br />
OSC<br />
200<br />
MHz<br />
100<br />
MHz<br />
DDR2 SODIMM<br />
(4GB Max)<br />
123<br />
<strong>FPGA</strong><br />
Virtex 4<br />
LX40, LX60<br />
LX80, LX100,<br />
SX55<br />
(FF1148)<br />
Mictor<br />
OSC 0<br />
OSC1<br />
200 MHz<br />
100 MHz<br />
34<br />
93<br />
16<br />
5<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
connector (400-pin)<br />
PCIe Cable Adapter<br />
Board<br />
sma<br />
A Data Channel 1<br />
DAC<br />
B Data<br />
sma<br />
Digital to<br />
Channel 2<br />
Control Analog<br />
Converter<br />
16-bit, 160 MSPS<br />
(AD9777)<br />
MICTOR<br />
DAC Clock<br />
16<br />
<strong>The</strong> DNMEG_V5T_PCIE allows an<br />
additional PCI Express interface to be<br />
added to any <strong>Dini</strong> <strong>Group</strong> <strong>FPGA</strong> board,<br />
including the DN9000K10. It connects<br />
to a base-board using the high-speed<br />
MEG-400 daughter card interface and<br />
can also be used stand-alone. In addition<br />
to two 4-lane PCIe cable interfaces,<br />
this card is equipped with an SFP,<br />
four RX/TX channels via SMAs, and<br />
one 4x DisplayPort Source/Sink.<br />
<strong>The</strong> DNMEG_AD-DA is intended to<br />
be a peripheral daughter card to our<br />
ASIC emulation products, but can be<br />
used stand-alone with an inexpensive<br />
ATX power supply. It allows designers<br />
two DAC channels and two ADC<br />
channels for Analog-to-Digital or Digital-to-Analog<br />
communication.<br />
DNMEG_S2GX<br />
AUX<br />
Power<br />
connector<br />
+5V 10A 1.2V<br />
Switcher<br />
+1.8V<br />
5A<br />
+3.3V<br />
Switcher<br />
19.53125<br />
MHz<br />
freq_sel<br />
OSC<br />
(DDR2<br />
clock)<br />
SMA Clock<br />
Input<br />
CLK_SMA<br />
User<br />
clock<br />
socket<br />
Clock<br />
synths<br />
(ICS844051)<br />
OSC<br />
156.25<br />
MHz<br />
OSC<br />
62.5<br />
MHz<br />
OSC<br />
optional<br />
fixed<br />
frequency<br />
(not<br />
stuffed)<br />
78.125 MHz or 156.25 MHz<br />
OSC 13<br />
OSC 14<br />
OSC 15<br />
= Differential, but can be used<br />
single-ended at a reduced frequency<br />
user<br />
LED's<br />
(8)<br />
ByteBlasterII<br />
Configuration<br />
Flash<br />
Serial<br />
Flash<br />
+1.5V to +3.3V I/O<br />
JTAG<br />
DNMEG_1G_SSRAM<br />
8<br />
123<br />
DDR2 SODIMM<br />
(4GB Max)<br />
MEG Array Expansion<br />
connector (400-pin)<br />
6<br />
93<br />
93<br />
<strong>FPGA</strong><br />
Stratix II GX<br />
2SGX90E<br />
(FF1152)<br />
4<br />
(Rx/Tx)<br />
1<br />
1<br />
2<br />
sma<br />
0<br />
1 2 3<br />
Host<br />
Peripheral<br />
SFP socket<br />
SFP socket<br />
SFP socket<br />
SFP socket<br />
RS232<br />
RS232<br />
Level Translator<br />
SATA<br />
Interface<br />
<strong>The</strong> DNMEG_S2GX is a daughter<br />
card that enables ASIC or IP designers<br />
to prototype logic and memory designs<br />
for a fraction of the cost of existing solutions.<br />
Of the 12 available high-speed<br />
channels, four are connected to SFPs,<br />
four to SMAs, and four to SATA connectors.<br />
Add 1Gb of SSRAM to <strong>Dini</strong> <strong>Group</strong><br />
<strong>FPGA</strong> boards with this adapter.<br />
36<br />
www.dinigroup.com
114.285<br />
MHZ<br />
114.285<br />
MHZ<br />
114.285<br />
MHZ<br />
EEPROM<br />
EEPROM<br />
EEPROM<br />
clk 0<br />
clk 1<br />
control & config<br />
RESET<br />
clk 0<br />
clk 1<br />
control & config<br />
clk 0<br />
clk 1<br />
control & config<br />
GTP OSC<br />
GTP OSC<br />
114.285 MHz<br />
114.285 MHz<br />
114.285 MHz<br />
OSC0<br />
OSC1<br />
CLK2-1<br />
CLK QSE<br />
CLK1-1<br />
CLK1-2<br />
ClK0-1<br />
CLK0-2<br />
1<br />
2<br />
Top<br />
Bottom<br />
5<br />
10<br />
0<br />
DDR2<br />
OSC<br />
200 MHz<br />
Channel 0<br />
MICTOR<br />
1<br />
CLK-QSE<br />
3<br />
+1.21V<br />
+1.5V<br />
+1.2V<br />
+3.3V<br />
+1.8V<br />
DNIOB: High Speed Serial Interfaces<br />
+3.3V<br />
DNMEG_INTERCON<br />
External<br />
Power<br />
(stand alone<br />
operation only)<br />
JTAG<br />
I/O Bank<br />
reference Voltage<br />
Ref<br />
VCCO<br />
Bank0<br />
Ref<br />
VCCO<br />
Bank1<br />
Ref<br />
VCCO<br />
Bank2<br />
500mA<br />
Config<br />
PROM<br />
+5V<br />
+12V<br />
<strong>FPGA</strong><br />
+2.5V<br />
+2.5V<br />
+2.5V<br />
+12V +5V +3.3V<br />
LED<br />
LED<br />
LED<br />
400-pin<br />
MEG-Array<br />
connector<br />
(P1)<br />
DNMEG_DVI<br />
B0<br />
B1<br />
B2<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
93 93<br />
Base Board Connections<br />
1 2 3 4<br />
6.5 Gb/s<br />
Rocket I/O<br />
(tx/rx)<br />
400-pin MEG-Array<br />
connector (P3)<br />
- LVDS when paired, but can be used<br />
single-ended at reduced frequencies<br />
93<br />
93<br />
93<br />
Switching<br />
Regulator<br />
Switching<br />
Regulator<br />
Switching<br />
Regulator<br />
Switching<br />
Regulator<br />
Switching<br />
Regulator<br />
93<br />
400-pin<br />
MEG-Array<br />
connector<br />
(P2)<br />
B_RST<br />
T_RST<br />
<strong>The</strong> DNMEG_Intercon is a daughter<br />
card that bridges the expansion signals<br />
between two 400-pin MEG-Array connectors,<br />
adding 93 pairs of LVDS signals<br />
for <strong>FPGA</strong> to <strong>FPGA</strong> interconnect.<br />
At a lower frequency, the 93 pairs can<br />
be used as 186 signal ended signals.<br />
Linear regulators needed to drive the<br />
VCCIO voltages are provided, along<br />
with several LEDs for power presence<br />
and reset activity.<br />
<strong>The</strong> DNMEG_DVI-400 provides duallink<br />
input and dual-link output Digital<br />
Video interface (DVI) functionality.<br />
DVI Input<br />
(Dual-Link)<br />
Si5326<br />
Freq<br />
Synth<br />
2<br />
2<br />
DVI TX0<br />
SIL163B<br />
SIL163B<br />
24<br />
24<br />
Config<br />
PROM<br />
XCF32<br />
MGT<br />
OSC<br />
24<br />
24<br />
Virtex4<br />
<strong>FPGA</strong><br />
FX60/FX100<br />
(FF1152)<br />
PPC PPC<br />
Rocket I/O<br />
12<br />
12<br />
32<br />
12<br />
12<br />
SIL1178<br />
SIL1178<br />
DVI Output<br />
(Dual-Link)<br />
Freq<br />
Synth<br />
2<br />
2<br />
DVI TX1<br />
Rocket I/O<br />
UART<br />
120<br />
Freq<br />
Synth<br />
2<br />
2<br />
2<br />
2<br />
1<br />
LED's<br />
DDR2 SODIMM<br />
MGT<br />
4 4<br />
RS232<br />
Santec High<br />
Speed Cable<br />
Connector (QSE-DP)<br />
SFP<br />
socket<br />
LVDS when paired, but can be run<br />
single-ended at reduced frequencies.<br />
DNMEG_MICTOR_DIFF<br />
<strong>The</strong> DNMEG_Mictor_Diff daughter<br />
card is a solution for connecting you<br />
<strong>Dini</strong> <strong>Group</strong> board to a differential<br />
(read: NON-AMP) mictor interface.<br />
<strong>The</strong> PCB is routed for maximum differential<br />
throughput and the connectors<br />
pinned out to minimize crosstalk<br />
between pairs.<br />
DNMEG_V5T<br />
Aux Power<br />
+5V<br />
+12V<br />
JTAG<br />
EE<br />
RS232<br />
Clock Synth<br />
Si5326<br />
Clock Synth<br />
Si5326<br />
Clock Synth<br />
Si5326<br />
LEDs<br />
(8)<br />
Green<br />
<strong>FPGA</strong><br />
= Differential when paired, but<br />
can be used single ended at<br />
reduced frequency<br />
= SX95T, FX70T, FX100T,<br />
LX110T, LX155T only<br />
= SPI Flash Configuration<br />
8<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
5<br />
Serial<br />
FLASH<br />
(16 Mbit)<br />
sma<br />
sma<br />
EXT Clock<br />
user GTP<br />
DDR2 SODIMM<br />
(4GB Max)<br />
123<br />
<strong>FPGA</strong><br />
Virtex-5T<br />
LX50T/LX85T/SX50T<br />
SX95T/FX70T/FX100T<br />
LX110T/LX155T<br />
(FFG1136)<br />
Config<br />
EEPROM<br />
Battery<br />
2<br />
+<br />
23<br />
11<br />
200 MHz<br />
OSC<br />
(DDR2)<br />
GTP<br />
GTP<br />
GTP<br />
GTP<br />
MICTOR<br />
4<br />
4<br />
4<br />
4<br />
93<br />
+1.5V to +3.3V I/O<br />
(bottom)<br />
MEG Array Expansion<br />
connector (400-pin)<br />
(top)<br />
sma<br />
1 2 3<br />
Infiniband<br />
0<br />
SFP Socket (x4)<br />
QSE<br />
- TX Fault SFP Signals<br />
(LX110T/ - MOD_DEF0 not available<br />
SX95T - RATE_SEL with LX50T,<br />
only)<br />
- LOS<br />
LX85T, SX50T<br />
<strong>The</strong> DNMEG_V5T enables engineers<br />
to utilize the Xilinx Virtex-5T <strong>FPGA</strong><br />
for high-speed serial interconnect. It is<br />
hosted on any <strong>Dini</strong> <strong>Group</strong> ASIC Emulation<br />
/product that has MEG-Array<br />
expansion capability but also can be<br />
operated in stand-alone mode with a<br />
separate power supply. Connectors<br />
for the high-speed MGTs include four<br />
SMA channels (Rx/Tx), one 4x Infiniband<br />
connector, four SFP sockets, and<br />
four high-speed channels on a QSE<br />
connector.<br />
858 . 454 . 3419 37
DC2<br />
DC3<br />
SMA<br />
SMA<br />
20<br />
96<br />
96<br />
20<br />
DDR2 SODIMM<br />
(4GB max)<br />
120 120 120 96 96<br />
<strong>FPGA</strong><br />
0<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
240 240<br />
<strong>FPGA</strong><br />
4<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
120 120<br />
<strong>FPGA</strong><br />
8<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
120 120<br />
<strong>FPGA</strong><br />
12<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
160<br />
20 20<br />
20 20<br />
120<br />
20 20<br />
20 20<br />
120<br />
20 20<br />
20 20<br />
160<br />
120 120<br />
120 120<br />
120 120<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
120 120 120<br />
DDR2 SODIMM<br />
(4GB max)<br />
DIMM0 DIMM1 DIMM2<br />
DIMM3<br />
Serial<br />
FLASH<br />
128Mb<br />
Serial<br />
FLASH<br />
128Mb<br />
DDR2 SODIMM<br />
(4GB max)<br />
<strong>FPGA</strong><br />
1<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
<strong>FPGA</strong><br />
5<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
<strong>FPGA</strong><br />
9<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
<strong>FPGA</strong><br />
13<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
DDR2 SODIMM<br />
(4GB max)<br />
DIMM4<br />
Serial<br />
FLASH<br />
128Mb<br />
Serial<br />
FLASH<br />
128Mb<br />
120<br />
80<br />
80<br />
120<br />
DDR2 SODIMM<br />
(4GB max)<br />
<strong>FPGA</strong><br />
2<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0 1 0<br />
<strong>FPGA</strong><br />
6<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0 1 0<br />
<strong>FPGA</strong><br />
10<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0 100<br />
<strong>FPGA</strong><br />
14<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
DDR2 SODIMM<br />
(4GB max)<br />
DIMM5<br />
Serial<br />
FLASH<br />
128Mb<br />
MBV<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
20 20<br />
Serial<br />
FLASH<br />
128Mb<br />
140<br />
80<br />
120<br />
120<br />
140<br />
SMA<br />
SMA<br />
+1.5V to +3.3V I/O<br />
DC4<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
<strong>FPGA</strong><br />
3<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0 100<br />
<strong>FPGA</strong><br />
7<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0<br />
1 0<br />
<strong>FPGA</strong><br />
11<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
1 0 1 0<br />
<strong>FPGA</strong><br />
15<br />
Virtex-5<br />
LX330<br />
(FF1760)<br />
96 96<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
DC9<br />
+1.5V to +3.3V I/O<br />
96<br />
MBH<br />
96<br />
96<br />
MBH<br />
96<br />
SMA<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
DC5<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
QuickSwitch<br />
DC6<br />
MEG Array Expansion<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
+1.5V to +3.3V I/O<br />
QuickSwitch<br />
DC7<br />
DC8<br />
SMA<br />
80<br />
(quickswitches)<br />
MBH<br />
MICTOR<br />
Control<br />
32<br />
CY7C68013<br />
uP Configuration<br />
controller<br />
Clock Mux<br />
Control<br />
MBCLK<br />
Reference Clock<br />
GCLK0<br />
GCLK1<br />
GCLK2<br />
DC_GCLK0<br />
DC_GCLK1<br />
DC_GCLK2<br />
DC_GCLK3<br />
SRAM<br />
128Kb x 8<br />
Flash<br />
1 M x 8<br />
Config<br />
<strong>FPGA</strong><br />
LX80<br />
(FF1148)<br />
Single-Step Clock<br />
JTAG<br />
USB 2.0<br />
48 MHz<br />
8<br />
RS232<br />
4 Serial<br />
Ports<br />
(Tx/Rx)<br />
COMPACT FLASH<br />
<strong>FPGA</strong><br />
CONFIGURATION<br />
Reset<br />
96<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
Config PROM<br />
LCD<br />
Control<br />
Panel<br />
PCI0<br />
Clock Synth<br />
Si5326<br />
Clock Synth<br />
Si5326<br />
External<br />
Clock SMA's<br />
Clock Synth<br />
Si5326<br />
External<br />
Clock SMA's<br />
Clock Synth<br />
Si5326<br />
External<br />
Clock SMA's<br />
from Daughter Card 2 (DC2)<br />
from Daughter Card 4 (DC4)<br />
from Daughter Card 3 (DC3)<br />
from Daughter Card 9 (DC9)<br />
from Daughter Card 5 (DC5)<br />
from Daughter Card 6 (DC6)<br />
from Daughter Card 7 (DC7)<br />
from Daughter Card 8 (DC8)<br />
LED<br />
(x32)<br />
104<br />
104<br />
32<br />
20<br />
32<br />
32<br />
32<br />
30<br />
29<br />
(USB 3300)<br />
40-pin<br />
IDC Headers<br />
(x5)<br />
Config<br />
EEPROM<br />
RJ45<br />
2<br />
3<br />
3<br />
15<br />
32<br />
7<br />
22<br />
16<br />
4<br />
36<br />
16<br />
SDRAM<br />
16M x 32<br />
FLASH<br />
(32/64 MBIT)<br />
(AT<br />
49BV320D)<br />
2M x 16<br />
SSRAM<br />
(512k x 36)<br />
CY7C<br />
1380D<br />
SoundMAX<br />
Codec<br />
(AD1881A)<br />
<strong>FPGA</strong><br />
CD Audio<br />
Line Out<br />
Headphone<br />
In<br />
EE<br />
DNMEG Daughter Cards<br />
DNMEG_DOUBLE<br />
+3.3V<br />
I/O Bank<br />
Reference Voltage<br />
Ref +2.5V<br />
VCCO<br />
Bank0<br />
LED<br />
Ref<br />
VCCO<br />
Bank1<br />
Ref<br />
VCCO<br />
Bank2<br />
500mA<br />
B0<br />
+2.5V<br />
B1<br />
LED<br />
+2.5V<br />
B2<br />
LED<br />
400-pin<br />
MEG-Array<br />
Connector<br />
(P1)<br />
93 93<br />
93<br />
93<br />
93 93<br />
400-pin<br />
MEG-Array<br />
Connector<br />
(P2)<br />
B_RST<br />
T_RST<br />
Connect two DNV6_F2PCIE cards together.<br />
Also works for other cards in<br />
the V6 line of <strong>Dini</strong> products.<br />
External<br />
Clock<br />
Input<br />
p1<br />
p2<br />
400-pin<br />
MEG-Array<br />
Connector<br />
(P3)<br />
= LVDS when paired, but can be used<br />
single-ended at reduced frequencies<br />
+12V<br />
+5V +3.3V<br />
DNMEG_HSMC<br />
(VCCO regulators set to +2.5V,<br />
for MEG Array Signals)<br />
LT1963A<br />
Power<br />
MEG<br />
Array<br />
Bank #1 Bank #3 Bank #2 Bank #0<br />
JTAG<br />
IIC<br />
IIC<br />
(Level Translators)<br />
Altera JTAG<br />
Header<br />
Probe<br />
Points<br />
Probe<br />
Points<br />
HS Serial<br />
LVDS<br />
LVDS<br />
HSMC #1<br />
HSMC #2<br />
Power Power<br />
Connect High Speed Mezzanine Card<br />
(HSMC) to <strong>Dini</strong> <strong>Group</strong> <strong>FPGA</strong> boards<br />
with this adapter.<br />
SMAs for GCC Insertion<br />
JTAG<br />
Altera JTAG<br />
Header<br />
Probe<br />
Points<br />
Probe<br />
Points<br />
HS Serial<br />
(Level Translators)<br />
LEDs for Status, Power<br />
DNMEG_FMC<br />
(VCCO regulators<br />
set to +2.5V, LDO<br />
for MEG Array Signals)<br />
+VADJ<br />
Power<br />
(Level Translators)<br />
IIC<br />
JTAG<br />
Xilinx JTAG<br />
Header<br />
LA/HA/HB Banks<br />
+VADJ<br />
Power<br />
<strong>The</strong> DNMEG_FMC board is a <strong>FPGA</strong><br />
Mezzanine card.<br />
MEG<br />
Array<br />
SelectIO Pins<br />
+VIO (VCCO FOR HB Signals Only)<br />
QSE<br />
Headers<br />
HS Serial<br />
(DP)<br />
Clocking<br />
CLK_UP (C2M)<br />
CLK_DN (M2C)<br />
SMAs for Clock Insertion<br />
PG_M2C, PSNT_M2C<br />
PG_C2M<br />
Power monitors,<br />
daughtercard reset<br />
Clocking Sideband<br />
DNMEG_ARM_TILE<br />
CPLD<br />
(XC9572)<br />
ARM7 / ARM9 / ARM 11<br />
ARM<br />
Test<br />
Chip<br />
38<br />
LEDs for Status, Power<br />
Z Memory<br />
Expansion<br />
PISMO<br />
Y Memory<br />
Expansion<br />
PISMO<br />
ARM Coretile<br />
DN9000 & DN7000 Series<br />
ASIC Prototyping <strong>Boards</strong><br />
(to 50M gates)<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
+1.5V to +3.3V I/O<br />
Y[31:0]<br />
Y[169:150]<br />
Misc Control<br />
(power, clocks,<br />
memory type/sizes,<br />
board ID, etc.)<br />
HWDATA[31:0]<br />
HDRZ<br />
HDRY<br />
JTAG<br />
MEMEXPB [103:0]<br />
MEMEXPA [103:0]<br />
<strong>FPGA</strong>_LED<br />
<strong>FPGA</strong>_GPIO<br />
CPLD Config<br />
JTAG<br />
ARM ICE<br />
Config<br />
ARM ICE<br />
Debug<br />
JTAG<br />
AHB<br />
HDRX<br />
Clocks, Misc control<br />
HADDR[31:0]<br />
HDATA[31:0]<br />
HRDATA[31:0]<br />
Bus Control<br />
MEG Array Expansion<br />
Connector (400-pin)<br />
25<br />
MHz<br />
<strong>FPGA</strong><br />
Xilinx<br />
Spartan 3<br />
XCS5000<br />
(FG900)<br />
100<br />
MHz<br />
USB-OTG<br />
Phy<br />
10/100/1000<br />
Ethernet<br />
Phy<br />
(UCS8601)<br />
Addr<br />
Data<br />
Addr<br />
Data<br />
Addr<br />
USB 2.0<br />
(mini AB)<br />
www.dinigroup.com<br />
Cntl<br />
Cntl<br />
Data<br />
Cntl<br />
AC97 Audio<br />
10/100/1000 base T<br />
Ethernet<br />
RS232<br />
Mouse<br />
Keyboard<br />
JTAG (<strong>FPGA</strong>)<br />
<strong>The</strong> DNMEG_ARM_TILE is an intermediate<br />
host for an ARM RealView<br />
CoreTile. It adds the features and interfaces<br />
necessary to make the ARM9<br />
(or ARM11) processor useful for prototyping.<br />
<strong>The</strong> combination of the DN-<br />
MEG_ARM_TILE with the CoreTile<br />
can be mounted on an ASIC <strong>FPGA</strong><br />
board from <strong>The</strong> <strong>Dini</strong> <strong>Group</strong>, enabling<br />
full-speed system prototyping and<br />
debugging of high gate count ARMbased<br />
systems. With a separate power<br />
supply, the DNMEG_ARM_TILE/<br />
CoreTile combo can also be used<br />
standalone.
DNIOB: High Speed Serial Interfaces<br />
DNIOB_LOOPBACK<br />
DNIOB_CFP<br />
DNIOB_PCIe<br />
DNIOB_QSFP<br />
DNIOB_SFP<br />
DNIOB_SMA<br />
DNIOB_INTERCON<br />
DNIOB_USB3<br />
858 . 454 . 3419 39
SMA<br />
1<br />
GTX<br />
Flash<br />
Flash<br />
Phy<br />
SFP<br />
or<br />
SFP+<br />
8 GTX<br />
GTX<br />
4<br />
GTX<br />
4<br />
4<br />
DDR3 SODIMM<br />
(4GB Max)<br />
D<br />
4<br />
60<br />
E<br />
58<br />
F<br />
130<br />
130<br />
60<br />
40<br />
58<br />
20<br />
24<br />
MHz<br />
G0<br />
(2KHz<br />
40<br />
20<br />
GTX<br />
4<br />
GTX<br />
GTX<br />
8<br />
16<br />
12<br />
95<br />
95<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
24<br />
MHz<br />
Config <strong>FPGA</strong><br />
G1<br />
(2KHz<br />
12<br />
GTX<br />
GTX<br />
NMB<br />
GTX<br />
GTX<br />
4<br />
PCIe<br />
DDR3 SODIMM<br />
(4GB Max)<br />
A<br />
4<br />
4<br />
1 0<br />
24<br />
MHz<br />
B<br />
4<br />
120<br />
C<br />
G2<br />
(2KHz<br />
130<br />
130<br />
1 0<br />
40<br />
40<br />
120<br />
20<br />
40<br />
OSC<br />
G0<br />
8<br />
8<br />
GTX<br />
40<br />
GTX<br />
OSC<br />
PCIe<br />
(Gen1)<br />
MPP Bus<br />
Flash<br />
RGMII<br />
Phy<br />
64<br />
3<br />
CPU CPU<br />
SPI<br />
USB<br />
(3x)<br />
PCIe<br />
SATA<br />
8<br />
RTC<br />
Boot<br />
(host)<br />
2x<br />
RJ45<br />
RJ45<br />
D<br />
2<br />
125<br />
MHz<br />
RS232<br />
93<br />
56<br />
93<br />
93<br />
125<br />
MHz<br />
93<br />
93<br />
93<br />
40<br />
40<br />
DDR2 SODIMM<br />
(4GB Max)<br />
3<br />
3<br />
3<br />
120<br />
SPI<br />
FLASH<br />
16Mb<br />
SPI<br />
FLASH<br />
16Mb<br />
SPI<br />
FLASH<br />
16Mb<br />
LX330<br />
(FF1760)<br />
120<br />
GTP OSC<br />
GTP OSC<br />
1 0 1 0<br />
LX330<br />
(FF1760)<br />
120 120<br />
LX330<br />
(FF1760)<br />
16<br />
Configuration<br />
<strong>FPGA</strong><br />
COMPACT<br />
FLASH<br />
config<br />
114.285 MHz<br />
114.285 MHz<br />
114.285 MHz<br />
QL5064<br />
DDR2 SODIMM<br />
(4GB Max)<br />
164<br />
70<br />
70<br />
1 0<br />
1 0<br />
120<br />
120<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
40<br />
uP Config<br />
Control<br />
Config RS232<br />
USB 2.0<br />
(480 Mb/s)<br />
OSC0<br />
OSC1<br />
CLK2-1<br />
CLK QSE<br />
CLK1-1<br />
CLK1-2<br />
ClK0-1<br />
CLK0-2<br />
config data<br />
DDR2 SODIMM<br />
(4GB Max)<br />
3<br />
120<br />
SPI<br />
FLASH<br />
16Mb<br />
LX330<br />
(FF1760)<br />
40 40<br />
120 120<br />
LX330<br />
(FF1760)<br />
3 140 140<br />
SPI<br />
FLASH<br />
16Mb<br />
SPI<br />
FLASH<br />
16Mb<br />
3<br />
LX330<br />
(FF1760)<br />
120<br />
Step<br />
QL5064<br />
DDR2 SODIMM<br />
(4GB Max)<br />
Step<br />
120<br />
90<br />
90<br />
120<br />
(250<br />
MHz)<br />
MICTOR<br />
34<br />
LX30T,<br />
LX50T,<br />
SX35T,<br />
SX50T,<br />
FX30T,<br />
FX70T<br />
EXT0<br />
sma<br />
EXT1<br />
FBB<br />
FBE<br />
sma sma<br />
250<br />
MHZ<br />
CLK-QSE<br />
PCIe Ref Clock<br />
100MHz<br />
sma<br />
External Input<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
sma<br />
sma<br />
SATA (6 Gb/s)<br />
SATA (6 Gb/s)<br />
sma<br />
SFP Connector<br />
SFP Connector<br />
sma<br />
SMAs<br />
Miscellaneous Peripherals<br />
DNJTAG_USB<br />
JTAG 1<br />
TDI TDO<br />
TMS<br />
USB to JTAG Adapter for in-chassis<br />
<strong>FPGA</strong> reconfiguration<br />
Xilinx<br />
JTAG 2<br />
TDI TDO<br />
USB<br />
(micro-B)<br />
USB<br />
to<br />
JTAG<br />
TDI<br />
TMS<br />
TCK<br />
TDO<br />
TMS<br />
JTAG 3<br />
TDI TDO<br />
TMS<br />
Diligent JTAG SMT1<br />
JTAG 4<br />
TDI TDO<br />
TMS<br />
TCK<br />
PCIe<br />
+12V<br />
DNPCIe-SATA<br />
100<br />
MHz<br />
PCIe Ref Clock<br />
100MHz<br />
sma<br />
2<br />
2<br />
2<br />
SATA (6 Gb/s)<br />
10/100/1000<br />
ETHERNET<br />
(VSC8201)<br />
8-lane PCIe Express to Serial ATA adapter<br />
External Input<br />
0<br />
1<br />
2<br />
3<br />
4<br />
5<br />
6<br />
7<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
16-lane PCIe<br />
Connector<br />
2<br />
2<br />
sma<br />
SATA (6 Gb/s)<br />
sma<br />
sma<br />
sma<br />
SFP Connector<br />
SFP Connector<br />
SMAs<br />
A B C<br />
JTAG<br />
+1.5V to +3.3V I/O<br />
+1.5V to +3.3V I/O<br />
+1.5V to +3.3V I/O<br />
Q F E<br />
MEG Array Expansion<br />
connector (400-pin)<br />
MEG Array Expansion<br />
connector (400-pin)<br />
MEG Array Expansion<br />
connector (400-pin)<br />
10/100/1000<br />
ETHERNET<br />
(VSC8201)<br />
ALL <strong>FPGA</strong>s<br />
(bussed)<br />
ALL <strong>FPGA</strong>s<br />
Reset<br />
<strong>FPGA</strong> F<br />
Virtex 5<br />
<strong>FPGA</strong> E<br />
Virtex 5<br />
<strong>FPGA</strong> D<br />
Virtex 5<br />
MB [35:0]<br />
Spartan 3<br />
MB [163:0]<br />
clock config<br />
<strong>FPGA</strong> C<br />
Virtex 5<br />
<strong>FPGA</strong> B<br />
Virtex 5<br />
<strong>FPGA</strong> A<br />
Virtex 5<br />
Global Clocks<br />
GCLK0<br />
Clock Synth<br />
Si2536<br />
GCLK1<br />
Clock Synth<br />
Si2536<br />
CLK_FB<br />
(from <strong>FPGA</strong> A)<br />
DDR2 SODIMM<br />
(4GB Max)<br />
DDR2 SODIMM<br />
(4GB Max)<br />
Xilinx<br />
Virtex 5T<br />
GCLK2<br />
Clock Synth<br />
Si2536<br />
(zero delay)<br />
Daughtercard D<br />
Daughtercard E<br />
(zero delay)<br />
Daughtercard F<br />
MB48CLK<br />
48MHz<br />
<strong>FPGA</strong> B<br />
<strong>FPGA</strong> E<br />
Ref_CLK<br />
100<br />
MHz<br />
16-lane PCIe<br />
Connector<br />
DNUSB30_USB20<br />
USB 3.0<br />
sma<br />
TX<br />
RX<br />
USB 2.0<br />
DM<br />
DP<br />
ID<br />
Micro - AB<br />
Mini - AB<br />
Aux Power<br />
+5V<br />
+12V<br />
DN9000K10PCIe-8T<br />
JTAG<br />
EE<br />
RS232<br />
Clock Synth<br />
Si5326<br />
Clock Synth<br />
Si5326<br />
Clock Synth<br />
Si5326<br />
LEDs<br />
(8)<br />
Green<br />
<strong>FPGA</strong><br />
8<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
2<br />
5<br />
DDR2 SODIMM<br />
(4GB Max)<br />
123<br />
<strong>FPGA</strong><br />
Virtex-5T<br />
LX50T/LX85T/SX50T<br />
SX95T/FX70T/FX100T<br />
LX110T/LX155T<br />
(FFG1136)<br />
2<br />
GTP<br />
GTP<br />
GTP<br />
GTP<br />
DNPCIe_SATA<br />
200 MHz<br />
OSC<br />
(DDR2)<br />
4<br />
4<br />
4<br />
4<br />
93<br />
Infiniband<br />
QSE<br />
(LX110T/<br />
SX95T<br />
only)<br />
+1.5V to +3.3V I/O<br />
MEG Array Expansion<br />
connector (400-pin)<br />
(top)<br />
USB3.0 Prototyping using GTX via SMAs<br />
sma<br />
SFP Socket (x4)<br />
- TX Fault<br />
- MOD_DEF0<br />
- RATE_SEL<br />
- LOS<br />
(bottom)<br />
1 2 3<br />
0<br />
SFP Signals<br />
not available<br />
with LX50T,<br />
LX85T, SX50T<br />
sma<br />
USB 2.0<br />
Mini - AB<br />
TX<br />
RX<br />
DM<br />
DP<br />
ID<br />
USB 3.0<br />
Micro - AB<br />
Floppy<br />
HDD Power<br />
Connector<br />
+5V<br />
5A<br />
5V<br />
Good<br />
(GRN)<br />
5V to<br />
3.3V<br />
PVBUS 3.3V<br />
1.5A Max<br />
USB Power<br />
DNPCIe_CBL_GEN2<br />
= Differential when paired, but<br />
can be used single ended at<br />
reduced frequency<br />
= SX95T, FX70T, FX100T,<br />
LX110T, LX155T only<br />
= SPI Flash Configuration<br />
Serial<br />
FLASH<br />
(16 Mbit)<br />
sma<br />
EXT Clock<br />
sma<br />
user GTP<br />
Config<br />
EEPROM<br />
23<br />
11<br />
MICTOR<br />
+<br />
Battery<br />
ATX<br />
Power<br />
Supply<br />
+5V<br />
5A<br />
5V to<br />
3.3V<br />
5V<br />
Good<br />
(GRN)<br />
PVBUS 3.3V<br />
1.5A Max<br />
USB Power<br />
Bridge GNE2 PCIe with a iPASS cable<br />
GTX Expansion<br />
Header<br />
USER_R<br />
MEG Array Expansion<br />
connector (400-pin)<br />
128Mb<br />
MEG Array Expansion<br />
connector (400-pin)<br />
128Mb<br />
<strong>FPGA</strong> C<br />
<strong>FPGA</strong> E<br />
<strong>FPGA</strong> F<br />
MEG Array Expansion<br />
connector (400-pin)<br />
10/100/1000<br />
CLK_25<br />
(25 MHz)<br />
96 96<br />
96 96<br />
96 96<br />
SATA II<br />
(device)<br />
USER_L<br />
<strong>FPGA</strong> A<br />
<strong>FPGA</strong> D<br />
<strong>FPGA</strong> B<br />
<strong>FPGA</strong><br />
GTX <strong>FPGA</strong><br />
GTX<br />
<strong>FPGA</strong><br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
DDR3 SODIMM<br />
(4GB Max)<br />
(host)<br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
to 700 MHz)<br />
20 20 73 73<br />
40 74` 74<br />
<strong>FPGA</strong> Q<br />
Virtex-5<br />
Config <strong>FPGA</strong><br />
114.285 MHz<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
to700 MHz)<br />
114.285 MHz<br />
<strong>FPGA</strong><br />
GTX <strong>FPGA</strong><br />
GTX<br />
<strong>FPGA</strong><br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
Virtex-6<br />
LX240T/LX365T<br />
SX315T<br />
LX550T/SX475T<br />
(FF1759)<br />
DDR3 SODIMM<br />
(4GB Max)<br />
Frequency<br />
Synthesizer<br />
(Si5326)<br />
to 700 MHz)<br />
MGT Clock<br />
125 MHz<br />
150 MHz<br />
250 MHz<br />
312.5 MHz<br />
4 - lanes<br />
128Mb<br />
GTX Expansion<br />
Header<br />
128Mb<br />
FLASH<br />
GTX Expansion<br />
Header<br />
128M x 64<br />
DDR2<br />
128Mb<br />
Boot FLASH<br />
Marvell MV78200<br />
FPU FPU<br />
DMA(4x)<br />
10/100/1000 10/100/1000<br />
baseT<br />
RJ45<br />
RS232<br />
USB 2.0<br />
4-lanes<br />
256Mb<br />
SATA II<br />
PCIe (GEN1)<br />
NAND FLASH<br />
PCI EXPRESS<br />
iPASS<br />
Connector<br />
4<br />
4<br />
PCIe<br />
Driver<br />
Ref-Clk Jitter<br />
Attenuator<br />
iPASS<br />
Connector<br />
4<br />
4<br />
PCIe<br />
Driver<br />
DNPCIe_CBL_GEN2 (slot)<br />
iPASS<br />
Connector<br />
4<br />
4<br />
PCIe<br />
Driver<br />
Jitter Ref-Clk<br />
Attenuator<br />
iPASS<br />
Connector<br />
4<br />
4<br />
PCIe<br />
Driver<br />
DNPCIe_CBL_GEN2 (finger)<br />
Finger<br />
PCIe GEN2<br />
(8-lane)<br />
Host<br />
Computer<br />
Slot<br />
4<br />
Ref-Clk<br />
4<br />
PCIe GEN2<br />
(8-lane)<br />
PCIe<br />
Driver<br />
Jitter<br />
Attenuator<br />
PCIe<br />
Driver<br />
4<br />
4<br />
iPASS<br />
Connector<br />
iPASS<br />
Connector<br />
4 lanes<br />
4 lanes<br />
4 lanes<br />
4 lanes<br />
iPASS<br />
Connector<br />
iPASS<br />
Connector<br />
4<br />
4<br />
PCIe<br />
Driver<br />
Jitter<br />
Attenuator<br />
PCIe<br />
Driver<br />
4<br />
Ref-Clk<br />
4<br />
Finger<br />
PCIe GEN2<br />
(8-lane)<br />
40<br />
www.dinigroup.com
SEAM Expansion<br />
DNSEAM_IPASSx4<br />
Add 4 iPass connection to any <strong>Dini</strong>group<br />
board with a SEARAY connector.<br />
DNSEAM_CX4<br />
Add CX4 connection to any <strong>Dini</strong>group<br />
board with a SEARAY connector.<br />
DNSEAM_PCIe<br />
Add an 8-lane GEN1/GEN2 PCI Express<br />
connection to any <strong>Dini</strong>group board with a<br />
SEARAY connector.<br />
DNSEAM_SFP<br />
Expansion card that hosts 8 SFP sockets.<br />
Attaches to the SEARAY GTX Expansion<br />
connectors on the DN2076k10,<br />
DNV6F6PCIe, DNMEG_V6HXT . Adds 8<br />
channels of 1x/2x/4x Fibre Channel,<br />
10/100/1G Ethernet, XAUI, SATA,<br />
Serial RapidI/O (SRIO).<br />
858 . 454 . 3419 41
PC3-1600<br />
PC3-1600<br />
PC3-800<br />
DDR3<br />
PC3-800<br />
DDR3<br />
DDR3<br />
(128M DDR3x 16)<br />
(128M x 16)<br />
PC3-800 PC3-1600<br />
DDR3<br />
DDR3<br />
(128M x 16) (128M x 16)<br />
(128M x 16) (128M x 16)<br />
DDR3 DDR3<br />
DDR3<br />
DDR3<br />
DDR3<br />
DDR3<br />
(128M DDR3 x 16) (128M DDR3 x 16)<br />
( M x 16) ( M x 16)<br />
( M x 16) ( M x 16)<br />
(128M x 16) (128M x 16)<br />
DDR3<br />
DDR3<br />
( M x 16)<br />
( M x 16)<br />
Kintex-7<br />
Kintex-7<br />
7K410T/7K325T/<br />
46<br />
7K410T/7K325T/<br />
46<br />
7K160T<br />
7K160T<br />
Kintex-7<br />
<strong>FPGA</strong> 1<br />
<strong>FPGA</strong> 2<br />
6<br />
(FFG676)<br />
(FFG676)<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 0<br />
(FFG900)<br />
46<br />
8 CFG Bus<br />
46<br />
JTAG<br />
6<br />
1<br />
0 2<br />
Kintex-7<br />
Kintex-7<br />
78<br />
7K410T/7K325T/<br />
46<br />
7K410T/7K325T/<br />
3<br />
7K160T<br />
7K160T<br />
<strong>FPGA</strong> 4<br />
<strong>FPGA</strong> 3<br />
CPLD 4<br />
PCIe<br />
(FFG676)<br />
(FFG676)<br />
DDR3<br />
DDR3<br />
DDR3<br />
DDR3<br />
( M x 16) ( M x 16)<br />
( M x 16) ( M x 16)<br />
DDR3<br />
DDR3<br />
DDR3<br />
DDR3<br />
( M x 16) ( M DDR3 x 16)<br />
( M x 16) ( DDR3 M x 16)<br />
PC3-800<br />
( M x 16)<br />
PC3-800<br />
( M x 16)<br />
I 2 C 2<br />
PC3-1600<br />
PC3-1600<br />
Serial<br />
cfg Prog<br />
5<br />
HPCLK<br />
(FF484)<br />
EEProm<br />
OSC<br />
DDR3 Clocks<br />
(all <strong>FPGA</strong>s)<br />
cfg Prog<br />
5<br />
Flash<br />
HRCLK<br />
<strong>FPGA</strong><br />
OSC<br />
Config<br />
<strong>FPGA</strong> 1<br />
SYSCLK (all <strong>FPGA</strong>s)<br />
4-lane PCIe<br />
PCIe<br />
(GEN1 / GEN2)<br />
SFB Clock (CFG Bus Clocking)<br />
<strong>FPGA</strong><br />
DNK7 F5PCIe<br />
PCIe<br />
Godzilla’s Bad Hair Day<br />
Block Diagram v1.10<br />
High Performance Computing<br />
DNK7F5_8_Cluster<br />
PCIe<br />
Bridge<br />
DNK7_F5PCIe<br />
PCIe (GEN1/GEN2)<br />
4 4 4 4 4<br />
4 4 4<br />
PCIe Fan Out<br />
Switch<br />
PCIe Fan Out<br />
Switch<br />
8 8<br />
PCIe<br />
Xeon E3-1275<br />
(CPU1)<br />
8 GB DDR3<br />
8 GB DDR3<br />
8 GB DDR3<br />
8 GB DDR3<br />
Platform<br />
Controller<br />
Hub<br />
(3420)<br />
6<br />
LAN 1<br />
10/100/1000 base-T<br />
LAN 2<br />
USB 0<br />
USB 1<br />
Video (SandyBridge)<br />
HDD<br />
Up to 6 HDD (SATA3 )<br />
Features<br />
• 5U Rackmount Chassis containing:<br />
- 1 Intel Xeon® E3-1275 processor card<br />
- DNK7_F5PCIe <strong>FPGA</strong> cards each with 5 Xilinx of the largest<br />
Kintex 7 <strong>FPGA</strong>s (7K410T)<br />
• PCIe 4-lane (GEN1/GEN2)<br />
• 40 <strong>FPGA</strong>s in total, 100% dedicated to application<br />
- Other configurations with different CPU to <strong>FPGA</strong> ratios are available<br />
- 2 bays for SATA-2 hard drives<br />
• Processor card<br />
- Intel Xeon® E3-1200 series processors (Sandy Bridge), 3.4 GHz<br />
• Quad-Core, 8MB shared L2 cache<br />
• 4 GB DDR3 memory (4 GB total)<br />
• Options up to 32 GB (32 GB max)<br />
• VGA with standard D-Sub connector<br />
• 10/100/1000BASE-T Ethernet (2 ports)<br />
• USB 2.0 (4 ports total)<br />
- 2 ports on front panel<br />
- 2 ports on back bracket<br />
• Supports most all Linux distributions<br />
• DNK7_F5PCIe <strong>FPGA</strong> HPC Acceleration card<br />
- PCI Express (4-lane) <strong>FPGA</strong>-based algorithm acceleration<br />
peripheral with 5 Kintex-7 <strong>FPGA</strong>s<br />
• 4 Xilinx Kintex-7 <strong>FPGA</strong>s: 7K410T-1 (FFG676)<br />
- 7K410T-3,-2,-1, 7K325T-3,-2,-1, or 7K160T-3,-2,-1<br />
• 1 Xilinx Kintex-7 <strong>FPGA</strong>: 7K325T-1 (FFG900)<br />
- 7K410T-3,-2,-1 or 7K325T-3,-2,-1<br />
<strong>The</strong> DNK7_F5_8_Cluster is a complete, 5U rack mount <strong>FPGA</strong> acceleration<br />
cluster. <strong>The</strong> standard configuration contains the following:<br />
Trenton TSB7053 Xeon processor card<br />
8 DNK7_F5PCIe Kintex 7 <strong>FPGA</strong> cards with 5 7K410T-1 <strong>FPGA</strong>s per card.<br />
1.5 TB SATA II Hard Drive<br />
This system contains the maximum number of cost effective <strong>FPGA</strong> that<br />
can be reasonability integrated into a 5U chassis. Power and cooling are<br />
the constraining variables. High performance data paths between <strong>FPGA</strong><br />
boards enable data movement under algorithmic control that is wholly<br />
separate from the host processor, enabling <strong>FPGA</strong>-based acceleration of<br />
whole new classes of data intensive algorithms.<br />
In short, the DNK7_F5_8_Cluster is a massive number of large, low<br />
cost <strong>FPGA</strong>s integrated with an excellent dual Xeon-based processor<br />
host.<br />
A partial list of possible applications includes:<br />
Bioinformatics<br />
Genomic Search<br />
Financial Analytics<br />
- Low Latency Analysis<br />
- Derivative Calculations<br />
Image Processing<br />
Signal Processing<br />
Radar<br />
Scientific Computing<br />
Video Compression<br />
Encryption/Decryption (Cryptography)<br />
42<br />
www.dinigroup.com
DNK7_F5PCIe<br />
PC3-800<br />
DDR3<br />
(256M DDR3 x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
PC3-1600<br />
DDR3<br />
(256M DDR3 x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
PC3-800<br />
DDR3<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
PC3-1600<br />
DDR3<br />
(256M DDR3x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
PC3-800<br />
DDR3<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
PC3-1600<br />
DDR3<br />
(256M DDR3x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
Kintex-7<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 0<br />
(FFG900)<br />
46<br />
Kintex-7<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 1<br />
(FFG676)<br />
46<br />
6<br />
Kintex-7<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 2<br />
(FFG676)<br />
LED<br />
46<br />
46<br />
8<br />
CFG Bus<br />
JTAG<br />
1<br />
0 2<br />
CPLD 4<br />
PCIe<br />
3<br />
78<br />
Kintex-7<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 4<br />
(FFG676)<br />
6<br />
46<br />
Kintex-7<br />
7K410T/7K325T<br />
<strong>FPGA</strong> 3<br />
(FFG676)<br />
PCIe<br />
Bridge<br />
(FF484)<br />
I 2 C<br />
2<br />
Serial<br />
EEProm<br />
Flash<br />
<strong>FPGA</strong><br />
Config<br />
DDR3<br />
DDR3<br />
DDR3<br />
DDR3<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M DDR3 x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M x 16)<br />
(256M x 16)<br />
DDR3<br />
(256M DDR3 x 16)<br />
PC3-800<br />
(256M x 16)<br />
PC3-800<br />
(256M x 16)<br />
PC3-1600<br />
PC3-1600<br />
cfg<br />
cfg<br />
Prog<br />
OSC<br />
Prog<br />
OSC<br />
<strong>FPGA</strong> 1<br />
5<br />
5<br />
HPCLK<br />
HRCLK<br />
DDR3 Clocks<br />
(all <strong>FPGA</strong>s)<br />
SYSCLK (all <strong>FPGA</strong>s)<br />
PCIe<br />
4-lane PCIe<br />
(GEN1 / GEN2)<br />
PCIe<br />
<strong>FPGA</strong><br />
SFB Clock (CFG Bus Clocking)<br />
<strong>The</strong> DNK7_F5PCIe is Xilinx Kintex-7 based <strong>FPGA</strong> board optimized for algorithmic acceleration applications requiring <strong>FPGA</strong>s with high performance local<br />
memory. Data movement to/from the <strong>FPGA</strong> grid is accomplished via a fixed 4-lane, GEN1/GEN2 PCIe bridge. Each field Kintex-7 <strong>FPGA</strong> (<strong>FPGA</strong>s 1-4<br />
in the block diagram) has five separate 256M x 16 DDR3 (4 Gb) memories. <strong>The</strong> Dataflow Manager <strong>FPGA</strong> (<strong>FPGA</strong> 0 in the block diagram) has six 256M x<br />
16 DDR3 memories.<br />
Features<br />
• PCI Express (4-lane) <strong>FPGA</strong>-based algorithm acceleration<br />
peripheral with 5 Kintex-7 <strong>FPGA</strong>s<br />
- 4 Xilinx Kintex-7 <strong>FPGA</strong>s: 7K325T-1 (FFG676)<br />
- 1 Xilinx Kintex-7 <strong>FPGA</strong>: 7K325T-1 (FFG900)<br />
• Fixed 4-lane PCIe interface and controller<br />
- PCIe GEN1/GEN2<br />
- Full mastering DMA<br />
• 2 transmit (host memory -> card)<br />
• 2 receive (card -> host memory)<br />
• Xilinx <strong>FPGA</strong> Kintex-7 7K325T-1 – 5 total user <strong>FPGA</strong>s<br />
- 407,600 flip-flops per <strong>FPGA</strong><br />
• 203K flips-flops with 6-input LUT<br />
- 840, 25x18 multipliers + 48-bit accumulator per <strong>FPGA</strong><br />
- 890, 18 Kbit block RAM (2 Mbytes) per <strong>FPGA</strong> (or 445,<br />
36 Kbit blocks)<br />
• Fully dual-ported<br />
• Each block RAM configurable as:<br />
32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8),<br />
2K × 18 (or 16), 1K × 36 (or 32), or 512 × 72 (or 64)<br />
- Options for the larger 7K410T when available.<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect is single-ended<br />
- Source synchronous <strong>FPGA</strong> -> <strong>FPGA</strong> frequency: 400 MHz<br />
• 400 Mb/s per pin when using DDR<br />
• Config Bus (CFG) connects all Kintex-7 <strong>FPGA</strong>s (8 signals)<br />
- 90MHz<br />
• 5 separate 256Mb x 16 DDR3 memories for each field <strong>FPGA</strong><br />
- 3 memories PC3-1600<br />
- 2 memories PC3-800<br />
- Each memory has separate address, data, and control<br />
• 6 separate 256Mb x 16 DDR3 memories for Dataflow<br />
Manager <strong>FPGA</strong><br />
- 3 memories PC3-1600<br />
- 3 memories PC3-800<br />
- Each memory has separate address, data, and control<br />
• Two independent low-skew global clock networks distributed<br />
differentially and balanced<br />
• Fast and Painless <strong>FPGA</strong> configuration via PCIe<br />
- On-board battery for AES bitstream encryption<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope, and other third-party debug solutions<br />
• <strong>FPGA</strong>-controlled LEDs<br />
- Enough light to use as a LED-based flashlight<br />
858 . 454 . 3419 43
(128M x 16)<br />
16<br />
(128M x 16)<br />
16<br />
Config<br />
EE<br />
User<br />
EEPROM<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6<br />
77<br />
77<br />
77<br />
77<br />
77<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
<strong>FPGA</strong> 0 <strong>FPGA</strong> 1 <strong>FPGA</strong> 2 <strong>FPGA</strong> 3 <strong>FPGA</strong> 4 <strong>FPGA</strong> 5<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
MB (upper) 8<br />
64 MB (lower)<br />
64<br />
64<br />
64<br />
64<br />
64 77<br />
8<br />
Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6<br />
77<br />
77<br />
77<br />
77<br />
77<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
LX150<br />
<strong>FPGA</strong> 11 <strong>FPGA</strong> 10 <strong>FPGA</strong> 9 <strong>FPGA</strong> 8 <strong>FPGA</strong> 7 <strong>FPGA</strong> 6<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
(FGG484)<br />
32<br />
32<br />
16<br />
16<br />
16<br />
16<br />
16<br />
16<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
DDR3 - 800<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
(128M x 16)<br />
PCIe<br />
100MHz Clock<br />
Bridge<br />
ALL <strong>FPGA</strong>s<br />
Q<br />
MB Clock<br />
4-lane PCIe (GEN1/GEN2)<br />
PCIe<br />
Expansion Board to Board<br />
Cards / Dataflow<br />
Top<br />
Bottom<br />
QSE<br />
QSE<br />
4 4 4 4<br />
data<br />
GTP<br />
77<br />
Spartan - 6<br />
LX150T<br />
User <strong>FPGA</strong><br />
Dataflow<br />
data<br />
Manager<br />
77<br />
DM<br />
GTP<br />
GTP<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
data<br />
High Performance Computing<br />
DNBFC_S12_12_Cluster<br />
DDR3 - 800<br />
DDR3 - 800<br />
Each line represents 4 GTX<br />
serial I/O connections<br />
3.125 GB/s per line<br />
BFC_S10_PCIe<br />
PCIe (GEN1)<br />
4 4 4 4 4 4<br />
4 4 4 4<br />
PCIe Fan Out<br />
Switch<br />
PCIe Fan Out<br />
Switch<br />
8 8<br />
PCIe<br />
QPI<br />
Xeon<br />
(CPU2)<br />
Xeon<br />
(CPU1)<br />
2 GB DDR3<br />
2 GB DDR3<br />
2 GB DDR3<br />
2 GB DDR3<br />
2 GB DDR3<br />
2 GB DDR3<br />
Platform<br />
Controller<br />
Hub<br />
(3420)<br />
6<br />
LAN 1<br />
10/100/1000 base-T<br />
LAN 2<br />
USB 0<br />
USB 1<br />
Video (XGI)<br />
HDD<br />
Up to 6 HDD (SATA 3)<br />
Features<br />
• 5U Rackmount Chassis containing:<br />
- 1 Intel Xeon E3-1275 processor card<br />
- 12 DNBFC_S12_PCIe <strong>FPGA</strong> cards each with 13 Xilinx of the<br />
largest Spartan-6 <strong>FPGA</strong>s (XC6SLX150)<br />
• PCIe 4-lane (GEN1)<br />
• 156 <strong>FPGA</strong>s in total, 100% dedicated to application<br />
- Other configurations with different CPU to <strong>FPGA</strong> ratios are available<br />
- 2 bays for SATA-3 hard drives<br />
• Processor card<br />
- Intel Xeon E3-1200 series (Sandy Bridge) processors, 3.4 GHz<br />
• Quad-Core, 8MB shared L2 cache<br />
• 4 GB DDR3 memory (4 GB total)<br />
- Options up to 32 GB (32 GB max)<br />
• VGA with standard D-Sub connector<br />
• 10/100/1000BASE-T Ethernet (2 ports)<br />
• USB 2.0 (4 ports total)<br />
- 2 ports on front panel<br />
- 2 ports on back bracket<br />
• Supports most all Linux distributions<br />
<strong>The</strong> DNBFC_S12_12_Cluster is a complete, 5U rack mount <strong>FPGA</strong> acceleration<br />
cluster. <strong>The</strong> standard configuration contains the following:<br />
Trenton TSB7053 Xeon processor card<br />
12 DNBFC_S12_PCIe Spartan-6 <strong>FPGA</strong> cards with 13 LX150 <strong>FPGA</strong>s per card.<br />
2 TB SATA II Hard Drive<br />
This system contains the maximum number of cost effective <strong>FPGA</strong> that<br />
can be reasonability integrated into a 5U chassis. Power and cooling are<br />
the constraining variables. High performance data paths between <strong>FPGA</strong><br />
boards enable data movement under algorithmic control that is wholly<br />
separate from the host processor, enabling <strong>FPGA</strong>-based acceleration of<br />
whole new classes of data intensive algorithms.<br />
In short, the DNBFC_S12_12_Cluster is a massive number of large,<br />
low cost <strong>FPGA</strong>s integrated with an excellent dual Xeon-based processor<br />
host. High speed serial cables between <strong>FPGA</strong> cards add as much a 5<br />
GB/s data throughput within the chassis.<br />
A partial list of possible applications includes:<br />
Bioinformatics<br />
Genomic Search<br />
Financial Analytics<br />
- Low Latency Analysis<br />
- Derivative Calculations<br />
Image Processing<br />
Signal Processing<br />
Radar<br />
Scientific Computing<br />
Video Compression<br />
Encryption/Decryption (Cryptography)<br />
44<br />
www.dinigroup.com
DNBFC_S12_PCIe<br />
Expansion<br />
Cards<br />
/<br />
Board to Board<br />
Dataflow<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
Top<br />
Bottom<br />
QSE<br />
QSE<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
DDR3 - 800<br />
(128M x 16)<br />
DDR3 - 800<br />
(128M x 16)<br />
data<br />
16<br />
data<br />
16<br />
GTP<br />
GTP<br />
Spartan - 6<br />
LX150T<br />
User <strong>FPGA</strong><br />
Dataflow<br />
Manager<br />
GTP<br />
4 4 4 4<br />
DM<br />
77<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 0<br />
(FGG484)<br />
64<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 11<br />
(FGG484)<br />
77<br />
MB (upper)<br />
MB (lower)<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 1<br />
(FGG484)<br />
8<br />
8<br />
64<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 10<br />
(FGG484)<br />
77<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 2<br />
(FGG484)<br />
64<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 9<br />
(FGG484)<br />
77<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 3<br />
(FGG484)<br />
64<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 8<br />
(FGG484)<br />
77<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 4<br />
(FGG484)<br />
64<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 7<br />
(FGG484)<br />
77<br />
77<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 5<br />
(FGG484)<br />
Spartan - 6<br />
LX150<br />
<strong>FPGA</strong> 6<br />
(FGG484)<br />
64 77<br />
32<br />
32<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
16<br />
data<br />
Config<br />
EE<br />
User<br />
EEPROM<br />
PCIe<br />
Bridge<br />
Q<br />
4-lane PCIe (GEN1/GEN2)<br />
DDR3 - 800<br />
(128M x 16)<br />
100MHz Clock<br />
ALL <strong>FPGA</strong>s<br />
MB Clock<br />
DDR3 - 800<br />
(128M x 16)<br />
JTAG<br />
0<br />
DM<br />
1 2<br />
11<br />
10<br />
3<br />
9<br />
4<br />
5<br />
8<br />
6<br />
7<br />
DDR3 - 800<br />
(128M x 16)<br />
Frequency<br />
Synthesizer<br />
31.25 MHz-<br />
350 MHz<br />
DDR3 - 800<br />
(128M x 16)<br />
CLK A<br />
ALL <strong>FPGA</strong>s<br />
DDR3 - 800<br />
(128M x 16)<br />
Battery<br />
Bitstream<br />
Encryption<br />
DDR3 - 800<br />
(128M x 16)<br />
PCIe<br />
Features<br />
• PCI Express (4-lane) <strong>FPGA</strong>-based algorithm acceleration peripheral<br />
- 12 of the largest Xilinx Spartan-6 <strong>FPGA</strong>s: 6SLX150-2<br />
• 12, 128M x 16 (2Gb) DDR3-800 memories (1 per <strong>FPGA</strong>)<br />
- 1 Xilinx Spartan-6 <strong>FPGA</strong>s: 6SLX150T-2<br />
• 2, 128M x 16 (2Gb) DDR3-800 memories<br />
• Fixed 4-lane PCIe interface and controller<br />
- PCIe GEN1/GEN2<br />
- Full mastering DMA<br />
• 2 transmit (host memory -> card)<br />
• 2 receive (card -> host memory)<br />
• Xilinx <strong>FPGA</strong> Spartan-6 LX150-2 – 12 total<br />
- 184,464 flip-flops per <strong>FPGA</strong><br />
• 92K flips-flops with 6-input LUT<br />
- 180, 18x18 multipliers + 48-bit accumulator per <strong>FPGA</strong><br />
- 268, 18 Kbit block RAM (603 Kbytes) per <strong>FPGA</strong><br />
• Fully dual-ported<br />
• Each block RAM configurable as:<br />
- 16K×1, 8K×2, 4K×4, 2K×8/9, 1K×16/18, or 512 x 32/36<br />
- Options for LX150-1L (lower power) or LX150-3 (higher frequency)<br />
• Also LX150T-3,-4<br />
- Options for LX100, LX75, LX45, LX25 (lower cost)<br />
• <strong>FPGA</strong> to <strong>FPGA</strong> interconnect single-ended<br />
- Source synchronous <strong>FPGA</strong> -> <strong>FPGA</strong> frequency: 150MHz<br />
• 300 Mb/s per pin when using DDR<br />
• Main Bus (MB) connects all Spartan-6 <strong>FPGA</strong>s (8 signals)<br />
- 90MHz<br />
• 128Mb x 16 fixed external DDR3 memory dedicated to each field <strong>FPGA</strong> (12 total)<br />
• 2 – 128Mb x 16 fixed external DDR3 memories dedicated to USER<br />
Dataflow Manager <strong>FPGA</strong><br />
- DDR3-800 is stuffed. VCCINT is set to ‘Extended Performance’ operating range:<br />
• With LX150-2, LX150T-2: 667 Mbps (333.5 MHz)<br />
Designed for High Performance Computing (HPC) applications, the DNBFC_S12_PCIe is a <strong>FPGA</strong>-based<br />
peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost effective<br />
Xilinx Spartan-6 <strong>FPGA</strong>s. Data movement to/from the <strong>FPGA</strong> grid is accomplished via a fixed 4-lane,<br />
GEN1/GEN2 PCIe bridge. Each Spartan-6 <strong>FPGA</strong> has its own 128M x 16 DDR3 memory capable of clocked<br />
speeds up to 400MHz (800 Mb/s per data pin). Two additional 128M x 16 DDR3 memories are connected to<br />
the USER Dataflow Manager <strong>FPGA</strong> (LX150T) for bulk data storage.<br />
- 10.67 Gb/s maximum data rate<br />
• With LX150-3, LX150T-3,LX150T-4: 800 Mbps (400 MHz)<br />
- 12.8 Gb/s maximum data rate<br />
- Full support for <strong>FPGA</strong> memory block controller (MBC)<br />
• Up to 8 open banks<br />
• Configurable multi-port interface to <strong>FPGA</strong> fabric<br />
- 32-, 64-, or 128-bit data bus<br />
• Easy implementation with Xilinx CORE Generator<br />
• Expansion via high speed, low-power GTP transceivers (LX150T)<br />
- 3.125 Gb/s per lane, each direction with -3 or -4 (TX and RX)<br />
- 2.7 Gb/s per lane, each direction with -2 (TX and RX)<br />
- 4 lanes (4 RX and 4 TX) for daisy chain left<br />
- 4 lanes (4 RX and 4 TX) for daisy chain right<br />
- Board to board data communication<br />
• >1 GB/s per connector TX<br />
• >1 GB/s per connector RX<br />
• Non-proprietary, off-the-shelf Samtec cable assembly<br />
- Off-board daughter cards<br />
• Three independent low-skew global clock networks distributed<br />
differentially and balanced<br />
- G0: programmable in 1 MHz increments (ICS84314 clock synthesizer)<br />
• 32 MHz to 350 MHz<br />
- G1: 100MHz PCIe reference<br />
- G2: Main Bus (MB) clock<br />
• Fast and Painless <strong>FPGA</strong> configuration via PCIe<br />
- On-board battery for AES bitstream encryption<br />
- Unique Device DNA identifier for design authentication<br />
• Full support for embedded logic analyzers via JTAG interface<br />
- ChipScope, and other third-party debug solutions<br />
• <strong>FPGA</strong>-controller LEDs<br />
- Enough for emergency lighting in a small parking structure<br />
858 . 454 . 3419 45
IP - TCP Offload (TOE)<br />
FIX Data Stream<br />
10GbE Ethernet<br />
Input to Output<br />
10GbE packet latency<br />
IP - PCIe (Gen1,2,3) Slowdown<br />
PCIe Clock Slowdown<br />
Pin Multiplexing<br />
<strong>FPGA</strong> 0 <strong>FPGA</strong> 1<br />
Logic<br />
data<br />
D<br />
SET<br />
Q<br />
data<br />
data<br />
SET<br />
D Q<br />
data<br />
Logic<br />
CLR Q<br />
DATA_P/N[18:0]<br />
CLR<br />
Q<br />
DNLVDS_PINMUX_TX<br />
DNLVDS_PINMUX_RX<br />
clock<br />
clock<br />
CLK_SS_P/N<br />
MMCM<br />
System clock<br />
MMCM<br />
Overview<br />
CLK<br />
Oscillator<br />
<strong>The</strong> <strong>Dini</strong> <strong>Group</strong> LVDS IO Pin Multiplexing design (DNLVDS_PINMUX) is intended to ease the<br />
strain of prototyping an ASIC design that spans multiple <strong>FPGA</strong>s by providing a low-latency IO<br />
pin multiplexing design. A latency of one clock cycle is achievable end-to-end, so the multiplexing<br />
essentially becomes invisible to the ASIC design. IO rates are maximized to allow for the highest<br />
internal frequency possible. Eye detection training and real-time eye monitoring are implemented<br />
inside the receiver module.<br />
858 . 454 . 3419 47
DINI GROUP | 7469 Draper Ave. La Jolla, CA 858.454.3419 | www.dinigroup.com | sales@dinigroup.com