FPGA Boards - The Dini Group

LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
LED
(x4)
Config PROM
Frequency
Synths (Si5326)
Frequency
Synths (Si5326)
Frequency
Synths (Si5326)
COMPACT FLASH
FPGA
CONFIGURATION
Stratix IV
DN7020K10
+1.5V to +3.3V I/O
DC0
MEG Array Expansion
Connector (400-pin)
DIMM_F1
DDR2 SODIMM
(4GB max)
DIMM_F2
DDR2 SODIMM
(4GB max)
DIMM_F3
DDR2 SODIMM
(4GB max)
+1.5V to +3.3V I/O
DC2
MEG Array Expansion
Connector (400-pin)
MICTOR
Boot
EPROM
RS232
serial
port
SMA
SMA
SMA
SMA
12
12
12
62 24 61
190 120 120 120 190
SPI Flash
SPI Flash
SPI Flash
(16Mb)
(16Mb)
(16Mb)
Stratix IV
50 Stratix IV
51 Stratix IV
50 Stratix IV
50 Stratix IV
FPGA F0 FPGA F1 FPGA F2 FPGA F3 FPGA F4
50
4SE820
4SE820
62 24 61
62 24 61
62 24 61
184
188
186
48
48
48
48
48
48
46 50
44 51
46 50
46
4SE820
4SE820
4SE820
50
51
50
50
51
50
48
48
48
48
48
48
138
140
138
48
48
48
48
48
48
48
48
Stratix IV
Stratix IV
Stratix IV
Stratix IV
Stratix IV
38
39
38
38
FPGA F5 FPGA F6 FPGA F7 FPGA F8 FPGA F9
38
39
38
38
4SE820
4SE820
4SE820
4SE820
4SE820
38
48
48
Stratix IV
Stratix IV
Stratix IV
Stratix IV
Stratix IV
FPGA F10
38
FPGA F11
39
FPGA F12
38
FPGA F13
37
FPGA F14
38
39
38
36
4SE820
4SE820
4SE820
4SE820
4SE820
38
48
48
Stratix IV
50 Stratix IV
50
FPGA F15 FPGA F16 FPGA F17 FPGA F18 FPGA F19
4SE820
4SE820
40 50
40 40 46
Stratix IV
51 Stratix IV
51 Stratix IV
51
51
51
51 4SE820
51 4SE820
51 4SE820
SPI Flash
(16Mb)
38
38
50
24 23 24
24 23 24
24 23 24
24 23 24
39
39
SPI Flash
(16Mb)
39
39
51
24 23 24
24 23 24
24 23 24
24 23 24
138
140
138
48
48
48
48
48
48
48
48
48
38
38
48
48
48
48
48
48
SPI Flash
(16Mb)
38
38
51
24 23 24
24 23 24
24 23 24
24 23 24
140
140
138
48
48
48
48
48
48
50
50
38
36
50
48
48
38
48
48
37
48
48
50
21 21 21
21 21 21
21 21 21
21 21 21
MBUS48B
180
184
180
Bus
Switch
47
47
48
48
Bus
Switch
47
47
48
48
Bus
Switch
47
47
48
48
47
47
48
48
Bus
Switch
DC3
MEG Array Expansion
Connector (400-pin)
DC4
MEG Array Expansion
Connector (400-pin)
DC5
MEG Array Expansion
Connector (400-pin)
DC6
MEG Array Expansion
Connector (400-pin)
+1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O
34
Main Bus
Connector
SMA
SMA
F4
40
40
MICTOR
MBUS48A
MBUS48B
MBCLK
GCLK0
(to all FPGA’s)
GCLK1
(to all FPGA’s)
GCLK2
(to all FPGA’s)
DCGCLK0
(to all FPGA’s)
CY7C68013
uP Configuration
controller
SRAM
128Kb x 8
Flash
1 M x 8
Config
FPGA
48 MHz
8
LCD
Control
Panel
USB 2.0
(type b)
RS232
Reset
96
96
SMA
CFPGA Div Clk
CFPGA Step Clk
FPGA F19
SMA
CFPGA Div Clk
CFPGA Step Clk
FPGA F19
SMA
CFPGA Div Clk
CFPGA Step Clk
FPGA F19
G0 Si5326
FPGA F1
4 Serial
Ports
(Tx/Rx)
MEG Array Expansion
Connector (400-pin)
SMA
PLL
DC10
SMA
DC0
DC3
+1.5V to +3.3V I/O
Features
20
JTAG
www.dinigroup.com
0
5
1
6
2
7
10 11 12 13 14
15
16
17
3
8
18
4
9
19
190 120 120 48
DC1
DIMM F16
DIMM F17
MEG Array Expansion
Connector (400-pin)
+1.5V to +3.3V I/O
• USB2.0-hosted logic prototyping system
with 2-20 Altera Stratix IV FPGAs
- Stratix IV 4SE530 or 4SE820 in high I/O
package (FF1760)
- Backwards compatible with the Stratix-3,
3SL340
- 100% FPGA resources available for user application
• 130M+ ASIC gates (reasonable ASIC
measure) with twenty 4SE820s
- 82M+ with twenty 4SE530s
• FPGA to FPGA interconnect is single-ended or LVDS
- 600 MHz LVDS chip-to-chip DDR (1.2 Gb/s)
- Reference designs for integrated I/O pad
ISERDES/OSERDES
• 10x FPGA to FPGA pin multiplexing
per LVDS pair
• Greatly simplified logic partitioning
• Source synchronous clocking for LVDS
• Main Busses for global connectivity:
- Main Bus A (MBUS48A), all FPGAs: 48
single-ended signals
- Main Bus B (MBUS48B), all FPGAs: 48
single-ended signals
• Auspy AES models for partitioning assistance
- Hooks for other third-party partitioning solutions
• 6 separate DDR2 SODIMMs (350MHz)
- 64-bit data width, 350MHz operation
- PC2-5300
- Addressing/power to support 4GB in each
socket
- DDR2 Verilog/VHDL reference design
provided (no charge)
- DDR2 SODIMM data transfer rate: 32Gb/s
- Alternate pin compatible memory cards
available:
• QDR SSRAM, Mictor, RLDRAM I,
RLDRAM II, SSRAM, DDR3, DDR1,
interconnect, SDRAM DRAM,
FLASH, USB PHY, and others
• SODIMM Daughtercard expansion
- DNSODM200_Mictor - Mictor + 0.1” breakout
- DNSODM200_Flash - two 4M x 32 flash chips
DDR2 SODIMM
(4GB max)
DDR2 SODIMM
(4GB max)
= LVDS when paired, but can be used
single-ended at reduced frequency
120 190
DIMM F18
DDR2 SODIMM
(4GB max)
- DNSODM200_Quadmic - Mictors
- More...
• 3 board-level global clock networks (GCLK[2:0])
- Separate programmable synthesizers for
each network (Si5326)
• Ultra-low jitter
• 2 kHz – 710 MHz
• User configurable via Compact FLASH or USB
- Alternate clock sources:
• Config FPGA
- single-step
- Divide
• SMA for external clock insertion
• 4 Daughter Card global clock networks
(DC_GCLK[3:0]). Select from:
- Clock from daughter card with PLL for
zero-delay (ICS8745B-21)
• DC_GCLK0: Select DC0 or DC3 as source
• DC_GCLK1: Select DC2 or DC4 as source
• DC_GCLK2: Select DC5 or DC7 as source
• DC_GCLK3: Select DC1 or DC8 as source
- SMA for external clock insertion
- Selected FPGA outputs
• DC_GCLK0: Select GCLK0 or
FPGA1 as source
• DC_GCLK1: Select GCLK1 or
FPGA8 as source
• DC_GCLK2: Select GCLK2 or
FPGA13 as source
• DC_GCLK3: Select FPGA14 or
FPGA13 as source
• 8, 400-pin MEG-Array connectors (FCI) for
daughter card (DC) expansion
- 190 single-ended on DC0,1,2,7
- 47 LVDS pairs (FPGA -> DC), 48 LVDS
pairs (DC -> FPGA) on DC[6:3]
• Can be used as 190 single ended signals
- 600MHz on all signals with LVDS
- Reset, presence detect
- Supplied power rails (fused):
• +12V (24W max)
• +5V (10W max)
MEG Array Expansion
Connector (400-pin)
+1.5V to +3.3V I/O
DC7
Bus
Switch
34
F19
DCGCLK1
(to all FPGA’s)
DCGCLK2
(to all FPGA’s)
DCGCLK3
(to all FPGA’s)
G1 Si5326
FPGA F8
G2 Si5326
FPGA F13
FPGA F13
FPGA F14
• +3.3V (10W max)
- Pin multiplexing to/from daughter cards
using ISERDES/OSERDES and LVDS
(up to 10x)
• Fast and Painless FPGA configuration
- Compact FLASH, and/or USB
- Integrated sanity checks on configuration files
- Accelerated configuration readback
• Custom base plate (standard) and optional
rackmount chassis
- Provides protection from those drooling
engineers
• 4, RS232 ports for embedded uP debug
- Accessible from all FPGAs
• Full support for embedded logic analyzers
via JTAG interface
- SignalTap, and other third party tools
• Convert a pair of MEG-Array expansion
connectors to interconnect with the
DNMEG_Intercon.
• MEG-Array Daughtercard Expansion
- DNMEG_Obs - breakout/observation
- DNMEG_Intercon - more interconnect
- More...
• Enough status LEDs to adequately illuminate
a Twisted Sister concert.
PLL
SMA
PLL
SMA
PLL
DC2
DC4
DC5
DC7
DC1
DC6