FPGA Boards - The Dini Group

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116 116 A G B F 38 C E 38 39 D 39 38 40 40 40 40 40 40 40 38 59 59 FPU FPU 4 4 1 4 4 4 4 4 4 iPASS Cable (3’-18’) 4 Host Computer PCIe Slot (8-lane) Virtex - 6 DN2076K10 18 18 MEG Array Expansion MEG Array Expansion connector (400-pin) connector (400-pin) 96 96 96 96 FPGA A Virtex-6 LX550T / LX760 38 38 117 117 DDR3 SODIMM (4GB Max) 130 FPGA B Virtex-6 LX550T / LX760 SPI Flash 137 137 IDC Connector 16 FPGA C Virtex-6 LX550T / LX760 96 96 117 117 DDR3 SODIMM (4GB Max) 130 FPGA G Virtex-6 LX240T/LX365T SX315T (FF1759) SX475T/LX550T GTX Expansion Header 10GbE to XAUI QT2225 10GbE to XAUI QT2225 SFP+ Socket SFP+ Socket SFP+ Socket SFP+ Socket USB 3.0/2.0 10GbE Ethernet 10GbE Ethernet MEG Array Expansion connector (400-pin) 96 96 FPGA D Virtex-6 LX550T / LX760 157 157 117 117 168 168 FPGA E Virtex-6 LX550T / LX760 160 160 FPGA F Virtex-6 LX550T / LX760 MAIN BUS [51:0] SEARAY RGMII 10/100/1000 Phy RJ45 SFP 10/100/1000 base - T sma 1 2 3 0 SMA FPGA A FPGA D FPGA G FPGA B FPGA C FPGA E FPGA A USER_T USER_R 130 DDR3 SODIMM (4GB Max) JTAG 37 37 NMB FPGA A FPGA B FPGA C FPGA D FPGA E FPGA F FPGA G Config FPGA Virtex-6 (FF1156) SPI Flash 4 52 PCI Express Cable (GEN 2) PCIe (GEN1 / GEN2) PCIe Cable Adapter Board Features • Hosted via Config FPGA 24 MHz 24 MHz 24 MHz FPGA F FPGA D FPGA B CLK_25 (25 MHz) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) USER_L G0 (2KHz to 700 MHz) G1 (2KHz to700 MHz) G2 (2KHz to 700 MHz) 10/100/1000 baseT RJ45 USB 2.0 (3x) RS232 10/100/1000 Phy SATA II (host) 2x RGMII OSC USB DMA(4x) SATA RTC MPP Bus PCIe PCIe (Gen1) 4 - lanes Marvell MV78200 4-lanes PCIe (GEN1) PCI Express Cable (GEN 1) - 4-lane GEN1 PCIe (v1.1) slot - USB2.0 - 10/100/1000BASE-T Ethernet - Stand alone • Up to seven of the largest Xilinx Virtex-6 FPGAs - Six Xilinx Virtex-6 FPGAs (FF1760) from the following list: • LX760-2,-1,-1L(fastest to slowest), LX550T-2,-1,-1L - One Xilinx Virtex-6T FPGA (FF1759) from the following list: • LX550T-2,-1,-1L, SX475T-2,-1,-1L,SX315T-3,-2,-1,-1L • LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L - 50A VCCINT power per FPGA • 37+ million ASIC gates (ASIC measure) when stuffed with 6 Virtex-6 LX760 and 1 LX550T • 24, GTX low-powered transceivers: - 65 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1 - Dual AMCC QT2225-2 Dual Port Serial 10Gbps-to-XAUI Transceivers • Four SFP+ sockets for any of the following interfaces: - 10 Gigabit Optical Ethernet • 10GBase-SR 10GBASE-LR 10 GBASE-LRM 10GBASE-ER • 10 Gigabit Copper Ethernet: 10GBASE-R direct attach - 10 Gigabit Sonet: 10GBase-LW - 10 Gigabit FibreChannel - SFP socket - 4 channels using SMA connectors - 16 SMAs in total - 4-lane PCIe GEN1/GEN2 prototyping via iPASS cable - 2 SATA II ports: 1 host and 1 device CPU CPU 64 3 8 Third Party debug connector 128M x 64 DDR2 128Mb SPI Boot FLASH 256Mb NAND FLASH Boot (host) SATA II (device) = LVDS when paired, but can be run single-ended at reduced frequency - GTX Expansion header with LX550T/SX475T (SEARAY connector) - 8-lanes • FPGA to FPGA interconnect is LVDS - 1.3 Gb/s when using DDR with -2 speed grade • 1.0 Gb/s with -1 speed grade - LVDS pairs are length balanced and tested - LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz) - Reference designs for integrated I/O pad ISERDES/OSERDES - 10x pin multiplexing per LVDS pair, greatly simplified logic partitioning - Source synchronous clocking for LVDS • 52-pin Main Bus (MB[51:0]) connects all LX FPGAs • Auspy board interconnect models for logic partitioning assistance • Marvell MV78200 Discovery Innovation Dual CPU - 1 GHz clock - Dual USB2.0 ports (Type B connector) - Dual Serial-ATA II connectors (SATA II) - Gigabit Ethernet interface • 10/100/1000 GbE (RJ45 connector) - 1 GB external DDR2 SDRAM • Organized in a 128M x 64 configuration • 400 MHz (800 MHz data rate with DDR) - RS232 port for terminal-style observation - After configuration, both CPUs dedicated entirely to user application - LINUX operating system • Source and examples provided via GPL license (no charge) • ~15 seconds to CPU boot Virtex-6 LX LXT SXT FPGA Speed Grades (slowest to fastest) LUT Size FF's Gate Max (100% u (1000's LX760 -1,-2 6-input 948,480 9,105 LX550(T) -1,-2 6-input 687,360 6,599 LX365T -1,-2,-3 6-input 455,040 4,368 LX240T -1,-2,-3 6-input 301,440 2,894 LX195T -1,-2,-3 6-input 249,600 2,396 LX130T -1,-2,-3 6-input 160,000 1,536 SX475T -1,-2 6-input 595,200 5,714 SX315T -1,-2 6-input 394,000 3,782 24 www.dinigroup.com
DNV6F2PCIe JTAG A DDR3 SODIMM (4GB Max) DDR3 SODIMM (4GB Max) 130 130 FPGA A FPGA B CONFIG FPGA SMA FPGA A FPGA B CONFIG FPGA SMA CONFIG FPGA 24 MHz 24 MHz 24 MHz 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) G0 (2KHz to 700 MHz) G1 (2KHz to 700 MHz) G2 (2KHz to 700 MHz) B SFP SATA II (device) SATA II (host) Cabled PCIe (4-lane) iPASS Virtex-6 Config FPGA 4 Device Bus PCIe PCIe (Gen1) 4 - lanes 60 60 NMB A NMB B OSC 40 FPGA A Virtex-6 LX760 / LX550T (FFG1760) 94 94 MEG Array Expansion connector (400-pin) AB 40 40 LEDs (8) 322 322 FPGA B Virtex-6 LX760 / LX550T (FFG1760) 94 94 MEG Array Expansion connector (400-pin) 35 LEDs (8) MICTOR 125 MHz 150 MHz OSC 250 MHz 312.5 MHz 125 MHz 150 MHz OSC 250 MHz 312.5 MHz SFP Clock SATA Clock 10/100/1000 10/100/1000 Phy baseT RJ45 RS232 USB 2.0 (2X) SATA II (host) 2x RGMII USB DMA(4x) SATA Marvell MV78200 RTC PCIe PCI EXPRESS FPU CPU CPU 4-lanes PCIe (GEN1) FPU 64 3 8 128M x 64 DDR2 128Mb SPI Boot FLASH 256Mb NAND FLASH Boot Battery Encryption Key Voltage = LVDS when paired, but can be used single-ended at a reduced frequency Features • Hosted via - 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T Ethernet - Stand alone • 2 Xilinx Virtex-6 FPGAs (FF1760) from the following list: - LX760-2,-1,-1L, LX550T-2,-1,-1L (fastest to slowest) - 50A VCCINT power per FPGA • 11+ million ASIC gates (ASIC measure) when stuffed with 2 Virtex-6 LX760s • FPGA to FPGA interconnect is LVDS and GTX Rocket I/O - 1.3 Gb/s when using DDR with -2 speed grade • 1.0 Gb/s with -1 speed grade - Reference designs for integrated I/O pad ISERDES/OSERDES - 10x pin multiplexing per LVDS pair - Greatly simplified logic partitioning - Source synchronous clocking for LVDS • Bus connecting Config FPGA with each field FPGA - 40 signals, single-ended (NMB[A:B]) • RocketIO GTX Transceivers (Configuration FPGA) - PCI Express Cable (x4), SATA – Host (x1), SATA – Device (x1), SFP (x1) • Auspy board interconnect models for logic partitioning assistance • 2 separate DDR3 SODIMMs, one for each FPGA (AB) - 533MHz, 1066 MB/s, PC3-8500 or better - 64-bit, with addressing/power to support 4GB in each socket - DDR3 Verilog/VHDL reference design provided (no charge) - DDR3 SODIMM data transfer rate: 68Gb/s - Alternate pin compatible memory cards available (consult factory for availability): • SRAM: QDR, ASYNC, STD, or PSRAM, FLASH • DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2 • Mictor, USB PHY, Extra Interconnect • Three independent low-skew global clock networks - G0, G1, G2 - Three, high-resolution, user-programmable synthesizers for G0, G1, G2 • Silicon Labs Si5326: 2kHz to 945 MHz - User configurable via Marvell uP RS232, USB, PCIe, or Ethernet - Global clocks networks distributed differentially and balanced • Flexible customization via daughter cards using two expansion connectors - 400-pin FCI MEG-Array connector • Non proprietary, readily available, and cheap - 96 LVDS pairs + clocks (or 186 single-ended) - 650 MHz on all signals with source synchronous LVDS (with -2 speed grade) - Signal voltage set by daughter card (+1.2v to +2.5V) - Reset - Supplied power rails (fused): • +12v (24W max), +3.3V (10W max) - Pin multiplexing to/from daughter cards using LVDS (up to 10x) • Fast and Painless FPGA configuration - USB, PCIe, Ethernet, JTAG - Stand-alone configuration with USB stick or on-board NAND FLASH - Configuration Error reporting - Accelerated configuration readback for advanced debug • RS232 port for embedded FPGA-based SOC uP debug - Accessible from all FPGAs via separate 2-signal bus • Full support for embedded logic analyzers via JTAG interface - ChipScope and other third-party debug solutions • Status FPGA-controlled LEDs - Enough illumination to sterilize refrigerator door handles. til) ) Estimate Practical (60% util) (1000's) Max I/O's Multipliers (25x18) Blocks (18kbits) Memory Total (kbits) Total (kbytes) 5,509 1,200 864 1,440 25,920 3,240 3,959 1,200 864 1,264 22,752 2,844 2,621 600 576 832 14,976 1,872 1,736 600 768 832 14,976 1,872 1,438 600 640 688 12,384 1,548 922 600 480 528 9,504 1,188 3,428 600 2,016 2,128 38,304 4,788 2,269 600 1,344 1,408 25,344 3,168 858 . 454 . 3419 25
Page 1 and 2: April 2013 v5.0 FPGA Boards ASIC Pr
Page 3 and 4: WHO, WHAT, WHERE, WHY? Who are you?
Page 5 and 6: HOSTING THE LARGEST FPGA EVER! USB
Page 7 and 8: four Virtex-7 FPGAs | 7V2000T-1 | 5
Page 9 and 10: two Virtex-7 FPGAs | 7V2000T-1 | 28
Page 11 and 12: single Virtex-7 FPGA | 7V2000T-1 |
Page 13 and 14: SMA SMA SMA SMA SMA SMA SMA SMA SMA
Page 15 and 16: dual Altera Stratix V FPGAs | 5SGXA
Page 17 and 18: single Xilinx Kintex-7 FPGA | QDRII
Page 19 and 20: single Xilinx Kintex-7 FPGA | QDRII
Page 21 and 22: A B C D F A B C F E D F D FPGA A LE
Page 23: Alternate Memory: 200-pin SODIMM SO
Page 27 and 28: DN-DualV6-PCIe-4 from FPGA A from F
Page 29 and 30: Specialty 204-pin SODIMM DNSODM204_
Page 31 and 32: DINAR1 Daughter Cards DINAR1_SOC 18
Page 33 and 34: DINAR1 Daughter Cards | DNNMB DINAR
Page 35 and 36: SMA DNMEG Daughter Cards DNMEG_SODI
Page 37 and 38: 114.285 MHZ 114.285 MHZ 114.285 MHZ
Page 39 and 40: DNIOB: High Speed Serial Interfaces
Page 41 and 42: SEAM Expansion DNSEAM_IPASSx4 Add 4
Page 43 and 44: DNK7_F5PCIe PC3-800 DDR3 (256M DDR3
Page 45 and 46: DNBFC_S12_PCIe Expansion Cards / Bo
Page 47 and 48: IP - PCIe (Gen1,2,3) Slowdown PCIe

FPGA Boards - The Dini Group

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