FPGA Boards - The Dini Group

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Bottom Virtex - 6 DNMEG_V6HXT 4x 10 GbE or 1x 40 GbE QSFP (40G) QSFP (40G) 4 4 GTH GTH CPLD (SFP Control Signals) 10 GbE to 6 GbE 10/100/1000 GbE 100 GbE / 40 GbE SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ CFP (40G / 100G) 4 8 SATA II Device Host Device Host sma GTH GTX GTX GTX GTH 10 GTH DDR3 UDIMM (16 GB Max) LED (4) 72-bit Data Virtex-6 HXT FPGA HT380T / 565T (FF1923) 2 8 GTX 150 4 GTX GTX 110 110 GTX 96 96 10 FMC (Vita 57) Top MEG Array Expansion connector (400-pin) JTAG 2 2 FMC RS232 (x2) SMA 28 SPI Flash SPI Flash Debug (JTAG) Control 2 Config MCU LPC1754 25 MHz Quad Clock Synthe -sizer Si5338 www.dinigroup.com 0 1 CLK_CFP CLK_QSFP CLK_SFP+HS CLK_SFP+LS FPGA Config GTX Expansion Header USB 2.0 SEARAY Features • ASIC prototyping daughter card, stand-alone, or PCIe-hosted Serial I/O - 10GbE/40GbE/100GbE • Xilinx Virtex-6 HXT FPGA (FF1923) - HX565T-2,-1 or HX380T-3,-2,-1 (fastest to slowest) • 24 GTH transceivers (to ~11 Gb/s) • 40 GTX transceivers (to 6.5 Gb/s) • Virtex-6 HX565T resources: - 2M ASIC gates (ASIC measure) - 354k flip-flop/6-input LUTs (708k total FFs) - 4MB embedded memory (1824, 18 kbit blocks) - 864, 25x18 multipliers • Multiple High speed serial I/O Interfaces: - CFP Module – 10 lanes (GTH): • Single 40GbE (IEEE 802.3bg) or 100GbE - IEEE 802.3ba and IEEE 802.3bg - CAUI, XLAUI, OTL4.10, OTL3.4, and STL256.4 et al. - 2 – QSFP+ Modules (GTH) • Single 40GbE or 4 channels of 10GBASE - 4 – SFP+ Modules (GTH) • 4 channels 10GbE - 8 – SFP+ Modules (GTX) • 8 channels 10/100/1000GbaseT - Dual Serial ATA II (SATA II) Host/Device - 8 channels on GTX Expansion header - 2 GTH channels on SMAs • Bulk memory: 240-pin DDR3 uDIMM - 72-bit data width (64-bit with 8-bit ECC), 533MHz operation, PC3-8500 - Addressing/power to support 16GB (+ ECC) RS232 (LCD) JTAG CPLD FPGA 4 4 iPASS Cable (3’-18’) iPASS Connector PCIe Cable Adapter Board Cray/Sun/Intel/HP/et al. PCIe Slot (8-lane) - DDR3 Verilog/VHDL reference design provided (no charge) - Optional RLDRAM DIMM instead of DDR3 for ultra low latency • Optional cabled PCIe GEN1/GEN2 hosting (with DNMEG_CBL_GEN2) - Dual 1-lane, Dual 4-lane or single 8-lane - (Optional) PCIe clock slow down IP • Allows clocking the PIPE interface as slowly as 35 MHz - PCIe PIPE Slowdown Core • Flexible, abundant clock resources - 4 board-level clocks configurable clocks • Silicon Image Si5338: 0.16 to 710MHz - Fixed 150MHz oscillator for SATA II. Fixed 100MHZ oscillator for PCIe • Mount to DINI products with 400-pin MEG-Array connectors - 96 LVDS pairs + clocks (or 192 single-ended) • 550MHz on all signals with source synchronous LVDS. Slower when used single-ended - Pin multiplexing to/from motherboard using ISERDES/OSERDES and LVDS (up to 10x) • Supplied power rails (fused): +12V (24W max), +5V (10W max), +3.3V (10W max) - Reference designs for integrated I/O pad ISERDES/OSERDES • FMC (Vita 57) interface for use with off-the-shelf I/O boards - A/D-D/A, CameraLink, DSP, and RF Transceivers • Fast and Painless FPGA configuration with integrated uC and EEPROM • Dual RS232 ports for embedded uP debug and monitoring • Battery socket for configuration bitfile encryption • Full support for embedded logic analyzers via JTAG interface - ChipScope, ChipScope Pro, Veridae, and other third party solutions • Enough status LEDs to mystify a small trout
Specialty 204-pin SODIMM DNSODM204_SSRAM SSRAM: Pipeline or NoBL A [22:0] DQ [35:0] ADV / LD BW [A, B, C, D] 23 36 SSRAM A [22:0] DQ [35:0] ADV / LD BW [3:0] DNSODM204_SE Mobile SDRAM, Flash Ck0 RAS * CAS * WE * address 15 Mobile SDRAM WE CE [1:0] CEN ZZ OE CLK 0 WE CE [1:0] CEN ZZ OE data Ck1 16 16M x 16 Mobile SDRAM DQ [71:36] SSRAM A [22:0] DQ [35:0] BW [E, F, G, H] ADV / LD BW [3:0] data 16 WE CE [1:0] 16M x 16 CEN CLK 1 ZZ OE 8 control address 25 Flash (28F256) A [24:23] NC (future expansion) CS, SI, SO, RST, WP, SCK 6 Data Flash data 16 16M x 16 DNSODM204_SSRAM1_8V SSRAM: Pileline or NoBL, 16M x 72 +1.8V for Virtex-7, 144MB 24FC256 IIC Serial EEPROM 5 SCL,SDA,SA0,SA1,VDDSPD 204 USB2.0 Phy, SPI Flash, NAND Flash 5 Cntl[CKEn,Wn,En,Gn,BWxn,ADV,ZZ,LBOn] 23 A[22:0] 4 CLK[3:0] BA0 Bank 0 only 8 Data (12 Control) Nand Flash GS81284Z18-xxxV 144Mb SSRAM 8M x 18 NBT DQ[54:71] 204-pin “DD3” SODIMM 8 Data (5 Control) USB PHY USB 2.0 (480Mb/s) To FPGA 32 Data Header GS81284Z18-xxxV 144Mb SSRAM 8M x 18 NBT DQ[36:53] 32 Data Header SPI Flash GS81284Z18-xxxV 144Mb SSRAM 8M x 18 NBT DQ[18:35] 1 Data (3 Control) GS81284Z18-xxxV 144Mb SSRAM 8M x 18 NBT DQ[17:0] DNSODM204_QUADMIC 4 Mictors MICTOR DNSODM204_DDR2_FAST DQ [63:0] 64 Ck Ck 30 DDR2 64M x 8 DDR2 64M x 8 MICTOR 8 8 34 DDR2 64M x 8 DDR2 64M x 8 MICTOR 8 8 34 DDR2 64M x 8 DDR2 64M x 8 MICTOR 8 8 34 Addr 8 DDR2 64M x 8 18 8 DDR2 64M x 8 Control (RAS, CAS, WE) 858 . 454 . 3419 29
Page 1 and 2: April 2013 v5.0 FPGA Boards ASIC Pr
Page 3 and 4: WHO, WHAT, WHERE, WHY? Who are you?
Page 5 and 6: HOSTING THE LARGEST FPGA EVER! USB
Page 7 and 8: four Virtex-7 FPGAs | 7V2000T-1 | 5
Page 9 and 10: two Virtex-7 FPGAs | 7V2000T-1 | 28
Page 11 and 12: single Virtex-7 FPGA | 7V2000T-1 |
Page 13 and 14: SMA SMA SMA SMA SMA SMA SMA SMA SMA
Page 15 and 16: dual Altera Stratix V FPGAs | 5SGXA
Page 17 and 18: single Xilinx Kintex-7 FPGA | QDRII
Page 19 and 20: single Xilinx Kintex-7 FPGA | QDRII
Page 21 and 22: A B C D F A B C F E D F D FPGA A LE
Page 23 and 24: Alternate Memory: 200-pin SODIMM SO
Page 25 and 26: DNV6F2PCIe JTAG A DDR3 SODIMM (4GB
Page 27: DN-DualV6-PCIe-4 from FPGA A from F
Page 31 and 32: DINAR1 Daughter Cards DINAR1_SOC 18
Page 33 and 34: DINAR1 Daughter Cards | DNNMB DINAR
Page 35 and 36: SMA DNMEG Daughter Cards DNMEG_SODI
Page 37 and 38: 114.285 MHZ 114.285 MHZ 114.285 MHZ
Page 39 and 40: DNIOB: High Speed Serial Interfaces
Page 41 and 42: SEAM Expansion DNSEAM_IPASSx4 Add 4
Page 43 and 44: DNK7_F5PCIe PC3-800 DDR3 (256M DDR3
Page 45 and 46: DNBFC_S12_PCIe Expansion Cards / Bo
Page 47 and 48: IP - PCIe (Gen1,2,3) Slowdown PCIe

FPGA Boards - The Dini Group

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