FPGA Boards - The Dini Group

DNBFC_S12_PCIe
Expansion
Cards
/
Board to Board
Dataflow
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
Top
Bottom
QSE
QSE
16
data
16
data
16
data
16
data
16
data
16
data
DDR3 - 800
(128M x 16)
DDR3 - 800
(128M x 16)
data
16
data
16
GTP
GTP
Spartan - 6
LX150T
User FPGA
Dataflow
Manager
GTP
4 4 4 4
DM
77
77
Spartan - 6
LX150
FPGA 0
(FGG484)
64
Spartan - 6
LX150
FPGA 11
(FGG484)
77
MB (upper)
MB (lower)
77
Spartan - 6
LX150
FPGA 1
(FGG484)
8
8
64
Spartan - 6
LX150
FPGA 10
(FGG484)
77
77
Spartan - 6
LX150
FPGA 2
(FGG484)
64
Spartan - 6
LX150
FPGA 9
(FGG484)
77
77
Spartan - 6
LX150
FPGA 3
(FGG484)
64
Spartan - 6
LX150
FPGA 8
(FGG484)
77
77
Spartan - 6
LX150
FPGA 4
(FGG484)
64
Spartan - 6
LX150
FPGA 7
(FGG484)
77
77
Spartan - 6
LX150
FPGA 5
(FGG484)
Spartan - 6
LX150
FPGA 6
(FGG484)
64 77
32
32
16
data
16
data
16
data
16
data
16
data
16
data
Config
EE
User
EEPROM
PCIe
Bridge
Q
4-lane PCIe (GEN1/GEN2)
DDR3 - 800
(128M x 16)
100MHz Clock
ALL FPGAs
MB Clock
DDR3 - 800
(128M x 16)
JTAG
0
DM
1 2
11
10
3
9
4
5
8
6
7
DDR3 - 800
(128M x 16)
Frequency
Synthesizer
31.25 MHz-
350 MHz
DDR3 - 800
(128M x 16)
CLK A
ALL FPGAs
DDR3 - 800
(128M x 16)
Battery
Bitstream
Encryption
DDR3 - 800
(128M x 16)
PCIe
Features
• PCI Express (4-lane) FPGA-based algorithm acceleration peripheral
- 12 of the largest Xilinx Spartan-6 FPGAs: 6SLX150-2
• 12, 128M x 16 (2Gb) DDR3-800 memories (1 per FPGA)
- 1 Xilinx Spartan-6 FPGAs: 6SLX150T-2
• 2, 128M x 16 (2Gb) DDR3-800 memories
• Fixed 4-lane PCIe interface and controller
- PCIe GEN1/GEN2
- Full mastering DMA
• 2 transmit (host memory -> card)
• 2 receive (card -> host memory)
• Xilinx FPGA Spartan-6 LX150-2 – 12 total
- 184,464 flip-flops per FPGA
• 92K flips-flops with 6-input LUT
- 180, 18x18 multipliers + 48-bit accumulator per FPGA
- 268, 18 Kbit block RAM (603 Kbytes) per FPGA
• Fully dual-ported
• Each block RAM configurable as:
- 16K×1, 8K×2, 4K×4, 2K×8/9, 1K×16/18, or 512 x 32/36
- Options for LX150-1L (lower power) or LX150-3 (higher frequency)
• Also LX150T-3,-4
- Options for LX100, LX75, LX45, LX25 (lower cost)
• FPGA to FPGA interconnect single-ended
- Source synchronous FPGA -> FPGA frequency: 150MHz
• 300 Mb/s per pin when using DDR
• Main Bus (MB) connects all Spartan-6 FPGAs (8 signals)
- 90MHz
• 128Mb x 16 fixed external DDR3 memory dedicated to each field FPGA (12 total)
• 2 – 128Mb x 16 fixed external DDR3 memories dedicated to USER
Dataflow Manager FPGA
- DDR3-800 is stuffed. VCCINT is set to ‘Extended Performance’ operating range:
• With LX150-2, LX150T-2: 667 Mbps (333.5 MHz)
Designed for High Performance Computing (HPC) applications, the DNBFC_S12_PCIe is a FPGA-based
peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost effective
Xilinx Spartan-6 FPGAs. Data movement to/from the FPGA grid is accomplished via a fixed 4-lane,
GEN1/GEN2 PCIe bridge. Each Spartan-6 FPGA has its own 128M x 16 DDR3 memory capable of clocked
speeds up to 400MHz (800 Mb/s per data pin). Two additional 128M x 16 DDR3 memories are connected to
the USER Dataflow Manager FPGA (LX150T) for bulk data storage.
- 10.67 Gb/s maximum data rate
• With LX150-3, LX150T-3,LX150T-4: 800 Mbps (400 MHz)
- 12.8 Gb/s maximum data rate
- Full support for FPGA memory block controller (MBC)
• Up to 8 open banks
• Configurable multi-port interface to FPGA fabric
- 32-, 64-, or 128-bit data bus
• Easy implementation with Xilinx CORE Generator
• Expansion via high speed, low-power GTP transceivers (LX150T)
- 3.125 Gb/s per lane, each direction with -3 or -4 (TX and RX)
- 2.7 Gb/s per lane, each direction with -2 (TX and RX)
- 4 lanes (4 RX and 4 TX) for daisy chain left
- 4 lanes (4 RX and 4 TX) for daisy chain right
- Board to board data communication
• >1 GB/s per connector TX
• >1 GB/s per connector RX
• Non-proprietary, off-the-shelf Samtec cable assembly
- Off-board daughter cards
• Three independent low-skew global clock networks distributed
differentially and balanced
- G0: programmable in 1 MHz increments (ICS84314 clock synthesizer)
• 32 MHz to 350 MHz
- G1: 100MHz PCIe reference
- G2: Main Bus (MB) clock
• Fast and Painless FPGA configuration via PCIe
- On-board battery for AES bitstream encryption
- Unique Device DNA identifier for design authentication
• Full support for embedded logic analyzers via JTAG interface
- ChipScope, and other third-party debug solutions
• FPGA-controller LEDs
- Enough for emergency lighting in a small parking structure
858 . 454 . 3419 45