FPGA Boards - The Dini Group

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40 40 40 40 40 40 Virtex - 6 DNV6F6PCIe Features • Hosted via Config FPGA 10/100/1000 baseT RJ45 USB 2.0 (3x) 24 MHz 125 MHz 150 MHz OSC 250 MHz 312.5 MHz G0 - 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T Ethernet, or Stand alone • Six Xilinx Virtex-6 FPGAs (FF1759) from the following list: - LX550T-2,-1,-1L, SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L - LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L - 30A VCCINT power per FPGA • 24+ million ASIC gates (ASIC measure) when stuffed with 6 Virtex-6 LX550T • 21+ million ASIC gates and 12,096, 25x18 multipliers with 6 Virtex-6 SX475T • FPGA to FPGA interconnect is LVDS and GTX RocketI/O - 710 MHz LVDS chip to chip with -3 speed grade (1.4Gb/s with DDR) • 650MHz with -2 (1.3 Gb/s with DDR), 500MHz with -1 (1.0 Gb/s with DDR) - Pairs are length balanced and tested! - LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz) • Reference designs for integrated I/O pad ISERDES/OSERDES • 10x pin multiplexing per LVDS pair. Source synchronous clock ing for LVDS - GTX Transceivers FPGA to FPGA • 6.5 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1/-1L • Data examples provided using Aurora protocol • Bus connecting Config FPGA with each field FPGA - 40 signals, single-ended (NMB[F..A]) - Full PCI Express throughput to user design • Auspy board description models for logic partitioning assistance • 4 separate DDR3 SODIMMs, one for each corner Virtex-6 FPGA (ACFD) - 533MHz, 1066 MB/s with -2 and -3 speed grades (PC3-8500) • 400MHz, 800 Mb/s with -1 speed grade (PC3-6400) - 64-bit, with addressing/power to support 4GB in each socket - DDR3 Verilog/VHDL reference design provided (no charge) - DDR3 SODIMM data transfer rate: 68Gb/s - Alternate pin compatible memory cards available (consult factory for availability): • SRAM: QDR, ASYNC, STD, or PSRAM, FLASH DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra Interconnect SMA 24 MHz 24 MHz RS232 SATA II (host) 2x FPGA C FPGA E FPGA F FPGA A FPGA D FPGA B 10/100/1000 Phy CLK_25 (25 MHz) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) RGMII USB USER_R USER_L G0 (2KHz to 700 MHz) G1 (2KHz to700 MHz) G2 (2KHz to 700 MHz) MGT Clock DMA(4x) SATA RTC FPGA Q Virtex-5 Config FPGA MPP Bus PCIe PCIe (Gen1) 4 - lanes Marvell MV78200 PCIe PCI EXPRESS FPU FPU CPU CPU 4-lanes PCIe (GEN1) SFP or SFP+ SATA II (device) (host) NMB OSC 64 3 8 10/100/1000 Phy DDR3 SODIMM (4GB Max) DDR3 SODIMM (4GB Max) 128M x 64 DDR2 128Mb SPI Boot FLASH 256Mb NAND FLASH Boot GTX 1 130 130 MEG Array Expansion connector (400-pin) 40 96 96 FPGA F Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 40 74` 74 FPGA C Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 8 GTX GTX 8 GTX Expansion Header GTX 12 128Mb Flash 4 4 58 58 20 20 4 4 120 120 20 20 40 40 GTX GTX GTX GTX MEG Array Expansion connector (400-pin) 96 96 FPGA E Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 95 95 FPGA B Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 128Mb FLASH GTX 16 128Mb Flash 4 4 60 60 40 40 4 4 100 100 40 40 GTX GTX GTX GTX = LVDS when paired, but can be run single-ended at reduced frequency GTX--> Packet I/O Transceivers 6.5 Gb/s per channel bidirectional (13 Gb/s max) MEG Array Expansion connector (400-pin) 96 96 FPGA D Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 20 20 73 73 FPGA A Virtex-6 LX240T/LX365T SX315T LX550T/SX475T (FF1759) 8 GTX GTX GTX Expansion Header • Three independent low-skew global clock networks: G0, G1, G2 - Three, high-resolution, user-programmable synthesizers for G0, G1, G2 • Silicon Labs Si5326: 2kHz to 945 MHz - User configurable via Marvell uP RS232, USB, PCIe, or Ethernet - Global clocks networks distributed differentially and balanced • Add 8 SFP sockets to GTX Expansion Header with DNSEAM_SFP • Flexible customization via daughter cards using expansion connector - Daughter card location on FPGA D,E,F • 400-pin FCI MEG-Array connector - Non proprietary, readily available, and cheap - 96 LVDS pairs + clocks (or 186 single-ended) - 710 MHz (1/4 Gb/s) on all signals with source synchronous LVDS (assuming -3 speed grade) - Signal voltage set by daughter card (+1.2v to +2.5V) - Supplied power rails (fused): +12v (24W max), +3.3V (10W max) - Pin multiplexing to/from daughter cards using LVDS (up to 10x) • High Speed expansion via GTX connector - Connector for each FPGA A, C, F, 8 GTX lanes per connector - 6.5 Gb/s per lane, each direction (with -3) • 5.- Gb/s with -1 and 01L speed grade • Fast and Painless FPGA configuration via USB, PCIe, Ethernet, JTAG • Stand-alone configuration with USB stick or on-board NAND FLASH - Configuration Error reporting - Accelerated configuration readback for advanced debug • RS232 port for embedded FPGA-based SOC uP debug - Accessible from all FPGAs via separate 2-signal bus • Full support for embedded logic analyzers via JTAG interface - ChipScope and other third-party debug solutions • Status FPGA-controlled LEDs - Enough illumination to act as automobile fog lights Virtex-6 LX LXT SXT FPGA Speed Grades (slowest to fastest) 4 8 GTX 12 GTX 130 130 GTX Expansion Header DDR3 SODIMM (4GB Max) DDR3 SODIMM (4GB Max) 128Mb Flash LUT Size FF's Gate Max (100% u (1000's LX760 -1,-2 6-input 948,480 9,105 LX550(T) -1,-2 6-input 687,360 6,599 LX365T -1,-2,-3 6-input 455,040 4,368 LX240T -1,-2,-3 6-input 301,440 2,894 LX195T -1,-2,-3 6-input 249,600 2,396 LX130T -1,-2,-3 6-input 160,000 1,536 SX475T -1,-2 6-input 595,200 5,714 SX315T -1,-2 6-input 394,000 3,782 26 www.dinigroup.com
DN-DualV6-PCIe-4 from FPGA A from FPGA B TP osc 24 MHz CLK_G0 osc 24 MHz Config FPGA osc 24 MHz 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) 114.285 MHz Frequency Synthesizer (Si5326) CLK_G0 CLK_G1 (2KHz to 945 MHz) CLK_G2 (iDELAY) SPI FPGA Q Virtex-5T LX50T Config FPGA 100 100 20 QA 20 2 GTX DDR3 SODIMM (4GB max) 122 FPGA A Virtex-6 SX475T / SX315T LX365T / LX240T LX195T / LX130T (FF1156) AB GTX (6.5 Gb/s) 1 1 79 79 4 DDR3 SODIMM (4GB max) 122 FPGA B Virtex-6 SX475T / SX315T LX365T / LX240T LX195T / LX130T (FF1156) 99 99 MEG Array Expansion Connector (400-pin) RS232 (device) PCIe LEDs (x8) (host) A JTAG SATA II B QB 20 OSC PCIe 20 JTAG Q (4-lanes) GTX 2 MPP Bus 1 1 LEDs (x8) (device) (host) SATA II 10/100/1000 baseT RJ45 USB 2.0 (2x) RS232 10/100/1000 Phy RGMII USB DMA(4x) SATA Marvell MV78200 PCIe FPU FPU CPU CPU 64 3 128M x 64 DDR2 SPI Boot FLASH = LVDS when paired, but can be run single-ended at reduced frequency RTC 4-lanes PCIe (GEN1) 8 NAND FLASH Boot PCI EXPRESS Features • Hosted in a 4-lane GEN1 PCIe (v1.1) slot, USB 2.0, 10/100/1000 baseT Ethernet, stand alone • 1-2 Xilinx Virtex-6 FPGAs from the following list: - SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L, LX365T-3,-2,-1,-1L - LX240T-3,-2,-1,-1L, LX195T-3,-2,-1,-1L, LX130T-3,-2,-1,-1L - 50A VCCINT power shared between both FPGAs • FF1156 package with 600 I/Os, all utilized • 10+ million ASIC gates (ASIC measure) when stuffed with 2 Virtex-6 SX475T - 2016, 25 x 18 multipliers (with accumulator) per SX475 • FPGA to FPGA interconnect is LVDS - 710 MHz LVDS chip to chip with -3 speed grade (1.4 Gb/s with DDR) • 650 MHz with -2 (1.3 Gb/s with DDR), 500 MHz with -1 (1.0 Gb/s with DDR) - Pairs are length balanced and tested! - LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz) - Reference designs for integrated I/O pad ISERDES/OSERDES - 10x pin multiplexing per LVDS pair. Source synchronous clocking for LVDS • RocketI/O GTX Transceivers - 6.5 Gb/s (with -3, -2 speed grade), 5.0 Gb/s with -1 - 4-lanes connected between FPGA A and FPGA B - 2 lanes connected from Config FPGA Q to FPGA A - 2 lanes connected from Config FPGA Q to FPGA B - Data examples provided using Aurora protocol • Auspy models for logic partitioning assistance • 2 separate DDR3 SODIMMs, one for each Virtex-6 FPGA (AB) - 533MHz, 1066 MB/s, PC3-8500 or better - 64-bit, with addressing/power to support 4GB in each socket - DDR3 Verilog/VHDL reference design provided (no charge) - DDR3 SODIMM data transfer rate: 68Gb/s - Alternate pin compatible memory cards available (consult factory for availability): • SRAM: QDR, ASYNC, STD, or PSRAM, FLASH, DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra Interconnect • Seven independent low-skew global clock networks: G0, G1, G2 - High-resolution, user-programmable synthesizers for G0, G1, G2 • Silicon Labs Si5326: 2kHz to 945 MHz - User configurable via Marvell uP RS232, USB, PCIe, or Ethernet - Global clocks networks distributed differentially and balanced • Single-step clock - External clock input can be injected onto low-skew global clock networks - single-ended or differential • Flexible customization via daughter cards using expansion connector - Daughter card location on FPGA B - 400-pin FCI MEG-Array connector • Non proprietary, readily available, and cheap - 93 LVDS unidirectional pairs + clocks (or 186 single-ended) - 710 MHz on all signals with source synchronous LVDS(with -3 speed grade) - Signal voltage set by daughter card (+1.2v to +3.3V) • Supplied power rails (fused): +12v (24W max) and +3.3V (10W max) - Pin multiplexing to/from daughter cards using LVDS (up to 10x) • Fast and Painless FPGA configuration - USB, PCIe, Ethernet, JTAG. Stand-alone configuration with USB stick - Configuration Error reporting - Accelerated configuration readback for advanced debug • RS232 port for embedded FPGA-based SOC uP debug - Accessible from all FPGAs via separate 2-signal bus • Full support for embedded logic analyzers via JTAG interface - ChipScope and other third-party debug solutions • Status FPGA-controlled LEDs - Bright enough to see from a low-space orbit, but won’t blind airline pilots. til) ) Estimate Practical (60% util) (1000's) Max I/O's Multipliers (25x18) Blocks (18kbits) Memory Total (kbits) Total (kbytes) 5,509 1,200 864 1,440 25,920 3,240 3,959 1,200 864 1,264 22,752 2,844 2,621 600 576 832 14,976 1,872 1,736 600 768 832 14,976 1,872 1,438 600 640 688 12,384 1,548 922 600 480 528 9,504 1,188 3,428 600 2,016 2,128 38,304 4,788 2,269 600 1,344 1,408 25,344 3,168 858 . 454 . 3419 27
Page 1 and 2: April 2013 v5.0 FPGA Boards ASIC Pr
Page 3 and 4: WHO, WHAT, WHERE, WHY? Who are you?
Page 5 and 6: HOSTING THE LARGEST FPGA EVER! USB
Page 7 and 8: four Virtex-7 FPGAs | 7V2000T-1 | 5
Page 9 and 10: two Virtex-7 FPGAs | 7V2000T-1 | 28
Page 11 and 12: single Virtex-7 FPGA | 7V2000T-1 |
Page 13 and 14: SMA SMA SMA SMA SMA SMA SMA SMA SMA
Page 15 and 16: dual Altera Stratix V FPGAs | 5SGXA
Page 17 and 18: single Xilinx Kintex-7 FPGA | QDRII
Page 19 and 20: single Xilinx Kintex-7 FPGA | QDRII
Page 21 and 22: A B C D F A B C F E D F D FPGA A LE
Page 23 and 24: Alternate Memory: 200-pin SODIMM SO
Page 25: DNV6F2PCIe JTAG A DDR3 SODIMM (4GB
Page 29 and 30: Specialty 204-pin SODIMM DNSODM204_
Page 31 and 32: DINAR1 Daughter Cards DINAR1_SOC 18
Page 33 and 34: DINAR1 Daughter Cards | DNNMB DINAR
Page 35 and 36: SMA DNMEG Daughter Cards DNMEG_SODI
Page 37 and 38: 114.285 MHZ 114.285 MHZ 114.285 MHZ
Page 39 and 40: DNIOB: High Speed Serial Interfaces
Page 41 and 42: SEAM Expansion DNSEAM_IPASSx4 Add 4
Page 43 and 44: DNK7_F5PCIe PC3-800 DDR3 (256M DDR3
Page 45 and 46: DNBFC_S12_PCIe Expansion Cards / Bo
Page 47 and 48: IP - PCIe (Gen1,2,3) Slowdown PCIe

FPGA Boards - The Dini Group

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