FPGA Boards - The Dini Group

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(128M x 16) 16 (128M x 16) 16 Config EE User EEPROM DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 (128M x 16) (128M x 16) (128M x 16) (128M x 16) (128M x 16) (128M x 16) 16 16 16 16 16 16 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 77 77 77 77 77 LX150 LX150 LX150 LX150 LX150 LX150 FPGA 0 FPGA 1 FPGA 2 FPGA 3 FPGA 4 FPGA 5 (FGG484) (FGG484) (FGG484) (FGG484) (FGG484) (FGG484) MB (upper) 8 64 MB (lower) 64 64 64 64 64 77 8 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 77 77 77 77 77 LX150 LX150 LX150 LX150 LX150 LX150 FPGA 11 FPGA 10 FPGA 9 FPGA 8 FPGA 7 FPGA 6 (FGG484) (FGG484) (FGG484) (FGG484) (FGG484) (FGG484) 32 32 16 16 16 16 16 16 DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 DDR3 - 800 (128M x 16) (128M x 16) (128M x 16) (128M x 16) (128M x 16) (128M x 16) PCIe 100MHz Clock Bridge ALL FPGAs Q MB Clock 4-lane PCIe (GEN1/GEN2) PCIe Expansion Board to Board Cards / Dataflow Top Bottom QSE QSE 4 4 4 4 data GTP 77 Spartan - 6 LX150T User FPGA Dataflow data Manager 77 DM GTP GTP data data data data data data data data data data data data High Performance Computing DNBFC_S12_12_Cluster DDR3 - 800 DDR3 - 800 Each line represents 4 GTX serial I/O connections 3.125 GB/s per line BFC_S10_PCIe PCIe (GEN1) 4 4 4 4 4 4 4 4 4 4 PCIe Fan Out Switch PCIe Fan Out Switch 8 8 PCIe QPI Xeon (CPU2) Xeon (CPU1) 2 GB DDR3 2 GB DDR3 2 GB DDR3 2 GB DDR3 2 GB DDR3 2 GB DDR3 Platform Controller Hub (3420) 6 LAN 1 10/100/1000 base-T LAN 2 USB 0 USB 1 Video (XGI) HDD Up to 6 HDD (SATA 3) Features • 5U Rackmount Chassis containing: - 1 Intel Xeon E3-1275 processor card - 12 DNBFC_S12_PCIe FPGA cards each with 13 Xilinx of the largest Spartan-6 FPGAs (XC6SLX150) • PCIe 4-lane (GEN1) • 156 FPGAs in total, 100% dedicated to application - Other configurations with different CPU to FPGA ratios are available - 2 bays for SATA-3 hard drives • Processor card - Intel Xeon E3-1200 series (Sandy Bridge) processors, 3.4 GHz • Quad-Core, 8MB shared L2 cache • 4 GB DDR3 memory (4 GB total) - Options up to 32 GB (32 GB max) • VGA with standard D-Sub connector • 10/100/1000BASE-T Ethernet (2 ports) • USB 2.0 (4 ports total) - 2 ports on front panel - 2 ports on back bracket • Supports most all Linux distributions The DNBFC_S12_12_Cluster is a complete, 5U rack mount FPGA acceleration cluster. The standard configuration contains the following: Trenton TSB7053 Xeon processor card 12 DNBFC_S12_PCIe Spartan-6 FPGA cards with 13 LX150 FPGAs per card. 2 TB SATA II Hard Drive This system contains the maximum number of cost effective FPGA that can be reasonability integrated into a 5U chassis. Power and cooling are the constraining variables. High performance data paths between FPGA boards enable data movement under algorithmic control that is wholly separate from the host processor, enabling FPGA-based acceleration of whole new classes of data intensive algorithms. In short, the DNBFC_S12_12_Cluster is a massive number of large, low cost FPGAs integrated with an excellent dual Xeon-based processor host. High speed serial cables between FPGA cards add as much a 5 GB/s data throughput within the chassis. A partial list of possible applications includes: Bioinformatics Genomic Search Financial Analytics - Low Latency Analysis - Derivative Calculations Image Processing Signal Processing Radar Scientific Computing Video Compression Encryption/Decryption (Cryptography) 44 www.dinigroup.com
DNBFC_S12_PCIe Expansion Cards / Board to Board Dataflow DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) Top Bottom QSE QSE 16 data 16 data 16 data 16 data 16 data 16 data DDR3 - 800 (128M x 16) DDR3 - 800 (128M x 16) data 16 data 16 GTP GTP Spartan - 6 LX150T User FPGA Dataflow Manager GTP 4 4 4 4 DM 77 77 Spartan - 6 LX150 FPGA 0 (FGG484) 64 Spartan - 6 LX150 FPGA 11 (FGG484) 77 MB (upper) MB (lower) 77 Spartan - 6 LX150 FPGA 1 (FGG484) 8 8 64 Spartan - 6 LX150 FPGA 10 (FGG484) 77 77 Spartan - 6 LX150 FPGA 2 (FGG484) 64 Spartan - 6 LX150 FPGA 9 (FGG484) 77 77 Spartan - 6 LX150 FPGA 3 (FGG484) 64 Spartan - 6 LX150 FPGA 8 (FGG484) 77 77 Spartan - 6 LX150 FPGA 4 (FGG484) 64 Spartan - 6 LX150 FPGA 7 (FGG484) 77 77 Spartan - 6 LX150 FPGA 5 (FGG484) Spartan - 6 LX150 FPGA 6 (FGG484) 64 77 32 32 16 data 16 data 16 data 16 data 16 data 16 data Config EE User EEPROM PCIe Bridge Q 4-lane PCIe (GEN1/GEN2) DDR3 - 800 (128M x 16) 100MHz Clock ALL FPGAs MB Clock DDR3 - 800 (128M x 16) JTAG 0 DM 1 2 11 10 3 9 4 5 8 6 7 DDR3 - 800 (128M x 16) Frequency Synthesizer 31.25 MHz- 350 MHz DDR3 - 800 (128M x 16) CLK A ALL FPGAs DDR3 - 800 (128M x 16) Battery Bitstream Encryption DDR3 - 800 (128M x 16) PCIe Features • PCI Express (4-lane) FPGA-based algorithm acceleration peripheral - 12 of the largest Xilinx Spartan-6 FPGAs: 6SLX150-2 • 12, 128M x 16 (2Gb) DDR3-800 memories (1 per FPGA) - 1 Xilinx Spartan-6 FPGAs: 6SLX150T-2 • 2, 128M x 16 (2Gb) DDR3-800 memories • Fixed 4-lane PCIe interface and controller - PCIe GEN1/GEN2 - Full mastering DMA • 2 transmit (host memory -> card) • 2 receive (card -> host memory) • Xilinx FPGA Spartan-6 LX150-2 – 12 total - 184,464 flip-flops per FPGA • 92K flips-flops with 6-input LUT - 180, 18x18 multipliers + 48-bit accumulator per FPGA - 268, 18 Kbit block RAM (603 Kbytes) per FPGA • Fully dual-ported • Each block RAM configurable as: - 16K×1, 8K×2, 4K×4, 2K×8/9, 1K×16/18, or 512 x 32/36 - Options for LX150-1L (lower power) or LX150-3 (higher frequency) • Also LX150T-3,-4 - Options for LX100, LX75, LX45, LX25 (lower cost) • FPGA to FPGA interconnect single-ended - Source synchronous FPGA -> FPGA frequency: 150MHz • 300 Mb/s per pin when using DDR • Main Bus (MB) connects all Spartan-6 FPGAs (8 signals) - 90MHz • 128Mb x 16 fixed external DDR3 memory dedicated to each field FPGA (12 total) • 2 – 128Mb x 16 fixed external DDR3 memories dedicated to USER Dataflow Manager FPGA - DDR3-800 is stuffed. VCCINT is set to ‘Extended Performance’ operating range: • With LX150-2, LX150T-2: 667 Mbps (333.5 MHz) Designed for High Performance Computing (HPC) applications, the DNBFC_S12_PCIe is a FPGA-based peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost effective Xilinx Spartan-6 FPGAs. Data movement to/from the FPGA grid is accomplished via a fixed 4-lane, GEN1/GEN2 PCIe bridge. Each Spartan-6 FPGA has its own 128M x 16 DDR3 memory capable of clocked speeds up to 400MHz (800 Mb/s per data pin). Two additional 128M x 16 DDR3 memories are connected to the USER Dataflow Manager FPGA (LX150T) for bulk data storage. - 10.67 Gb/s maximum data rate • With LX150-3, LX150T-3,LX150T-4: 800 Mbps (400 MHz) - 12.8 Gb/s maximum data rate - Full support for FPGA memory block controller (MBC) • Up to 8 open banks • Configurable multi-port interface to FPGA fabric - 32-, 64-, or 128-bit data bus • Easy implementation with Xilinx CORE Generator • Expansion via high speed, low-power GTP transceivers (LX150T) - 3.125 Gb/s per lane, each direction with -3 or -4 (TX and RX) - 2.7 Gb/s per lane, each direction with -2 (TX and RX) - 4 lanes (4 RX and 4 TX) for daisy chain left - 4 lanes (4 RX and 4 TX) for daisy chain right - Board to board data communication • >1 GB/s per connector TX • >1 GB/s per connector RX • Non-proprietary, off-the-shelf Samtec cable assembly - Off-board daughter cards • Three independent low-skew global clock networks distributed differentially and balanced - G0: programmable in 1 MHz increments (ICS84314 clock synthesizer) • 32 MHz to 350 MHz - G1: 100MHz PCIe reference - G2: Main Bus (MB) clock • Fast and Painless FPGA configuration via PCIe - On-board battery for AES bitstream encryption - Unique Device DNA identifier for design authentication • Full support for embedded logic analyzers via JTAG interface - ChipScope, and other third-party debug solutions • FPGA-controller LEDs - Enough for emergency lighting in a small parking structure 858 . 454 . 3419 45
Page 1 and 2: April 2013 v5.0 FPGA Boards ASIC Pr
Page 3 and 4: WHO, WHAT, WHERE, WHY? Who are you?
Page 5 and 6: HOSTING THE LARGEST FPGA EVER! USB
Page 7 and 8: four Virtex-7 FPGAs | 7V2000T-1 | 5
Page 9 and 10: two Virtex-7 FPGAs | 7V2000T-1 | 28
Page 11 and 12: single Virtex-7 FPGA | 7V2000T-1 |
Page 13 and 14: SMA SMA SMA SMA SMA SMA SMA SMA SMA
Page 15 and 16: dual Altera Stratix V FPGAs | 5SGXA
Page 17 and 18: single Xilinx Kintex-7 FPGA | QDRII
Page 19 and 20: single Xilinx Kintex-7 FPGA | QDRII
Page 21 and 22: A B C D F A B C F E D F D FPGA A LE
Page 23 and 24: Alternate Memory: 200-pin SODIMM SO
Page 25 and 26: DNV6F2PCIe JTAG A DDR3 SODIMM (4GB
Page 27 and 28: DN-DualV6-PCIe-4 from FPGA A from F
Page 29 and 30: Specialty 204-pin SODIMM DNSODM204_
Page 31 and 32: DINAR1 Daughter Cards DINAR1_SOC 18
Page 33 and 34: DINAR1 Daughter Cards | DNNMB DINAR
Page 35 and 36: SMA DNMEG Daughter Cards DNMEG_SODI
Page 37 and 38: 114.285 MHZ 114.285 MHZ 114.285 MHZ
Page 39 and 40: DNIOB: High Speed Serial Interfaces
Page 41 and 42: SEAM Expansion DNSEAM_IPASSx4 Add 4
Page 43: DNK7_F5PCIe PC3-800 DDR3 (256M DDR3
Page 47 and 48: IP - PCIe (Gen1,2,3) Slowdown PCIe

FPGA Boards - The Dini Group

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