FPGA Boards - The Dini Group

April 

2013 

v5.0 

FPGA Boards 

ASIC Prototyping 

FPGA-Based High Performance Computing 

Low Latency Trading

FPGA 

Speed Grades 

(slowest to 

fastest) 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(18x18) 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

Xilinx 

Virtex-6 

Kintex-7 Virtex-7 

HXT SXT LXT LX 

VH V 

Spartan 

-6 

LX VX 

7V2000T -1,-2 2,443,200 23,455 14,070 1,200 2,160 2,584 46,512 5,814 

7V585T -1,-2,-3 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578 

7VX1140T -1,-2 1,424,000 13,670 8,200 1,100 3,360 3,760 67,680 8,460 

7VX980T -1,-2 1,224,000 11,750 7,050 880 3,600 3,000 54,000 6,750 

7VX690T -1,-2,-3 866,400 8,317 4,990 1,000 3,600 2,940 52,920 6,615 

7VX550T -1,-2,-3 692,800 6,651 3,990 600 2,880 2,360 42,480 5,310 

7VX485T -1,-2,-3 607,200 5,829 3,500 700 2,800 2,060 37,080 4,635 

7VX415T -1,-2,-3 515,200 4,946 2,970 600 2,160 1,760 31,680 3,960 

7VX330T -1,-2,-3 408,000 3,917 2,350 700 1,120 1,500 27,000 3,375 

7VH870T -1,-2 1,095,200 10,514 6,310 700 2,520 2,820 50,760 6,345 

7VH580T -1,-2 725,600 6,966 4,180 600 1,680 1,880 33,840 4,230 

7K480T -1,-2,-3 597,200 5,733 3,440 400 1,920 1,910 34,380 4,298 

7K420T -1,-2,-3 521,200 5,004 3,000 350 1,680 1,670 30,060 3,758 

7K410T -1,-2,-3 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578 

7K355T -1,-2,-3 445,200 4,274 2,560 300 1,440 1,430 25,740 3,218 

7K325T -1,-2,-3 407,600 3,913 2,350 500 840 890 16,020 2,003 

7K160T -1,-2,-3 202,800 1,947 1,170 400 600 650 11,700 1,463 

7K70T -1,-2,-3 82,000 787 470 300 240 270 4,860 608 

LX760 -1L,-1,-2 948,480 9,105 5,509 1,200 864 1,440 25,920 3,240 

LX550T -1L,-1,-2 687,360 6,599 4,000 1,200 864 1,264 22,752 2,844 

LX365T -1L,-1,-2,-3 455,040 4,368 2,621 600 576 832 14,976 1,872 

LX240T -1L,-1,-2,-3 301,440 2,894 1,736 600 768 832 14,976 1,872 

LX195T -1L,-1,-2,-3 249,600 2,396 1,438 600 640 688 12,384 1,548 

LX130T -1L,-1,-2,-3 160,000 1,536 922 600 480 528 9,504 1,188 

SX475T -1L,-1,-2 595,200 5,714 3,428 600 2,016 2,128 38,304 4,788 

SX315T -1L,-1,-2,-3 394,000 3,782 2,269 600 1,344 1,408 25,344 3,168 

HX565T -1,-2 708,000 6,797 4,078 720 864 1,824 32,832 4,104 

HX380T -1,-2,-3 478,000 4,589 2,753 720 864 1,536 27,648 3,456 

LX150T -2,-3N,-3,-4 184,464 1,771 1,063 540 180 268 4,824 603 

LX150 -1L,-2,-3N,-3 184,464 1,771 1,063 338 180 268 4,824 603 

LX100 -1L,-2,-3N,-3 126,576 1,215 729 326 180 268 4,824 603 

LX75 -1L,-2,-3N,-3 93,000 893 536 280 132 172 3,096 387 

LX45 -1L,-2,-3N,-3 54,576 524 314 316 58 116 2,088 261 

Virtex-5 

FXT SXT LXT LX 

LX330 -1,-2 207,360 3,320 1,990 1,200 192 576 10,368 1,296 

LX220 -1,-2 138,240 2,210 1,330 800 128 384 6,912 864 

LX155 -1,-2,-3 97,280 1,556 934 800 128 384 6,912 864 

LX110 -1,-2,-3 69,120 1,110 670 800 64 256 4,608 576 

LX155T -1,-2,-3 97,280 1,556 934 640 128 424 7,632 954 

LX110T -1,-2,-3 69,120 1,110 666 640 64 296 5,328 666 

LX85T -1,-2,-3 51,840 830 498 480 48 216 3,888 486 

LX50T -1,-2,-3 28,800 460 276 480 48 120 2,160 270 

LX30T -1,-2,-3 19,200 307 184 360 32 72 1,296 162 

SX95T -1,-2,-3 58,880 940 564 640 640 488 8,784 1,098 

SX50T -1,-2,-3 32,640 522 313 480 288 264 4,752 594 

SX35T -1,-2,-3 21,760 392 235 360 192 168 3,024 378 

FX100T -1,-2,-3 64,000 1,024 614 640 256 456 8,208 1,026 

FX70T -1,-2,-3 44,800 717 430 640 128 296 5,328 666 

FX30T -1,-2,-3 20,480 328 197 360 64 136 2,448 306 


Speed Grades 

(slowest to 

fastest) 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(18x18) 

MLAB 

(640) 

M9K 

(9 kbit) 

Memory 

M144K 

(144 kbit) 

M20K 

(20 kbit) 

Total 

(kbits) 

Total 

(kbytes) 

Altera 

Stratix V 

GT GS GX E 

ArriaV GZ 

Stratix IV 

Stratix III 

Cyclone III 

5SEEB -4,-3,-2 1,437,000 13,795 8,280 840 704 15850 2,640 52,800 6,600 

5SEE9 -4,-3,-2 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600 

5SGXAB -4,-3,-2 1,437,000 13,795 8,280 840 704 17960 2,640 52,800 6,600 

5SGXA9 -4,-3,-2 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600 

5SGXA7 -4,-3,-2 939,000 9,014 5,410 840 512 11736 2,560 51,200 6,400 

5SGXB6 -4,-3,-2 902,000 8,659 5,200 600 798 11270 2,660 53,200 6,650 

5SGXB5 -4,-3,-2 740,000 7,104 4,260 600 798 9250 2,100 42,000 5,250 

5SGXA5 -4,-3,-2 740,000 7,104 4,260 840 512 8020 2,304 46,080 5,760 

5SGXA4 -4,-3,-2 634,000 6,086 3,650 696 512 5880 1,900 38,000 4,750 

5SGXA3 -4,-3,-2 513,000 4,925 2,960 696 512 3776 957 19,140 2,393 

5SGSD8 -4,-3,-2 1,050,000 10,080 6,050 840 3926 2624 2,567 51,340 6,418 

5SGSD6 -4,-3,-2 880,000 8,448 5,070 480 3550 2320 2,320 46,400 5,800 

5SGSD5 -4,-3,-2 690,000 6,624 3,970 696 3180 2014 3,180 63,600 7,950 

5SGSD4 -4,-3,-2 543,000 5,213 3,130 696 2088 1062 2,088 41,760 5,220 

5SGSD3 -4,-3,-2 356,000 3,418 2,050 432 1200 686 1,200 24,000 3,000 

5SGTC7 -4,-3,-2 939,000 9,014 5,410 600 512 2560 2,560 51,200 6,400 

5SGTC5 -4,-3,-2 642,000 6,163 3,700 600 512 2304 2,304 46,080 5,760 

5AGZME7 -4,-3 679,200 6,520 3,910 674 2278 5306 1700 34,000 4,250 

5AGZME5 -4,-3 603,840 5,797 3,480 674 2184 4718 1440 28,800 3,600 

5AGZME3 -4,-3 543,360 5,216 3,130 414 2088 1044 957 19,140 2,393 

5AGZME1 -4,-3 332,080 3,188 1,910 414 1600 800 585 11,700 1,463 

4SE820 -4,-3 650,440 10,407 6,504 1120 960 16261 1610 60 23,130 2,891 

4SE530 -4,-3,-2 424,960 6,799 4,080 960 1024 10624 1280 64 20,736 2,592 

3SL340 -4,-3,-2 270,000 4,320 2,592 1120 576 6750 1040 48 16,272 2,034 

3C120 -8,-7 119,088 1,667 1,000 288 0 

432 

3,888 486 

3C16 -8,-7,-6 15,408 216 134 56 0 

56 

504 63 

2 

www.dinigroup.com

WHO, WHAT, WHERE, WHY? 

Who are you? 

The DINI Group was formed in May of 1995. We started as a consulting organization 

specializing in FPGA and board-level design. We branched into ASIC design in 1998, with 

particular emphasis in PCI and PCI-X. Our standard products are the direct result of unmet 

FPGA-based product needs discovered in our consulting practice. At present we have 20 

employees. 

Measured in numbers of gates shipped, we are the world’s 

leading provider of ASIC prototyping hardware. 

What are your products? 

We make big FPGA boards. The most common application for big FPGA boards is ASIC 

and SOC prototyping. Big FPGA boards in specialized configurations can be used to 

accelerate certain types of algorithms. In other configurations, large FPGA boards can be 

used for high frequency, low-latency trading. 

Where? 

We are based in La Jolla, 

California. La Jolla is about 

10 miles north of San Diego. 

Why? 

FPGA Prototyping is rapidly 

becoming a requirement due 

to the complexity and costs 

of ASIC tapeouts and spins. 

But FPGA boards required 

specialized teams to design 

and build. It is much easier and cheaper to buy off-the-shelf FPGA boards from those of us 

that already have that specialized set of skills. 

858 . 454 . 3419 3

Feature Breakdown: DNV7F2A 

iPASS connectors for 

4-lane PCIe GEN2 

SFP+ for 10GbE 

QSPF+ for 

10 and 40 GbE 

Add 40 GbE, 10GbE 

PCIe et al with DNSEAM 

Expansion Cards 

(page 41) 

7V2000T Xilinx Virtex-7 

FPGAs.The largest FPGA 

ever created. 14 million 

ASIC gates plus memory 

and multipliers each! 

POWER! 

75A per FPGA 

for VCCINT 

4 

www.dinigroup.com

HOSTING THE LARGEST FPGA EVER! 

USB 3.0 / 2.0 

Memory / Expansion / Stacking 

DINAR1 

Expansion Connector 

72 

3 

DINAR1 


1 


DINAR1 


0 

DINAR1 


72 

2 

SATA II 

(device) 

4 

72 

72 

72 

72 72 

72 

2 

SATA II 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

10GbE 

Ethernet 

24 

MHz 

SMA 

JTAG 

0 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

G1 

Config Clk OSC 

24 

MHz 

SMA 

114.285 MHz 

8 

1 

1 

PCIe 

(GEN2) 

iPASS 

Frequency 

Synthesizer 

(Si5326) 

4 

G2 


0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

RS232 

PCIe 

(Cabled 

GEN1/GEN2) 

Step Clock 


GTX 

10Gb/s 

NMB0 

YMB 

150 

150 

16 

Virtex-6 

Config FPGA 

PCIe 

40 

NMB1 

40 

YMB 

NMB 1 

NMB 2 


1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

40 

40 

SEAF 

DNNMB 

Connector 

(400 pins) 

5 

5 

5 

Global 

Clocks 

4 

8 

1 

4 

iPASS 

Stacking 

PCIe 

(GEN2) 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

QSFP+ 

10GbE 

Ethernet 

40 GbE or 

4, 10 GbE 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G3 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G4 

10/100/1000 10/100/1000 

baseT 

Phy 

RJ45 

RS232 

USB 2.0 

(2X) 

RGMII 

2 

USB 

EEPROM 

DMA(4x) 

SATA 

PCIe 

Device Bus 

PCIe 

(Gen1) 

4 - lanes 

Marvell MV78200 

FPU FPU 

CPU CPU 

OSC 

64 

3 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

SATA II 

(host) 

2x 

RTC 

4-lanes 

PCIe (GEN1) 

8 

256Mb 

NAND FLASH 

Boot 

PCI EXPRESS 

Cable (GEN1) 

Marvell Processor running Linux host this 

board via USB2.0, Ethernet, or PCIe GEN2 

5 Global Clocks programmable to 

any frequency 2KHz to 710 MHz 

DINAR1 Expansion Connectors 

Add memory (page 32) 

Add custom peripherals 

Add off-the-shelf boards (page 33) 

Stack two boards together (page 12) 

We don’t like hamsters and 

we don’t think hamster cages 

belong in engineering labs! 

858 . 454 . 3419 5

DNV7F4A: Godzilla’s Butcher 



DINAR1 


3 

top 

DINAR1 


1 

DINAR1 


0 

top 

DINAR1 


2 

72 

72 72 72 72 

72 

SATA 

(device) 

1 

72 

72 

1 

SMA 

4x 10GbE 

or 

1x 40GbE 

QSFP+ 

GTX Expansion 

DNSEAM_NS 

- 8-lane PCIe(GEN1/GEN2) 

- 2x CX4 Ethernet 

XAUI 

Infiniband 

- 8x SFP+ 10GbE et al. 

- 2x QSFP+ 40GbE 

- 8x USB 3.0/2.0 

A, B, AB 

- 8x SATA II 

- 8x SMA 

4 

8 

GTX 

GTX 

GTX 

FPGA B 

Virtex-7 

7V2000T 

(FLG1925) 

1 

GTX 

150 150 

40 

YMB 

NMB1 

75 

1 

1 

150 

150 

GTX 

NMB2 

GTX 

1 

75 

GTX 

40 

YMB 

FPGA C 

Virtex-7 

7V2000T 

(FLG1925) 

150 150 

1 GTX 

GTX 

4 

8 

GTX 

GTX 

SFP+ 

GTX Expansion 

DNSEAM_NS 

4x 10GbE 

- 8-lane PCIe(GEN1/GEN2) 

- 2x CX4 Ethernet 

XAUI 

Infiniband 

- 8x SFP+ 10GbE et al. 

- 2x QSFP+ 40GbE 

- 8x USB 3.0/2.0 

A, B, AB 

- 8x SATA II 

- 8x SMA 

4x 10GbE 

or 

1x 40GbE 

GTX Expansion 

DNSEAM_NS 

QSFP+ 

SATA 

(host) 

8 

4 

1 

GTX 

GTX 

GTX 

FPGA A 

Virtex-7 

7V2000T 

(FLG1925) 

1 

NMB0 

75 

75 

150 

150 

GTX 

NMB3 

FPGA D 

Virtex-7 

7V2000T 

(FLG1925) 

8 

4 

1 

GTX 

GTX 

GTX Expansion 

DNSEAM_NS 

SMA 

iPASS 

PCIe (GEN1/GEN2) 

4-lanes 

72 

72 

72 72 72 72 72 

72 

DINAR1 


3 

DINAR1 


1 

DINAR1 


0 

DINAR1 


2 

bottom 

bottom 



SEAF 

RS232 

PCIe 

(Cabled 

GEN1/GEN2) 

Step Clock 

Config Clk 

OSC 

Virtex-6 


PCIe 

YMB 

NMB 1 

NMB 2 

40 

40 

40 

DNNMB 

Connector 

(400 pins) 

5 

5 

5 

Global 

Clocks 

Stacking 

10/100/1000 10/100/1000 

baseT 

Phy 

RJ45 

RS232 

USB 2.0 

(2X) 

RGMII 

2 

USB 

EEPROM 

DMA(4x) 

SATA 

PCIe 

Device Bus 

PCIe 

(Gen1) 

4 - lanes 


FPU 

FPU 

CPU CPU 

OSC 

64 

3 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

SATA II 

(host) 

2x 

RTC 

4-lanes 

PCIe (GEN1) 

8 

256Mb 

NAND FLASH 

Boot 

6 

www.dinigroup.com 

PCI EXPRESS 

Cable (GEN1)

four Virtex-7 FPGAs | 7V2000T-1 | 56 million ASIC gates | stackable 

Features 

• Hosted via 

- 4-lane GEN2 PCIe via iPASS cable, USB2.0 

- 10/100/1000BASE-T Ethernet, or Stand alone 

• Four Xilinx Virtex-7 FPGAs (FLG1925): 

- 7V2000T-2,-1 (fastest to slowest) 

• 56+ million ASIC gates (ASIC measure) when 

stuffed with four 7V2000Ts 

• Memory can be added using DINAR1_SODM204 on 

a DINAR1 expansion connector: 

- DNSODM204_SSRAM (1.8V version) 

- DNSODM204_QUADMIC (four mictor connectors) 

- DNSODM204_SE (mobile SDRAM) 

- DNSODM204_USB (USB2.0 PHY) 

- DNSODM204_DDR2_FAST 

- DNSODM204_QDRII+ 

- DNSODM204_DDR2_2GB 

- DNSODM204_MICTOR_IO (dual Mictor connectors) 

• Marvel MV78200 Discovery Innovation Dual CPU 

- 1 GHz clock 

- Dual USB2.0 ports (Type B connector) 

- Dual Serial-ATA II connectors for 2 external hard 

drives (SATA II) 

- Gigabit Ethernet interface 

• 10/100/1000 GbE (RJ45 connector) 

- Sheeva CPU Core (ARM v5TE compliant) 

• Out-of-order execution 

• Single and double-precision IEEE compliant 

floating point 

• 16-bit Thumb instruction set increases code 

density 

• DSP instructions boosts performance for signal 

processing applications 

• MMU to support virtual memory features 

• Dual Cache: 32 KB for data and instruction, 

parity protected 

• L2 cache: 512 KB unified L2 cache per CPU 

(total of 1MB), ECC protected. 

- 1 GB external DDR2 SDRAM 

• Organized in a 128M x 64 configuration 

• 400 MHz (800 MHz data rate with DDR) 

- RS232 port for terminal-style observation 

- After configuration, both CPUs dedicated entirely 

to user application 

- Linux operating system 

• Source and examples provided via GPL license 

(no charge) 

• ~15 seconds to CPU boot 

• Five independent low-skew global clock networks 

and single fixed clock 

- Five, high-resolution, user-programmable synthe 

sizers for G0, G1, G2 

• Silicon Labs Si5326: 2kHz to 945 MHz 

- User configurable via Marvell uP RS232, USB, 

PCIe, or Ethernet 

- Global clocks networks distributed differentially 

and balanced 

• Flexible customization and stacking via 2 daughter 

cards positions per FPGA 

- DINAR1 expansion connector 

• Connector: non-proprietary; readily available; cheap 

- 72 LVDS pairs + clocks (or 144 single-ended) 

- 700 MHz on all signals with source synchronous LVDS 

- Signal voltage set by daughter card (+1.2V to +1.8V) 

- Reset 

- Supplied power rails (fused): 

• +12V (24W max), +3.3V (10W max) 

- Pin multiplexing to/from daughter cards using 

LVDS (up to 10x) 

• Fast and Painless FPGA configuration 

- USB, cabled PCIe, Ethernet, JTAG 

- Stand-alone configuration with USB stick 

- Configuration Error reporting 

- Accelerated configuration readback for advanced debug 

• RS232 port for embedded FPGA-based SOC uP debug 

- Accessible from all FPGAs via separate 2-signal bus 

• Full support for embedded logic analyzers via 

JTAG interface 

- ChipScope, Tektronix Veridae 

• Status FPGA-controlled LEDs 

- Enough multicolored LEDs to blind a hamster. 

Virtex-7 


Speed Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

7V2000T -1,-2 6-input 2,443,200 23,455 14,070 1200 2,160 2,584 46,512 5,814 

858 . 454 . 3419 7

DNV7F2A: Twin of Godzilla’s Life Coach 

USB 3.0 / 2.0 


DINAR1 


72 

3 

DINAR1 


2 


DINAR1 


0 

DINAR1 


72 

1 

SATA II 

(device) 

4 

72 

72 

72 

72 72 

72 

2 

SATA II 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

10GbE 

Ethernet 

24 

MHz 

SMA 

JTAG 

0 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

G1 


24 

MHz 

SMA 

114.285 MHz 

8 

1 

1 

PCIe 

(GEN2) 

iPASS 

Frequency 

Synthesizer 

(Si5326) 

4 

G2 


1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

RS232 

PCIe 

(Cabled 

GEN1/GEN2) 

Step Clock 


GTX 

10Gb/s 

NMB0 

YMB 

150 

150 

16 

Virtex-6 


PCIe 

40 

NMB1 

40 

YMB 

NMB 1 

NMB 2 


0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

40 

40 

SEAF 

DNNMB 

Connector 

(400 pins) 

5 

5 

5 

Global 

Clocks 

4 

8 

1 

4 

iPASS 

Stacking 

PCIe 

(GEN2) 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

QSFP+ 

10GbE 

Ethernet 

40 GbE or 

4, 10 GbE 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G3 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G4 

10/100/1000 10/100/1000 

baseT 

Phy 

RJ45 

RS232 

USB 2.0 

(2X) 

RGMII 

2 

USB 

EEPROM 

DMA(4x) 

SATA 

PCIe 

Device Bus 

PCIe 

(Gen1) 

4 - lanes 


FPU 

FPU 

CPU CPU 

OSC 

64 

3 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

= LVDS when paired, but can be run 

single-ended at a reduced frequency 

SATA II 

(host) 

2x 

RTC 

4-lanes 

PCIe (GEN1) 

PCI EXPRESS 

Cable (GEN1) 

8 

256Mb 

NAND FLASH 

Boot 

Virtex-7 

V 

VX 


Speed 

Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

(1761) 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total (kbits) 

Total (kbytes) 

7V2000T -1,-2 6-input 2,443,200 23,455 14,070 850 2,160 2,584 46,512 5,814 

7V585T -1,-2,-3 6-input 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578 

7VX690T -1,-2,-3 6-input 866,400 8,317 4,990 850 3,600 2,940 52,920 6,615 

7VX485T -1,-2,-3 6-input 607,200 5,829 3,500 750 2,800 2,060 37,080 4,635 

7VX330T -1,-2,-3 6-input 408,000 3,917 2,350 750 1,120 1,500 27,000 3,375 

8 

www.dinigroup.com

two Virtex-7 FPGAs | 7V2000T-1 | 28 million ASIC gates | stackable 

Features 


- 4-lane GEN2 PCIe via iPASS cable 

- USB2.0 

- 10/100/1000BASE-T Ethernet 

- Stand alone 

• Dual Xilinx Virtex-7 FPGA: 


- 7VX690T-3,-2,-1 


stuffed with two 7V2000T 

• GTP low-powered transceivers (assumes -2 speed 

grade or faster for 10GbE): 

- FPGA 0: 

• 2 SFP+ sockets 

• 4 channels SATA II (device) 

• USB3.0 

• 2 channels using SMA connectors 

• 4-lane PCIe GEN1/GEN2 prototyping via 

iPASS cable 

• Dual SEARAY GTP Expansion headers, 

8-lanes each. 

• PCIe,CX4,4 SFP+ sockets or custom 

- FPGA 1: 

• QSFP+ socket 

• 4 lanes 10GbE or single lane 40 GbE Ethernet 

• 1 SFP+ socket 

• 2 channels SATA II (device) 

• 4-lane PCIe GEN1/GEN2 prototyping via 

iPASS cable 

• Dual SEARAY GTP Expansion headers, 

8-lanes each 

• PCIe,CX4,4 SFP+ sockets, SMA or custom 

- Marvel MV78200 Discovery Innovation Dual CPU 

• 1 GHz clock 

• Dual USB2.0 ports (Type B connector) 

• Dual Serial-ATA II connectors for 2 external 

hard drives (SATA II) 

• Gigabit Ethernet interface 


• Sheeva CPU Core (ARM v5TE compliant) 











• 1 GB external DDR2 SDRAM 



• RS232 port for terminal-style observation 

• After configuration, both CPUs dedicated entirely 


• Linux operating system 


(no charge) 


- Five independent low-skew global clock networks 

• G0, G1, G2, G3, G4 

• Five, high-resolution, user-programmable syn 

thesizers for G0, G1, G2, G3 and G4 


• User configurable via Marvell uP RS232, USB, 


• Global clocks networks distributed differen 

tially and balanced 

- Flexible customization via 2 daughter cards positions 

per FPGA 

• DINAR1 expansion connector 

• Connector is non-proprietary, readily available, 

and cheap 

• 72 LVDS pairs + clocks (or 150 single-ended) 

• 700 MHz on all signals with source synchronous 

LVDS 

• Signal voltage set by daughter card (+1.2V to +1.8V) 

• Reset 

• Supplied power rails (fused): 

• +12V (24W max) 

• +3.3V (10W max) 

• Pin multiplexing to/from daughter cards using 


• Support FMC, logic analyzer, memory expansion 

- Fast and Painless FPGA configuration 

• USB, cabled PCIe, Ethernet, JTAG 

• Stand-alone configuration with USB stick 

• Configuration Error reporting 

• Accelerated configuration readback for advanced 

debug 

- RS232 port for embedded FPGA-based SOC µP debug 

• Accessible from all FPGAs via separate 2-signal bus 

- Full support for embedded logic analyzers via 


• ChipScope, Tektronix Veridae 

- Status FPGA-controlled LEDs 

• Enough multicolored LEDs to illuminate a 

medium sized dungeon 

858 . 454 . 3419 9

DNV7F1A: Godzilla’s Life Coach 

24 

MHz 

SMA 

24 

MHz 

SMA 

24 

MHz 

SMA 

DDR3 

IDELAY Refclk 

DDR3 

Refclk 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

OSC 

OSC 

G0 

G1 

G2 

RS232 

PCIe 

(Cabled 

GEN1/GEN2) 

10GBE 

Ethernet 

USB 3.0 / 2.0 

Virtex-6 


SFP+ Socket 

SFP+ Socket 

SFP+ Socket 

SFP+ Socket 

PCIe 

2 

1 

0 

SMA 

SATA II 

(device) 

1 

0 

GTX Expansion 

DNSEAM_NS 

NMB 

JTAG 

OSC 

1 

1 

1 

1 

8 

Config Clk 

PCIe 

(GEN2) 

1 

3 

4 

8 

PCIe 

(GEN2) 

iPASS 

iPASS 

EEPROM 


Virtex-7 

7VX690T/7V585T/ 

7V2000T 

[F(F/L/H)G1761] 

4 

4 

DDR3 UDIMM 

(16GB Max) 

SPI 

148 

8 

LED 

(x8) 

40 

34 

72 

72 

72 

72 

72 

72 

0 

1 

21 

DINAR1 


DINAR1 


DINAR1 


Step Clock 

10/100/1000 10/100/1000 

baseT 

Phy 

RJ45 

RS232 

USB 2.0 

(2X) 

RGMII 

2 

USB 

DMA(4x) 

SATA 

EEPROM 

PCIe 

Device Bus 

PCIe 

(Gen1) 

4 - lanes 


FPU 

FPU 

CPU CPU 

OSC 

64 

3 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

MICTOR 

18 

40-pin 

IDC 

(0.1”) 

SATA II 

(host) 

2x 

RTC 

4-lanes 

PCIe (GEN1) 

8 

256Mb 

NAND FLASH 

Boot 

Features 

PCI EXPRESS 

Cable (GEN1) 


- 4-lane GEN1/2 PCIe (v1.1) via iPASS cable 

- USB2.0 


- Stand alone 

• Single Xilinx Virtex-7 FPGA: 


- 7VX690T-3,-2,-1 

- 7VX585T-3,-2,-1 

- 7VX485T-3,-2,-1 

- 7VX330T-3,-2,-1 


stuffed with 7V2000T 

• GTP low-powered transceivers (assumes -2 speed 

grade or faster for 10GbE): 

10 

www.dinigroup.com

single Virtex-7 FPGA | 7V2000T-1 | 14 million ASIC gates 

- 4 SFP+ sockets supports modules for any of the 

following interfaces: 

• 10 Gigabit Optical Ethernet 

• 10GBase-SR 10GBASE-LR 10GBASE-LRM 

10GBase-ER 

• 10 Gigabit Copper Ethernet 

• 10GBASE-R direct attach 

• 10 Gigabit Sonet: 10GBase-LW 

• 10 Gigabit FibreChannel 

- SATA II (device) 

- USB3.0 

- 2 channels using SMA connectors 

- Dual, 4-lane PCIe GEN1/GEN2 prototyping via 

iPASS cable 

- Dual SEARAY GTP Expansion headers, 8-lanes each 

• PCIe 

• CX4 

• 4 SFP+ sockets 

• custom 

• 240-pin DDR3 UDIMM 

- 72-bit data width (64-bit with 8-bit ECC) 

- 800 MHz operation, PC3-12800 

- Addressing/power to support 16GB (+ ECC) 

- DDR3 Verilog/VHDL reference design provided 

(no charge) 

- Optional RLDRAM DIMM instead of DDR3 for 

ultra low latency 

- Alternate pin compatible memory cards available 

(consult factory for availability): 

• SRAM: QDR, ASYNC, STD, or PSRAM, Flash 

• DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR2 

• Mictor, USB PHY, Extra Interconnect 


- 1 GHz clock 










• 16-bit Thumb instruction set increases code density 






Virtex-7 

V 

VX 


Speed 

Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Max 

(100% util) 

(1000's) 











(no charge) 


• Three independent low-skew global clock networks 

- G0, G1, G2 

- Three, high-resolution, user-programmable synthesizers 

for G0, G1, G2 


- User configurable via Marvell uP RS232, USB, 


- Global clocks networks distributed differentially 

and balanced 

• Flexible customization via 3 daughter cards positions 

- DINARI expansion connector 

• Connector is non-proprietary, readily available, 

and cheap 


- 700 MHz on all signals with source synchronous LVDS 

- Signal voltage set by daughter card (+1.2V to +1.8V) 

- Reset 


• +12V (24W max) 

• +3.3V (10W max) 

- Pin multiplexing to/from daughter cards using 



- USB, cabled PCIe, Ethernet, JTAG 

- Stand-alone configuration with USB stick 



• RS232 port for embedded FPGA-based SOC µP debug 




- ChipScope, Veridae, and other third-party debug 

solutions 


- Enough multicolored LEDs to light a fish tank. 

Gate Estimate 

Practical 

(60% util) 

(1000's) 

Max I/O's 

(1761) 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total (kbits) 

Total (kbytes) 

7V2000T -1,-2 6-input 2,443,200 23,455 14,070 850 2,160 2,584 46,512 5,814 

7V585T -1,-2,-3 6-input 728,400 6,993 4,200 850 1,260 1,590 28,620 3,578 

7VX690T -1,-2,-3 6-input 866,400 8,317 4,990 850 3,600 2,940 52,920 6,615 

7VX485T -1,-2,-3 6-input 607,200 5,829 3,500 750 2,800 2,060 37,080 4,635 

7VX330T -1,-2,-3 6-input 408,000 3,917 2,350 750 1,120 1,500 27,000 3,375 

858 . 454 . 3419 11

SMA 

SMA 

SMA 

SMA 

SMA 

Stacking the DNV7F2A 

Stacking two DINI Virtex-7 FPGA boards 

Two boards can be ganged together to increase the amount of available FPGA resources. 

This example uses the DNV7F2A. In this example, shown in figure 1, two DNV7F2A 

cards are ganged together, seamlessly doubling the functionality. A DDR3 memory module 

is added to each of the FPGA cards. 

The cable 

We use a custom Samtec cable, DINAR1_CBL to connect the signals across the connectors 

of the two boards. You get these cables from us. The DINAR1_CLB is a high 

speed coax cable designed specifically to connect two 400-pin Samtec SEAM connectors 

together. Initially these cables are 30”, but eventually we will have several different 

lengths. 

The busses: YMB and NMB 

The first cable, marked in Figure 1 with as ‘1’, is required. This cable connects the YMB 

busses together and adds a bus between the Config FPGAs on the two boards. The second 

bus is used to connect the NMB busses from the slave FPGA card to the master FPGA 

card. Full NMB functionality is maintained including DMA data movement between all 

FPGAs. Also, the host system sees all FPGAs as if they were placed on a single circuit 

board. The data from the NMB busses on the slave card must be re-clocked in the slave’s 

Config FPGA, so this adds a few clock cycles of latency. The raw performance measured 

in terms of GB/s is not compromised. FPGA and other configuration data of the slave 

DNV7F2A is transferred over this second bus. Configuration of the slave FPGA board is 

also transparent to the host system and software. 

FPGA to FPGA Interconnect between boards 

The DNV7F2A has 4 expansion connectors, two per FPGA. These connectors are yellow 

in the block diagram and labeled 0 thru 3. When stacking two DNV7F2As, you can 

connect ANY DINAR1 expansion connector to any other DINAR1 Expansion connector 

using a DINAR1_CBL. It is perfectly reasonable to connect all four DINAR1 cables between 

the two DNV7F2As, but that would leave no expansion position open for memory 

or external peripherals. In the example shown in v 1, I connected three of the expansion 

connectors together: 

FPGA 0 DINAR1 3 (master DNV7F2A) → FPGA 1 DINAR1 0 (slave) 



I choose these connections because it was easy to draw and not for any practical reason. 

Each of these cables carries 72 LVDS pairs, along with clocks, IDs and resets. I will state 

again: You can connect ANY DINAR1 connector to any other DINAR1 connector. Note 

that if you want to increase the interconnect between the FPGAs on a stand-alone DN- 

V7F2A, you would not use the DINAR1_CBL. Use the DINAR1_INTERCON instead. 

DDR3 Memory 

I added a DINAR1_SODM204 to the spare DINAR1 connector on each DNV7F2A. This 

card hosts a 204-pin SODIMM memory module. In the block diagram, I put an 8 GB 

DDR3 memory module in the socket. You aren’t limited to DDR3. We have several other 

SODIMMs that work fine in this slot: 

• DNSODM204_SSRAM (1.8V version) (SSRAM) 

• DNSODM204_QUADMIC (4 Mictor connectors) 

• DNSODM204_SE (Flash and Mobile SDRAM) 

• DNSODM204_USB (USB2.0 Phy) 

• DNSODM204_DDR2_FAST (DDR2) 

• DNSODM204_QDRII+ (QDRII+ SSRAM) 

• DNSODM204_DDR2_2GB (more DDR2, larger) 

• DNSODM204_MICTOR_IO (2 Mictors) 

Overview 

Figure 2 shows the final functionality of the two DNV7F2As as seen from the host. 

12 


DINAR1_CABLE 

24 

MHz 

24 

MHz 

YMB + NMB 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

G3 

40 GbE or 

4, 10 GbE 

10GbE 

Ethernet 

24 

MHz 

24 

MHz 

Figure 1 

10GbE 

Ethernet 

USB 3.0 / 2.0 

SATA II 

(device) 

JTAG 

SATA II 

0 

1 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

QSFP+ 

SFP+ Socket 

DNSEAM_NS 

GTX Expansion 

G1 

G4 

2 

4 

5 

6 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

24 

MHz 

1 

Config Clk 

DINAR1_SODM204 


10/100/1000 

baseT 

USB 2.0 

(2X) 

Stacking 

PCIe 

(GEN2) 

iPASS 

4 

DINAR1 


OSC 

114.285 MHz 

1 

8 

8 

1 

1 

PCIe 

(GEN2) 

iPASS 

Frequency 

Synthesizer 

(Si5326) 

4 

RJ45 

RS232 

SATA II 

(host) 

2x 

Global 

Clocks 

72 

72 

DINAR1 


DDR 3 

DDR 3 

72 

72 

4 

G2 

3 

10/100/1000 

Phy 

6Mb 

FLASH 

oot 

8Mb 

SPI 

FLASH 

x 64 

DR2 

5 

5 

5 

DNNMB 

onnector 

400 pins) 

T 

T 

761] 

A 

0 

r 

Ex 

FP 

7V 

7V 

[F(F/H 

GEN1 

Step Clo 

RGM 

2 

R

SMA 

SMA 

SMA 

SMA 

SMA 

SMA 

SMA 

SMA 

SMA 

SMA 

four Virtex-7 FPGAs | 7V2000T-1 | 56 million ASIC gates 



DINAR1 


3 

DINAR1 


2 

DINAR1 


0 

DINAR1 


1 

USB 3.0 / 2.0 

72 

72 

SATA II 

(device) 

4 

72 

72 

72 

72 72 

72 

2 

SATA II 

PCI EXPRESS 

Cable (GEN1) 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

10GbE 

Ethernet 

24 

MHz 

JTAG 

0 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

G1 

24 

MHz 


8 

1 

1 

PCIe 

(GEN2) 

iPASS 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

4 

G2 


1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

PCIe 

(Cabled 

GEN1/GEN2) 

Step Clock 

RS232 


GTX 

10Gb/s 

NMB0 

YMB 

150 

150 

16 

Virtex-6 


PCIe 

40 

NMB1 

40 

YMB 

NMB 1 

NMB 2 

40 

40 


0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

SEAF 

DNNMB 

Connector 

(400 pins) 

5 

5 

5 

Global 

Clocks 

8 

1 

4 

4 

PCIe 

(GEN2) 

iPASS 

Stacking 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

QSFP+ 

10GbE 

Ethernet 

40 GbE or 

4, 10 GbE 

25 

NAND 

B 

Boot 

128M 

D 

12 

8 

3 

64 

OSC 

CPU 

4-lanes 

PCIe (GEN1) 

PCIe 

(Gen1) 

4 - lanes 

CPU 

FPU FPU 

Device Bus 

PCIe 


EEPROM 

DMA(4x) 

SATA 

RTC 

USB 

2 

RGMII 

Step Clock 

10/100/1000 

Phy 

SATA II 

(host) 

2x 

RS232 

RJ45 

USB 2.0 

(2X) 

10/100/1000 

baseT 

G4 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

24 

MHz 

G3 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

24 

MHz 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G3 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 



G4 

10/100/1000 

baseT 

RJ45 

USB 2.0 

(2X) 

RS232 

SATA II 

(host) 

2x 

10/100/1000 

Phy 

RGMII 

2 

USB 

EEPROM 

DMA(4x) 

SATA 

RTC 

PCIe 

Device Bus 

PCI EXPRESS 

Cable (GEN1) 

PCIe 

(Gen1) 

4 - lanes 


FPU FPU 

CPU CPU 

4-lanes 

PCIe (GEN1) 

OSC 

64 

3 

8 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

40 

40 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

Config Clk 

OSC 

NMB0 

GTX 

10Gb/s 

YMB 

NMB1 

YMB 

SEAF 

JTAG 

RS232 

PCIe 

(Cabled 

GEN1/GEN2) 

Config Clk 

OSC 

Virtex-6 


PCIe 

NMB 1 

40 

150 

16 

150 

USB 3.0 / 2.0 

SATA II 

(device) 

10GbE 

Ethernet 

FPG 

0 

7VX690 

7V2000 

[F(F/H)G1 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

24 

MHz 

0 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G1 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G2 

NMB 2 

C 

( 

1 

72 72 

DINAR1 

Expansion Connecto 

4 

PCIe 

(GEN2) 

iPASS 

40 

8 

1 

72 

4 

72 

DINAR1 



1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

72 

72 

2 

DINAR1 


3 

FPGA to FPGA 

Interconnect 

DINAR1_CABLE 

2 3 4 


Interconnect 

DINAR1_CABLE 


Interconnect 

DINAR1_CABLE 

SLAVE 

DINAR1 

pansion Connector 

2 

DINAR1 


0 

DINAR1 


1 

72 

GA 

1 

X690T 

2000T 

)G1761] 

PCIe 

(Cabled 

/GEN2) 


II 

S232 

ck 

72 

USB 

72 

EEPROM 

DMA(4x) 

SATA 

RTC 

GTX 

10Gb/s 

NMB0 

PCIe 

Device Bus 

YMB 

Virtex-6 


PCI EXPRESS 

Cable (GEN1) 

150 

150 

16 

40 

PCIe 

PCIe 

(Gen1) 

4 - lanes 

4-lanes 

PCIe (GEN1) 

NMB1 

40 

YMB 


FPU FPU 

CPU CPU 

NMB 1 

NMB 2 

72 72 

40 

40 

OSC 


0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

64 

3 

8 

SEAF 

DNNMB 

Connector 

(400 pins) 

5 

5 

5 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

72 

Global 

Clocks 

8 

1 

4 

4 

PCIe 

(GEN2) 

iPASS 

Stacking 

2 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

QSFP+ 

SATA II 

10GbE 

Ethernet 

40 GbE or 

4, 10 GbE 

MASTER 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

40 GbE or 

4, 10 GbE 

10GbE 

Ethernet 

10GbE 

Ethernet 

24 

MHz 

JTAG 

SATA II 

USB 3.0 / 2.0 

SATA II 

(device) 

0 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

QSFP+ 

SFP+ Socket 

DNSEAM_NS 

GTX Expansion 

G1 

2 

4 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

24 

MHz 

Config Clk 

PCIe 

(GEN2) 

iPASS 

4 

OSC 

1 

8 

8 

1 

1 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

4 

PCIe 

(GEN2) 

iPASS 

4 

G2 


S0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

PCIe 

(Cabled 

GEN1/GEN2) 

4GB SODIMM 


M1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

RS232 

Config Clk 

OSC 

16 

40 

SNMB1 

YMB 

NMB0 

GTX 

10Gb/s 

NMB1 

150 

150 

40 40 

YMB 

NMB0 

72 72 

144 144 

DDR 3 

SNMB0 

150 

150 

GTX 

10Gb/s 

NMB1 

Virtex-6 


PCIe 

YMB 

16 

40 


S1 

7VX690T 

7V2000T 

[F(F/H)G1761] 

4GB SODIMM 

DDR 3 


M0 

7VX690T 

7V2000T 

[F(F/H)G1761] 

4 

PCIe 

(GEN2) 

iPASS 

4 

1 

1 

8 

8 

1 

OSC 

4 

iPASS 

PCIe 

(GEN2) 

Config Clk 

SFP+ Socket 

DNSEAM_NS 

GTX Expansion 

4 

2 

GTX Expansion 

DNSEAM_NS 

SFP+ Socket 

QSFP+ 

SATA II 

(device) 

USB 3.0 / 2.0 

SATA II 

10GbE 

Ethernet 

10GbE 

Ethernet 

40 GbE or 

4, 10 GbE 

SLAVE 

SMA 

SMA 

SMA 

Step Clock 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G3 

24 

MHz 

SMA 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G4 

10/100/1000 

baseT 

RJ45 

USB 2.0 

(2X) 

RS232 

10/100/1000 

Phy 

RGMII 

2 

USB 

EEPROM 

PCIe OSC 

(Gen1) 

4 - lanes 

Device Bus 

Marvell MV78200 64 

FPU FPU 

DMA(4x) 

CPU CPU 3 

SATA PCIe 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 



Figure 2 

SATA II 

(host) 

2x 

RTC 

PCI EXPRESS 

Cable (GEN1) 

4-lanes 

PCIe (GEN1) 

8 

256Mb 

NAND FLASH 

Boot 

MASTER 

858 . 454 . 3419 13

DNS5GX_F2: Monster’s Evil Interior Decorator 

DC0 

MEG Array Expansion 

connector (400-pin) 

180 

unidirectional LVDs when paired. 

Can be used single-ended at 

reduced frequencies. 

DC1 



180 

NMB0 

40 

DDR3 SODIMM 

(4GB Max) 

140 


0 

Stratix-5 

5SGXA5, A7, A9, AB 

5SGSD6, D8 

(F1932) 

96 

96 

96 

96 


1 

Stratix-5 

5SGXA5, A7, A9, AB 

5SGSD6, D8 

(F1932) 

140 

DDR3 SODIMM 

(4GB Max) 

iPASS 

NMB1 

40 

14.1 GHz XCVR 

24 

OOB 

32 

14.1 GHz XCVR 

OOB 

24 32 

14.1 GHz XCVR 

OOB 

24 32 

14.1 GHz XCVR 

OOB 

24 32 

PCIe 

Cable 

(GEN 2) 

Expansion 

Header 

4 

segm 

8 

GTX 


Config 

Stratix-5 

5SGXA3, A4, A5, 

A7, 5SGSD5, D6, D8 

(F1517) 

8 

GTX 

Expansion 

Header 

IOB0 

IOB1 

IOB2 

IOB3 

segm 

10/100/1000 10/100/1000 

baseT 

Phy 

RJ45 

RS232 

USB 

2.0 

(2x) 

SATA II 

(host) 

2x 

RGMII 

USB 

DMA(4x) 

SATA 

RTC 

MPP Bus 

PCIe 

PCIe 

(Gen1) 

4 - lanes 


FPU 

CPU CPU 

4-lanes 

PCIe (GEN1) 

FPU 

OSC 

64 

3 

8 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

IOB Options (each position): 

100 Gigabit Ethernet (via CFP) 

40 Gigabit Ethernet (via CFP) 

Quad QSFP+ (10 GbE) 

Octal SFP+ (10GbE) 

GEN1 / GEN2 / GEN 3 PCIe 

USB3 

SMAs 

iPASS 

14 


PCI Express Cable 

(GEN 1) 

Features 

• Cabled PCIe-hosted logic prototyping system 

- 2 - Altera Stratix V FPGAs 

• 5SGXAB,A9,A7,A5 (largest to smallest) 

-for logic prototyping 

• 5SGSD8,D6 

-for signal processing 

- 100% FPGA resources available for user application 

• 16.6M+ ASIC gates (reasonable ASIC measure) with 

two 5SGXAB 

- 7,852 - 18x18 multipliers with dual 5SGSD8 (8M 

gates of logic) 

• 4 configurable high speed serial interface card slots 

(IOB), 2 per FPGA 

- 12 - 14.1 GHz serial links per slot 

- 32 - general purpose I/O for out of band signaling (OOB) 

- Options interfaces include: 

• 100 GbE Ethernet (via CFP module) 

• 40 GbE Ethernet, Quad QSFP+, Octal SFP+ 

• GEN1/GEN2 PCIe, USB3, SMAs

dual Altera Stratix V FPGAs | 5SGXAB | 16.5 million ASIC gates 

• FPGA to FPGA interconnect is single-ended or LVDS 

- 700 MHz LVDS chip-to-chip DDR with -2 speed 

grade (1.4 Gb/s) 

- Reference designs for integrated I/O pad shift registers 

• 10x FPGA to FPGA pin multiplexing per 

LVDS pair 

• Greatly simplified logic partitioning 

• Source synchronous clocking for LVDS 

• 2 separate DDR3 SODIMMs, PC3-8500 

- 64-bit data with addressing/power to support 4GB 

- DDR3 Verilog reference design provided (no charge) 

• VHDL on special request 


- 1 GHz clock 










• 16-bit Thumb instruction set increases code density 
















(no charge) 


• 3 board-level global clock networks (GCLK[2:0]) 

- Separate programmable synthesizers for each 

network (Si5326) 

• Ultra-low jitter 

• 2 kHz - 710 MHz 

• User configurable via USB, PCIe, et al. 

- Alternate clock sources: 

• Config FPGA 

-single-step, divide 

• SMA for external clock insertion 

- 2 Daughter Card global clock networks 

• Allows insertion of global clock from daughter card 

• 2x 400-pin MEG-Array connectors for daughter 

card expansion 

- 180 signals 

- 700MHz on all signals with source synchronous LVDS 

- Reset, presence detect 


• +12V (24W max), +5V (10W max), +3.3V (10W max) 

- Pin multiplexing to/from daughter cards with 


• Auspy AES models for partitioning assistance 

- Hooks and models for other third-party 

partitioning solutions 


- USB, PCIe, Ethernet et al. 

- Integrated sanity checks on configuration files 

• Custom base plate (standard) and optional rackmount 

chassis 

- Provides protection from those drooling engineers 



- SignalTap, Veridae, and other third party debug tools 

• Convert MEG-Array expansion connectors to 

interconnect with the DNMEG_Intercon. 

• Enough status LEDs to function as a bathroom nightlight 

Stratix-5 

GS GX 


Gate Estimate 

Memory 

Speed Grades 

LUT 

Max Practical 

(slowest to 

FF's 

Size 

MLAB M20K Total Total 

(100% util) (60% util) 

fastest) 

(1000's) (1000's) 

(640) (20 kbit) (kbits) (kbytes) 

5SGXAB -4,-3,-2 6-input 1,437,000 13,795 8,280 840 704 17960 2,640 52,800 6,600 

5SGXA9 -4,-3,-2 6-input 1,268,000 12,173 7,300 840 704 15850 2,640 52,800 6,600 

5SGXA7 -4,-3,-2 6-input 939,000 9,014 5,410 840 512 11736 2,560 51,200 6,400 

5SGXA5 -4,-3,-2 6-input 740,000 7,104 4,260 840 512 8020 2,304 46,080 5,760 

5SGXA4 -4,-3,-2 6-input 634,000 6,086 3,650 696 512 5880 1,900 38,000 4,750 

5SGXA3 -4,-3,-2 6-input 513,000 4,925 2,960 696 512 3776 957 19,140 2,393 

5SGSD8 -4,-3,-2 6-input 1,050,000 10,080 6,050 840 3926 2624 2,567 51,340 6,418 

5SGSD6 -4,-3,-2 6-input 880,000 8,448 5,070 480 3550 2320 2,320 46,400 5,800 

5SGSD5 -4,-3,-2 6-input 690,000 6,624 3,970 696 3180 2014 3,180 63,600 7,950 

Max I/O's 

Multiplier 

s (18x18) 

858 . 454 . 3419 15

DNPCIe_10G_K7_LL 

Xilinx Kintex-7 

Son of Godzilla’s Bad Hair Day 

PC3-10600 

DDR3 DIMM 

(512M x 72) 

123 

10GBASE-ER 

10 GBASE-SR 

10GBASE-KR 

Fiber: 

COPPER: 

10GbE SFP+ 

10GbE SFP+ 

GPS 


Xilinx 

Kintex-7 

7K325T / 7K410T 

(FFG 676) 

control 

18 

QDRII+ 

SRAM 

(4Mx18) 

D in D Out 

FLASH 

(1Gbit) 

18 

Time Sync 

4 

Cost Effective 

Low Latency 

Networking! 

4-Lane PCIe 

GEN1 / GEN2 

4-lane electrical 

16-lane mechanical 

16 

www.dinigroup.com

single Xilinx Kintex-7 FPGA | QDRII+ and DDR3 

Features 

• 2 separate 10GbE LAN/WAN using SFP+ modules 

- Customized IP for packet analysis with minimum latency 

• Hosted in a 4-lane GEN1 or GEN2 PCIe slot 

- 16-lane mechanical 

- Low profile, short length form factor 

• Fully compatible with our TCP Offload Engine (TOE) 

• FIX board support package (DN_FBSP). Functioning reference design with: 

- 10-Gigabit Ethernet MAC 

- TCP/IP Offload Engine (TOE) 

- FIX protocol parser 

- Tick Filter (optional) 

- PCIe Interface (4-lane, GEN2) 

- Memory 

• QDR2 II+ Controller 

• DDR3 Controller 

• Xilinx Kintex-7 FPGA (FFG676) : 

- 7K410T-3,-2,-2L (fastest to slowest) 

- 7K325T-3,-2,-2L 

- 3M ASIC gates (ASIC measure) when stuffed with Kintex-7 7K410T 

• 254k flip-flop/6-input LUTs (708k total FFs) 

• 3.578 Kbytes total FPGA block memory (1590, 18 kbit blocks) 

• 1540, 25x18 multipliers 

• Bulk memory: DDR3 Mini-uDIMM 


- 666.5MHz operation, PC3-10600 (single rank) 

- Addressing/power to support 4GB 

- DDR3 Verilog/VHDL reference design provided (no charge) 

• Optimized DDR3 controller for lowest latency bulk memory access 

- Optional RLDRAM Mini-DIMM instead of DDR3 for ultra low latency 

• QDRII+ SRAM memory: 2M x 18 (72Mb) 

- Separate 18-bit read and write ports 

- 500 MHz bus operation, DDR (double data rate) 

• Fast enough to be clocked at 312.50 MHz 

• Eliminates clock synchronization delays between memory and Ethernet clock 

• SMBus-based thermal management 

• GPS input for precise message time stamping and tracking 

• Full support for embedded logic analyzers via JTAG interface 

- ChipScope and other third-party debug solutions: 

• Veridae, SpringSoft 


- Enough light to make your houseplants happy 

Kintex-7 


Speed Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

7K410T -1,-2,-3 6-input 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578 

7K325T -1,-2,-3 6-input 407,600 3,913 2,350 500 840 890 16,020 2,003 

7K160T -1,-2,-3 6-input 202,800 1,947 1,170 400 600 650 11,700 1,463 

858 . 454 . 3419 17

DNPCIe_10G_K7_LL_QSFP Xilinx Kintex-7 

Daughter of Godzilla’s Bad Hair Day 

PC3-10600 

DDR3 VLP Mini-uDIMM 

(512M x 64) 

4x 10GbE 

or 

1x 40GbE 

USB 2.0 

QSFP+ 

GPS 

Time Sync 

GTX 4 

2 

RS232 

GTX 


Xilinx 

7K325T / 7K410T 

(FFG 676) 

control 

18 

QDRII+ 

SRAM 

(4Mx18) 

D in D Out 

FLASH 

(1Gbit) 

18 

(Type B) 

USB 

JTAG / UART 


LED 

(X8) 

JTAG 

( +1.8V) 

QDRII+ 

CPLD 

4-Lane PCIe 

GEN1 / GEN2 / GEN3 

4-lane electrical 

16-lane mechanical 

18 

www.dinigroup.com

single Xilinx Kintex-7 FPGA | QDRII+ and DDR3 | QSFP+ 

Features 

• QSFP+ socket 

- 4 ports 10GbE LAN/WAN using SFP+ modules OR 

- 1 port 40 GbE 

• Hosted in a 4-lane GEN1/GEN2/GEN3 PCIe slot 

- 16-lane mechanical 

- Low profile, short length form factor 

- GEN1/GEN2 PCIe bridge provided 

• GEN3 supplied by user 

• Fully compatible with our TCP Offload Engine (TOE) 

• FIX board support package (DN_FBSP). Functioning reference design with: 

- 10-Gigabit Ethernet MAC and 40 GbE MAC 

- TCP/IP Offload Engine (TOE) 

- FIX protocol parser 

- Tick Filter (optional) 

- PCIe Interface (4-lane, GEN2) 

- Memory 

• QDR2 II+ Controller 

• DDR3 Controller 

• Xilinx Kintex-7 FPGA (FFG676) : 

- 7K410T-3,-2,-2L (fastest to slowest) 

- 7K325T-3,-2,-2L 

- 3M ASIC gates (ASIC measure) when stuffed with Kintex-7 7K410T 

• 254k flip-flop/6-input LUTs (708k total FFs) 

• 3.578 Kbytes total FPGA block memory (1590, 18 kbit blocks) 

• 1540, 25x18 multipliers 

• Bulk memory: DDR3 VLP Mini-uDIMM 


- 666.5MHz operation, PC3-10600 (single rank) 

- Addressing/power to support 4GB 

- DDR3 interface compatible with Vivado MIG 

• Optimized DDR3 controller for lowest latency bulk memory access 

- Optional RLDRAM Mini-UDIMM instead of DDR3 for ultra low latency 

• QDRII+ SRAM memory: 4M x 18 (72Mb) 

- Separate 18-bit read and write ports 

- 500 MHz bus operation, DDR (double data rate) 

• Fast enough to be clocked at 312.50 MHz 

• Eliminates clock synchronization delays between memory and Ethernet clock 

• SMBus-based thermal management 

• GPS input for precise message time stamping and tracking 


- ChipScope and other third-party debug solutions: 

• Tektronix Certus 

• Eight FPGA-controlled LEDs 

- Enough light to make your houseplants happy 

Kintex-7 


Speed Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

7K410T -1,-2,-3 6-input 508,400 4,881 2,930 500 1,540 1,590 28,620 3,578 

7K325T -1,-2,-3 6-input 407,600 3,913 2,350 500 840 890 16,020 2,003 

7K160T -1,-2,-3 6-input 202,800 1,947 1,170 400 600 650 11,700 1,463 

858 . 454 . 3419 19

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

LED 

(x4) 

Config PROM 

Frequency 

Synths (Si5326) 

Frequency 


Frequency 


COMPACT FLASH 


CONFIGURATION 

Stratix IV 

DN7020K10 

+1.5V to +3.3V I/O 

DC0 


Connector (400-pin) 

DIMM_F1 

DDR2 SODIMM 

(4GB max) 

DIMM_F2 

DDR2 SODIMM 

(4GB max) 

DIMM_F3 

DDR2 SODIMM 

(4GB max) 

+1.5V to +3.3V I/O 

DC2 



MICTOR 

Boot 

EPROM 

RS232 

serial 

port 

SMA 

SMA 

SMA 

SMA 

12 

12 

12 

62 24 61 

190 120 120 120 190 

SPI Flash 

SPI Flash 

SPI Flash 

(16Mb) 

(16Mb) 

(16Mb) 

Stratix IV 

50 Stratix IV 

51 Stratix IV 

50 Stratix IV 

50 Stratix IV 

FPGA F0 FPGA F1 FPGA F2 FPGA F3 FPGA F4 

50 

4SE820 

4SE820 

62 24 61 

62 24 61 

62 24 61 

184 

188 

186 

48 

48 

48 

48 

48 

48 

46 50 

44 51 

46 50 

46 

4SE820 

4SE820 

4SE820 

50 

51 

50 

50 

51 

50 

48 

48 

48 

48 

48 

48 

138 

140 

138 

48 

48 

48 

48 

48 

48 

48 

48 

Stratix IV 

Stratix IV 

Stratix IV 

Stratix IV 

Stratix IV 

38 

39 

38 

38 


38 

39 

38 

38 

4SE820 

4SE820 

4SE820 

4SE820 

4SE820 

38 

48 

48 

Stratix IV 

Stratix IV 

Stratix IV 

Stratix IV 

Stratix IV 

FPGA F10 

38 


39 


38 


37 


38 

39 

38 

36 

4SE820 

4SE820 

4SE820 

4SE820 

4SE820 

38 

48 

48 

Stratix IV 

50 Stratix IV 

50 


4SE820 

4SE820 

40 50 

40 40 46 

Stratix IV 

51 Stratix IV 

51 Stratix IV 

51 

51 

51 

51 4SE820 

51 4SE820 

51 4SE820 

SPI Flash 

(16Mb) 

38 

38 

50 

24 23 24 

24 23 24 

24 23 24 

24 23 24 

39 

39 

SPI Flash 

(16Mb) 

39 

39 

51 

24 23 24 

24 23 24 

24 23 24 

24 23 24 

138 

140 

138 

48 

48 

48 

48 

48 

48 

48 

48 

48 

38 

38 

48 

48 

48 

48 

48 

48 

SPI Flash 

(16Mb) 

38 

38 

51 

24 23 24 

24 23 24 

24 23 24 

24 23 24 

140 

140 

138 

48 

48 

48 

48 

48 

48 

50 

50 

38 

36 

50 

48 

48 

38 

48 

48 

37 

48 

48 

50 

21 21 21 

21 21 21 

21 21 21 

21 21 21 

MBUS48B 

180 

184 

180 

Bus 

Switch 

47 

47 

48 

48 

Bus 

Switch 

47 

47 

48 

48 

Bus 

Switch 

47 

47 

48 

48 

47 

47 

48 

48 

Bus 

Switch 

DC3 



DC4 



DC5 



DC6 



+1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O 

34 

Main Bus 

Connector 

SMA 

SMA 

F4 

40 

40 

MICTOR 

MBUS48A 

MBUS48B 

MBCLK 

GCLK0 

(to all FPGA’s) 

GCLK1 


GCLK2 


DCGCLK0 


CY7C68013 

uP Configuration 

controller 

SRAM 

128Kb x 8 

Flash 

1 M x 8 

Config 


48 MHz 

8 

LCD 

Control 

Panel 

USB 2.0 

(type b) 

RS232 

Reset 

96 

96 

SMA 

CFPGA Div Clk 

CFPGA Step Clk 


SMA 




SMA 




G0 Si5326 


4 Serial 

Ports 

(Tx/Rx) 



SMA 

PLL 

DC10 

SMA 

DC0 

DC3 

+1.5V to +3.3V I/O 

Features 

20 

JTAG 


0 

5 

1 

6 

2 

7 

10 11 12 13 14 

15 

16 

17 

3 

8 

18 

4 

9 

19 

190 120 120 48 

DC1 

DIMM F16 

DIMM F17 



+1.5V to +3.3V I/O 

• USB2.0-hosted logic prototyping system 

with 2-20 Altera Stratix IV FPGAs 

- Stratix IV 4SE530 or 4SE820 in high I/O 

package (FF1760) 

- Backwards compatible with the Stratix-3, 

3SL340 

- 100% FPGA resources available for user application 

• 130M+ ASIC gates (reasonable ASIC 

measure) with twenty 4SE820s 

- 82M+ with twenty 4SE530s 


- 600 MHz LVDS chip-to-chip DDR (1.2 Gb/s) 

- Reference designs for integrated I/O pad 

ISERDES/OSERDES 

• 10x FPGA to FPGA pin multiplexing 

per LVDS pair 



• Main Busses for global connectivity: 

- Main Bus A (MBUS48A), all FPGAs: 48 

single-ended signals 

- Main Bus B (MBUS48B), all FPGAs: 48 

single-ended signals 


- Hooks for other third-party partitioning solutions 

• 6 separate DDR2 SODIMMs (350MHz) 

- 64-bit data width, 350MHz operation 

- PC2-5300 

- Addressing/power to support 4GB in each 

socket 

- DDR2 Verilog/VHDL reference design 

provided (no charge) 

- DDR2 SODIMM data transfer rate: 32Gb/s 

- Alternate pin compatible memory cards 

available: 

• QDR SSRAM, Mictor, RLDRAM I, 

RLDRAM II, SSRAM, DDR3, DDR1, 

interconnect, SDRAM DRAM, 

FLASH, USB PHY, and others 

• SODIMM Daughtercard expansion 

- DNSODM200_Mictor - Mictor + 0.1” breakout 

- DNSODM200_Flash - two 4M x 32 flash chips 

DDR2 SODIMM 

(4GB max) 

DDR2 SODIMM 

(4GB max) 

= LVDS when paired, but can be used 

single-ended at reduced frequency 

120 190 

DIMM F18 

DDR2 SODIMM 

(4GB max) 

- DNSODM200_Quadmic - Mictors 

- More... 

• 3 board-level global clock networks (GCLK[2:0]) 

- Separate programmable synthesizers for 

each network (Si5326) 

• Ultra-low jitter 

• 2 kHz – 710 MHz 

• User configurable via Compact FLASH or USB 


• Config FPGA 

- single-step 

- Divide 


• 4 Daughter Card global clock networks 

(DC_GCLK[3:0]). Select from: 

- Clock from daughter card with PLL for 

zero-delay (ICS8745B-21) 

• DC_GCLK0: Select DC0 or DC3 as source 




- SMA for external clock insertion 

- Selected FPGA outputs 

• DC_GCLK0: Select GCLK0 or 

FPGA1 as source 





• DC_GCLK3: Select FPGA14 or 


• 8, 400-pin MEG-Array connectors (FCI) for 

daughter card (DC) expansion 

- 190 single-ended on DC0,1,2,7 

- 47 LVDS pairs (FPGA -> DC), 48 LVDS 

pairs (DC -> FPGA) on DC[6:3] 

• Can be used as 190 single ended signals 

- 600MHz on all signals with LVDS 

- Reset, presence detect 


• +12V (24W max) 

• +5V (10W max) 



+1.5V to +3.3V I/O 

DC7 

Bus 

Switch 

34 

F19 

DCGCLK1 


DCGCLK2 


DCGCLK3 


G1 Si5326 


G2 Si5326 




• +3.3V (10W max) 

- Pin multiplexing to/from daughter cards 

using ISERDES/OSERDES and LVDS 

(up to 10x) 


- Compact FLASH, and/or USB 


- Accelerated configuration readback 

• Custom base plate (standard) and optional 

rackmount chassis 

- Provides protection from those drooling 

engineers 

• 4, RS232 ports for embedded uP debug 

- Accessible from all FPGAs 

• Full support for embedded logic analyzers 

via JTAG interface 

- SignalTap, and other third party tools 

• Convert a pair of MEG-Array expansion 

connectors to interconnect with the 

DNMEG_Intercon. 

• MEG-Array Daughtercard Expansion 

- DNMEG_Obs - breakout/observation 

- DNMEG_Intercon - more interconnect 

- More... 

• Enough status LEDs to adequately illuminate 

a Twisted Sister concert. 

PLL 

SMA 

PLL 

SMA 

PLL 

DC2 

DC4 

DC5 

DC7 

DC1 

DC6

A 

B 

C 

D 

F 

A B C 

F 

E 

D 

F 

D 


LED’s 


LED’s 

18 

11 


LED’s 

FPGA E 

LED 

FPGA F 

LED’s 


LED’s 

DN7406K10PCIe-8T 

JTAG 

RJ45 

D 

+1.5V to +3.3V I/O 



+1.5V to +3.3V I/O 



+1.5V to +3.3V I/O 



RJ45 

F 

RS232 

2 

(bussed) 

ALL FPGAs 

10/100/1000 

ETHERNET 

(VSC8601) 

125 

MHz 

48 48 

47 47 

48 48 

47 47 

9 

48 48 

47 47 

125 

MHz 

125 MHz 

10/100/1000 

ETHERNET 

(VSC8601) 

Config 

USB 2.0 

(480 Mb/s) 

RS232 

Reset 

COMPACT 

FLASH 

config 


Configuration 


uP Config 

Control 

clock config 

Ethernet 

JTAG 

16 

MB [35:0] 

config data 

DDR2 SODIMM 

(4GB Max) 

QL5064 

122 

+2.5V 

I/O 

mac addr 

Flash 

(24C64) 

36 

8 

User 

Serial Flash 

(16 Mbit) 

1 

17 

2 

5 


Stratix 4 

4SE820 

(FF1760) 

62 62 

62 62 

46 

2 

clock input 

14 

9 

9 

184 

9 

9 

48 48 

48 

48 

x14 


Stratix 4 

4SE820 

(FF1760) 

MB [95:0] 

96 

9 

clock input 

1 

9 

9 

clock input 

186 

9 

9 

9 

9 


Stratix 4 

4SE820 

(FF1760) 

62 62 

62 62 

62 62 62 62 

46 

1 

2 

5 

14 

17 

mac addr 

Flash 

(24C64) 

8 

User 

Serial Flash 

(16 Mbit) 

x14 

122 

+2.5V 

I/O 

Main Bus 

Connector 

DDR2 SODIMM 

(4GB Max) 

114.285MHz 


clock 

sourcing 

clk_TP 

single step clock 

(from config 

FPGA) 

clk_G0 

from config FPGA 

48 MHz 

24 

MHz 

24 

MHz 

24 

MHz 

Clock Synth 

Si5326 

2Khz to 600MHz 

114.285MHz 

Clock Synth 

Si5326 


114.285MHz 

Clock Synth 

Si5326 


MB clock 

clk_G0 

(General 

clocking) 

clk_G1 

(DDR2) 

clk_G2 

(LVDS) 

clk_MB48 

DDR2 SODIMM 

(4GB Max) 

QL5064 

122 

89 89 

PCIe Express 

Endpoint 


Stratix 4 

4SE820 

(FF1760) 

(250 MHz) 

clock input 

184 

9 

9 

9 

9 

3 

User 

Serial Flash 

(16 Mbit) 

x3 

5 

1 


Stratix 4 

4SE820 

(FF1760) 

MICTOR 

clock input 

184 

x11 

clock input 

45 

User 

Serial Flash 

(16 Mbit) 

45 

45 

45 

21 

1 

21 

5 

21 

21 


Stratix 4 

4SE820 

(FF1760) 

11 

x11 

34 

122 

MICTOR 

DDR2 SODIMM 

(4GB Max) 

Daughter card D 

clk_EXT0 

sma 

Daughter card F 

Daughter card E 

clk_EXT1 

PCI Express 

8 - lane 

GEN1 - 2.5 Gb/s (8-lanes) 

GEN2 - 5.0 Gb/s (4-lanes) 



Features 

PCIe endpoint 

clk_ref 

Global Clocks to all FPGA’s 

• PCI Express (8-lane) logic prototyping system with 2-6 

Altera Stratix-4 FPGAs 

- EP4SE820-3, -2 (slowest to fastest) 

- EP4SE530-3, -2 

• FF1760 package: 1,120 I/Os (with 4SE820) 

• Fixed 8-lane PCIe interface and controller provided 

- PCIe GEN1 rev 1.1 

- PCIe GEN2 with upgrade 

• 40+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix-4 4SE820s 

• FPGA to FPGA interconnect is a mix of single-ended and LVDS 

- 600 MHz LVDS chip to chip (1.2 Gb/s) 

- LVDS pairs can be used as two single-ended signals at 

reduced frequency (~225MHz) 

- Reference designs for integrated I/O pad ISERDES/OSERDES 

- 10x pin multiplexing per LVDS pair 

- Greatly simplified logic partitioning 

- Source synchronous clocking for LVDS 

• Main Bus (MB) connects all Stratix-4 FPGAs (96 signals) 

- Single-ended 

• Auspy models for partitioning assistance 


- Direct connection to FPGAs A, C, F, D 

- PC2-4200 or better 

- Addressing/power to support 4GB in each socket 



- Alternate pin compatible memory cards available 

(consult factory for availability): 

• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH 



• Seven independent low-skew global clock networks 

- G0, G1, G2, M48, EXT0, EXT1, REF 

- Three, high-resolution, user-programmable synthesizers for G0, G1, G2 

- User configurable via CompactFLASH, USB, and/or PCIe 

- All seven global clocks networks distributed differentially and balanced 

• Two independent single-step clocks 

- Seven independent external clocks inputs (single-ended 

or differential) can be injected onto low-skew global clock networks 

Stratix IV 


Speed 

Grades 

(slowest to 

fastest) 

LUT 

Size 

FF's 

Gate Estimate 

Max 

(100% util) 

(1000's) 

Practical 

(60% util) 

(1000's) 

• Flexible customization via daughter cards using expansion connectors 

- 3 daughter card locations: FPGAs D, E, F 

- 400-pin FCI MEG-Array connectors 

- 93 LVDS unidirectional pairs + clocks (or 186 single-ended) 

- 450MHz on all signals with source synchronous LVDS 

- Signal voltage set by daughter card (1.2v to 3.3V) 

- Reset 


• +12v (24W max) 

• +5V (10W max) 

• +3.3V (10W max) 

- Pin multiplexing to/from daughter cards using LVDS (up to 10x) 


- CompactFLASH, USB, PCIe, JTAG 



• RS232 port for embedded uP debug 



- SignalTap, and other third-party debug solutions 

• 54 status FPGA-controller LEDs: bright enough to 

illuminate airplane landing strips 

Max I/O's 

MLAB 

(640) 

M9K 

(9 kbit) 

M144K 

(144 kbit) 

Total 

(kbits) 

Total 

(kbytes) 

4SE820 -4,-3 6-input 656,000 10,496 6,508 1120 960 16261 1610 60 23,130 2,891 

4SE530 -4,-3,-2 6-input 424,960 6,799 4,080 960 1024 10624 1280 64 20,736 2,592 

Multipliers 

(18x18) 

Memory 

858 . 454 . 3419 21

Stratix IV 

DN7002K10MEG 

COMPACT FLASH 


CONFIGURATION 

Config 

2 

Config 


36 

Main Bus (MB) 

Main Bus 

Connector 

RS232 

SSRAM 

FLASH 

72 

USB 2.0 

(type b) 

2 

uP 

Config 

Controller 

DDR2 SODIMM 

(4GB max) 

DDR2 SODIMM 

(4GB max) 

from FPGA A 

from FPGA B 

osc 

24 

MHz 

CLK_G2 

osc 

24 

MHz 

TP 


osc 

24 

MHz 

Clock from 

daughter card A0 

48 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

ClockGen 

(Mult/Div) 

0-delay PLL 

CLK_G0 

48 MHz 

(MB Clock) 

CLK_G1 

(2KHz to 945 MHz) 

CLK_G2 

CLK_DC_A0 

A0 



23 23 24 24 

90 

94 

24 24 23 23 



122 

Stratix IV 


A 

4SE820 



AB 

AB6BUS 

LED 

(x8) 

BA 

182 182 

62 

62 

62 

62 

38 

Stratix IV 


B 

4SE820 



B0 



23 23 24 24 

A1 A2 B2 B1 

LED 

(x8) 

122 

24 24 23 23 

92 

94 



SMA 

Clock from 

daughter card B0 

ClockGen 

(Mult/Div) 

0-delay PLL 

CLK_DC_B0 

JTAG 

A 

B 



SMA 

CLK_DC_A2 

CLK_DC_B1 

ClockGen 

(Mult/Div) 

0-delay PLL 

CLK_DC_A2 

RS232 

2 

FPGAs 

CLK_DC_B2 

CLK_DC_A1 

Features 

22 

ClockGen 

(Mult/Div) 

0-delay PLL 


CLK_DC_B2 

• USB2.0-hosted logic prototyping system with 

1-2 Altera Stratix 4 FPGAs 

- Stratix IV 4SE530 or 4SE820 in high I/O package (FF1760) 

• -30A VCCINT power per FPGA 

• 13M+ ASIC gates (LSI measure) with two Stratix IV 4SE820 


- 600 MHz LVDS DDR chip-to-chip (1.2 Gb/s) 

• Characterized and tested 

- Reference designs for integrated I/O pad shift registers 

• 10x FPGA to FPGA pin multiplexing per LVDS pair 



• 72-bit main busses for global connectivity: 


- Hooks for other third-party partitioning solutions 


- 64-bit data width, 350MHz operation 

- PC2-5300 

- Addressing/power to support 4GB in each socket 



- Alternate pin compatible memory cards available: 

• QDR SSRAM, Mictor, RLDRAM I, 

RLDRAM II, SSRAM, DDR3, DDR1, 

IDC interconnect, SDRAM DRAM, 

FLASH, USB PHY, mobile SDRAM, & others 

• 3 low-skew global clock networks (GCLK[2:0]) 

- Matched length and differentially distributed to each FPGA 

- Separate programmable synthesizers for each network (Si5326) 

• Ultra-low jitter (as low as 0.3 ps) 

• 2 kHz – 710 MHz 

• User configurable via Compact FLASH or USB 


• Configuration FPGA for generation of single-step or divided clock 


• 4 Daughter Card global clock networks (DC_GCLK[3:0]) 

• 6, 400-pin MEG-Array connectors (FCI) for Daughter Card (DC) expansion 

- 1,116 total single-ended signals for daughter card expansion 

• 47/46 LVDS pairs (FPGA -> DC), 46/47 LVDS pairs (DC -> FPGA) 

• Can be used as 186 single-ended signals per connector 

• 600MHz (1.2Gb/s) 

• Pin multiplexing to/from daughter cards using I/O shift registers (up to 10x) 


• +12V (24W max) 

• +5V (10W max) 

• +3.3V (10W max) 


- Compact FLASH, USB, and/or JTAG 



• RS232 port for embedded uP debug 

- Accessible from both FPGAs 



- SignalTap and other third party tools 

• Convert a pair of MEG-Array expansion 

connectors to interconnect with the 

DNMEG_Intercon. 

• Enough status LEDs to adequately direct traffic.

Alternate Memory: 200-pin SODIMM 

SODIMM OPTIONS 

DNSODM200_RLDRAM-II SODIMM 

The DNSODM200_RLDRAM-II is a 

SODIMM module that can be installed in 

a 200-pin DDR2 SODIMM socket. This 

module contains two RLDRAM II chips 

in a 32M x 36-bit configuration for a total 

of 144 megabytes. 

DNSODM200_DDR3 SODIMM 

The DNSODM200_DDR3 is a SODIMM. 

Provides 512MB of DRAM memory 

(DDR3 interface arranged as x64). 

DNSODM200_SSRAM SODIMM 

The DNSODM200_SSRAM is an 



module contains two SSRAM chips in a 

2M x 64 configuration for a total of 16 

megabytes. 

DNSODM200_SSRAMx4 SODIMM 

The DNSODM200_SSRAMx4 is a 



module contains four SSRAMs chips in a 

8M x 18 configuration. 

DNSODM200_INTERCON SODIMM 

The DNSODM200_INTERCON is a 

SODIMM compatible with all “DDR2” 

SODIMM slots on Dini Group products. 

This module provides up to 122 signals 

on 2mm headers for access. The signals 

can be used single-ended or differential. 

Termination resistors are provided to allow 

the use of standard IDC cabling 

DNSODM200_FLASH SODIMM 

The DNSODM200_FLASH is an 

SODIMM that can be installed in a 200- 

pin DDR2 SODIMM socket. This module 

contains two flash chips in a 4M x 32 configuration 

for a total of 16 megabytes. 

DNSODM200_MICTOR SODIMM 

The DNSODM200_MICTOR is a 



module contains two Mictor connectors 

and three, 12-pin IDC-type headers. Logic 

analyzers from Tektronix and Agilent can 

be directly connected to FPGA pins enabling 

direct high-speed observation. 

DNSODM200_QUADMIC SODIMM 

The DNSODM200_QUADMIC is a 


a 200-pin “DDR2” SODIMM socket. This 

module contains four Mictor connectors. 

Logic analyzers from Tektronix and Agilent 

can be directly connected to FPGA 

pins enabling direct high-speed observation. 

DNSODM200_RLDRAM SODIMM 

The DNSODM200_RLDRAM is a 



module contains two RLDRAM chips in 

an 8M x 64-bit configuration for a total of 

64 megabytes. 

DNSODM200_USB SODIMM 

The DNSODM200_USB is a SODIMM. 

Provides a USB OTG physical interface 

(Standard ULPI). Also provides PCB audio, 

DIP switches, LEDs, SD card, 512k 

serial non-volatile memory. 

DNSODM200_DDR1 SODIMM 

The DNSODM200_DDR is a DDR2-to- 

PC2700 adapter card compatible with 

Dini Group products with DDR2 memory 

sockets. It allows a standard PC2700 

SODIMM (up to 512MB) to connect to 

the SODIMM slot of your Dini Group 

Emulation board.tt 

DNSODM200_SDR SODIMM 

The DNSODM200_SDR is a DDR2-to- 

PC100 adapter card compatible with Dini 

Group products with DDR2 sockets. It 

allows a standard PC133 SODIMM (up 

to 512MB of Single-Data rate memory) 

to connect to the DDR2 slot of your Dini 

Group Emulation board. 

DNSODM200_SE SODIMM 

The DNSODM200_SE is a SODIMM module 

compatible with all 200-pin DIMM 

slots on Dini Group products. The module 

contains one 256Mb flash and two Micron 

32Mb SDRAM chips. An EPROM socket 

can hold a serial prom with densities up to 

512Kb. The DNSODM200_SE is compatible 

with all Dini Group products equipped 

with DDR2-SODIMM sockets. 

DNSODM200_QDR SODIMM 

The DNSODM204_QDR II+ is a 

SODIMM that can be installed in a 204- 

pin DDR3 SODIMM socket. 

858 . 454 . 3419 23

116 

116 

A 

G 

B 

F 

38 

C 

E 

38 39 

D 

39 38 

40 

40 

40 

40 

40 

40 

40 

38 59 

59 

FPU 

FPU 

4 4 

1 

4 

4 

4 

4 

4 

4 

iPASS Cable (3’-18’) 

4 

Host Computer 

PCIe Slot (8-lane) 

Virtex - 6 

DN2076K10 

18 

18 

MEG Array Expansion MEG Array Expansion 



96 

96 

96 

96 


A 

Virtex-6 

LX550T / LX760 

38 

38 

117 

117 

DDR3 SODIMM 

(4GB Max) 

130 


B 

Virtex-6 

LX550T / LX760 

SPI 

Flash 

137 

137 

IDC Connector 

16 


C 

Virtex-6 

LX550T / LX760 

96 96 

117 

117 

DDR3 SODIMM 

(4GB Max) 

130 


G 

Virtex-6 

LX240T/LX365T 

SX315T 

(FF1759) 

SX475T/LX550T 

GTX Expansion 

Header 

10GbE 

to 

XAUI 

QT2225 

10GbE 

to 

XAUI 

QT2225 

SFP+ Socket 

SFP+ Socket 

SFP+ Socket 

SFP+ Socket 

USB 3.0/2.0 

10GbE 

Ethernet 

10GbE 

Ethernet 



96 

96 


D 

Virtex-6 

LX550T / LX760 

157 

157 

117 117 

168 168 


E 

Virtex-6 

LX550T / LX760 

160 

160 


F 

Virtex-6 

LX550T / LX760 

MAIN BUS [51:0] 

SEARAY 

RGMII 10/100/1000 

Phy 

RJ45 

SFP 

10/100/1000 

base - T 

sma 

1 2 3 

0 

SMA 



FPGA G 





USER_T 

USER_R 

130 

DDR3 SODIMM 

(4GB Max) 

JTAG 

37 

37 

NMB 







FPGA G 


Virtex-6 

(FF1156) 

SPI 

Flash 

4 

52 

PCI Express 

Cable 

(GEN 2) 

PCIe (GEN1 / GEN2) 

PCIe Cable Adapter 

Board 

Features 



24 

MHz 

24 

MHz 

24 

MHz 




CLK_25 

(25 MHz) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

USER_L 

G0 

(2KHz 

to 700 MHz) 

G1 

(2KHz 

to700 MHz) 

G2 

(2KHz 

to 700 MHz) 

10/100/1000 

baseT 

RJ45 

USB 

2.0 

(3x) 

RS232 

10/100/1000 

Phy 

SATA II 

(host) 

2x 

RGMII 

OSC 

USB 

DMA(4x) 

SATA 

RTC 

MPP Bus 

PCIe 

PCIe 

(Gen1) 

4 - lanes 


4-lanes 

PCIe (GEN1) 

PCI Express Cable 

(GEN 1) 

- 4-lane GEN1 PCIe (v1.1) slot 

- USB2.0 


- Stand alone 

• Up to seven of the largest Xilinx Virtex-6 FPGAs 

- Six Xilinx Virtex-6 FPGAs (FF1760) from the following list: 

• LX760-2,-1,-1L(fastest to slowest), LX550T-2,-1,-1L 

- One Xilinx Virtex-6T FPGA (FF1759) from the following list: 

• LX550T-2,-1,-1L, SX475T-2,-1,-1L,SX315T-3,-2,-1,-1L 

• LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L 

- 50A VCCINT power per FPGA 


stuffed with 6 Virtex-6 LX760 and 1 LX550T 

• 24, GTX low-powered transceivers: 

- 65 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1 

- Dual AMCC QT2225-2 Dual Port Serial 10Gbps-to-XAUI Transceivers 

• Four SFP+ sockets for any of the following interfaces: 

- 10 Gigabit Optical Ethernet 

• 10GBase-SR 10GBASE-LR 10 GBASE-LRM 10GBASE-ER 

• 10 Gigabit Copper Ethernet: 10GBASE-R direct attach 

- 10 Gigabit Sonet: 10GBase-LW 

- 10 Gigabit FibreChannel 

- SFP socket 

- 4 channels using SMA connectors 

- 16 SMAs in total 

- 4-lane PCIe GEN1/GEN2 prototyping via iPASS cable 

- 2 SATA II ports: 1 host and 1 device 

CPU CPU 

64 

3 

8 

Third Party 

debug 

connector 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

(host) 

SATA II 

(device) 



- GTX Expansion header with LX550T/SX475T (SEARAY connector) 

- 8-lanes 

• FPGA to FPGA interconnect is LVDS 

- 1.3 Gb/s when using DDR with -2 speed grade 

• 1.0 Gb/s with -1 speed grade 

- LVDS pairs are length balanced and tested 

- LVDS pairs can be used as two single-ended 

signals at reduced frequency (~225MHz) 


- 10x pin multiplexing per LVDS pair, greatly simplified logic partitioning 


• 52-pin Main Bus (MB[51:0]) connects all LX FPGAs 

• Auspy board interconnect models for logic partitioning assistance 

• Marvell MV78200 Discovery Innovation Dual CPU 

- 1 GHz clock 


- Dual Serial-ATA II connectors (SATA II) 







- After configuration, both CPUs dedicated 

entirely to user application 

- LINUX operating system 

• Source and examples provided via GPL 

license (no charge) 


Virtex-6 

LX 

LXT 

SXT 


Speed 

Grades 

(slowest 

to fastest) 

LUT 

Size 

FF's 

Gate 

Max 

(100% u 

(1000's 

LX760 -1,-2 6-input 948,480 9,105 

LX550(T) -1,-2 6-input 687,360 6,599 

LX365T -1,-2,-3 6-input 455,040 4,368 

LX240T -1,-2,-3 6-input 301,440 2,894 

LX195T -1,-2,-3 6-input 249,600 2,396 

LX130T -1,-2,-3 6-input 160,000 1,536 

SX475T -1,-2 6-input 595,200 5,714 

SX315T -1,-2 6-input 394,000 3,782 

24 

www.dinigroup.com

DNV6F2PCIe 

JTAG 

A 

DDR3 SODIMM 

(4GB Max) 

DDR3 SODIMM 

(4GB Max) 

130 

130 



CONFIG FPGA 

SMA 




SMA 


24 

MHz 

24 

MHz 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

G0 

(2KHz 

to 700 MHz) 

G1 

(2KHz 

to 700 MHz) 

G2 

(2KHz 

to 700 MHz) 

B 

SFP 

SATA II 

(device) 

SATA II 

(host) 

Cabled 

PCIe 

(4-lane) 

iPASS 

Virtex-6 


4 

Device Bus 

PCIe 

PCIe 

(Gen1) 

4 - lanes 

60 

60 

NMB A 

NMB B 

OSC 

40 


A 

Virtex-6 

LX760 / LX550T 

(FFG1760) 

94 94 



AB 

40 40 

LEDs (8) 

322 

322 


B 

Virtex-6 

LX760 / LX550T 

(FFG1760) 

94 94 



35 

LEDs (8) 

MICTOR 

125 MHz 

150 MHz 

OSC 

250 MHz 

312.5 MHz 

125 MHz 

150 MHz 

OSC 

250 MHz 

312.5 MHz 

SFP 

Clock 

SATA 

Clock 

10/100/1000 10/100/1000 

Phy 

baseT 

RJ45 

RS232 

USB 2.0 

(2X) 

SATA II 

(host) 

2x 

RGMII 

USB 

DMA(4x) 

SATA 


RTC 

PCIe 

PCI EXPRESS 

FPU 

CPU CPU 

4-lanes 

PCIe (GEN1) 

FPU 

64 

3 

8 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

Battery 

Encryption 

Key Voltage 

= LVDS when paired, 

but can be used 

single-ended at a 

reduced frequency 

Features 


- 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T Ethernet 

- Stand alone 

• 2 Xilinx Virtex-6 FPGAs (FF1760) from the following list: 

- LX760-2,-1,-1L, LX550T-2,-1,-1L (fastest to slowest) 


• 11+ million ASIC gates (ASIC measure) when stuffed with 2 Virtex-6 LX760s 

• FPGA to FPGA interconnect is LVDS and GTX Rocket I/O 

- 1.3 Gb/s when using DDR with -2 speed grade 

• 1.0 Gb/s with -1 speed grade 


- 10x pin multiplexing per LVDS pair 

- Greatly simplified logic partitioning 


• Bus connecting Config FPGA with each field FPGA 

- 40 signals, single-ended (NMB[A:B]) 

• RocketIO GTX Transceivers (Configuration FPGA) 

- PCI Express Cable (x4), SATA – Host (x1), SATA – Device (x1), SFP (x1) 

• Auspy board interconnect models for logic partitioning assistance 

• 2 separate DDR3 SODIMMs, one for each FPGA (AB) 

- 533MHz, 1066 MB/s, PC3-8500 or better 

- 64-bit, with addressing/power to support 4GB in each socket 




available (consult factory for availability): 

• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH 



• Three independent low-skew global clock networks 

- G0, G1, G2 



- User configurable via Marvell uP RS232, 

USB, PCIe, or Ethernet 

- Global clocks networks distributed differentially and balanced 

• Flexible customization via daughter cards using two expansion connectors 

- 400-pin FCI MEG-Array connector 

• Non proprietary, readily available, and cheap 


- 650 MHz on all signals with source 

synchronous LVDS (with -2 speed grade) 

- Signal voltage set by daughter card (+1.2v to +2.5V) 

- Reset 


• +12v (24W max), +3.3V (10W max) 



- USB, PCIe, Ethernet, JTAG 

- Stand-alone configuration with USB stick or on-board NAND FLASH 






- ChipScope and other third-party debug solutions 


- Enough illumination to sterilize refrigerator door handles. 

til) 

) 

Estimate 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

5,509 1,200 864 1,440 25,920 3,240 

3,959 1,200 864 1,264 22,752 2,844 

2,621 600 576 832 14,976 1,872 

1,736 600 768 832 14,976 1,872 

1,438 600 640 688 12,384 1,548 

922 600 480 528 9,504 1,188 

3,428 600 2,016 2,128 38,304 4,788 

2,269 600 1,344 1,408 25,344 3,168 

858 . 454 . 3419 25

40 

40 

40 

40 

40 

40 

Virtex - 6 

DNV6F6PCIe 

Features 



10/100/1000 

baseT 

RJ45 

USB 2.0 

(3x) 

24 

MHz 

125 MHz 

150 MHz 

OSC 

250 MHz 

312.5 MHz 

G0 

- 4-lane GEN1 PCIe (v1.1) slot, USB2.0, 10/100/1000BASE-T 

Ethernet, or Stand alone 

• Six Xilinx Virtex-6 FPGAs (FF1759) from the 

following list: 

- LX550T-2,-1,-1L, SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L 

- LX365T-3,-2,-1,-1L, LX240T-3,-2,-1,-1L 


• 24+ million ASIC gates (ASIC measure) when stuffed with 6 

Virtex-6 LX550T 

• 21+ million ASIC gates and 12,096, 25x18 multipliers with 6 

Virtex-6 SX475T 

• FPGA to FPGA interconnect is LVDS and GTX RocketI/O 

- 710 MHz LVDS chip to chip with -3 speed 

grade (1.4Gb/s with DDR) 

• 650MHz with -2 (1.3 Gb/s with DDR), 500MHz with -1 (1.0 Gb/s 

with DDR) 

- Pairs are length balanced and tested! 

- LVDS pairs can be used as two single-ended signals at reduced 

frequency (~225MHz) 

• Reference designs for integrated I/O pad ISERDES/OSERDES 

• 10x pin multiplexing per LVDS pair. Source synchronous clock 

ing for LVDS 

- GTX Transceivers FPGA to FPGA 

• 6.5 Gb/s with -3, -2 speed grade and 5.0 Gb/s with -1/-1L 

• Data examples provided using Aurora protocol 

• Bus connecting Config FPGA with each field FPGA 

- 40 signals, single-ended (NMB[F..A]) 

- Full PCI Express throughput to user design 

• Auspy board description models for logic partitioning assistance 

• 4 separate DDR3 SODIMMs, one for each corner Virtex-6 FPGA (ACFD) 

- 533MHz, 1066 MB/s with -2 and -3 speed grades (PC3-8500) 

• 400MHz, 800 Mb/s with -1 speed grade (PC3-6400) 




- Alternate pin compatible memory cards available (consult factory 

for availability): 

• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH DRAM: SDR, 

DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra 

Interconnect 

SMA 

24 

MHz 

24 

MHz 

RS232 

SATA II 

(host) 

2x 







10/100/1000 

Phy 

CLK_25 

(25 MHz) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

RGMII 

USB 

USER_R 

USER_L 

G0 

(2KHz 

to 700 MHz) 

G1 

(2KHz 

to700 MHz) 

G2 

(2KHz 

to 700 MHz) 

MGT Clock 

DMA(4x) 

SATA 

RTC 

FPGA Q 

Virtex-5 


MPP Bus 

PCIe 

PCIe 

(Gen1) 

4 - lanes 


PCIe 

PCI EXPRESS 

FPU FPU 

CPU CPU 

4-lanes 

PCIe (GEN1) 

SFP 

or 

SFP+ 

SATA II 

(device) 

(host) 

NMB 

OSC 

64 

3 

8 

10/100/1000 

Phy 

DDR3 SODIMM 

(4GB Max) 

DDR3 SODIMM 

(4GB Max) 

128M x 64 

DDR2 

128Mb 

SPI 

Boot FLASH 

256Mb 

NAND FLASH 

Boot 

GTX 

1 

130 

130 



40 

96 96 


F 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

40 74` 74 


C 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

8 

GTX 

GTX 

8 

GTX Expansion 

Header 

GTX 

12 

128Mb 

Flash 

4 

4 

58 

58 

20 

20 

4 

4 

120 

120 

20 

20 

40 

40 

GTX 

GTX 

GTX 

GTX 



96 96 


E 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

95 

95 


B 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

128Mb 

FLASH 

GTX 

16 

128Mb 

Flash 

4 

4 

60 

60 

40 

40 

4 

4 

100 

100 

40 

40 

GTX 

GTX 

GTX 

GTX 



GTX--> Packet I/O Transceivers 

6.5 Gb/s per channel 

bidirectional (13 Gb/s max) 



96 96 


D 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

20 20 73 73 


A 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

8 

GTX 

GTX 

GTX Expansion 

Header 

• Three independent low-skew global clock networks: G0, G1, G2 



- User configurable via Marvell uP RS232, USB, PCIe, or Ethernet 


• Add 8 SFP sockets to GTX Expansion Header with DNSEAM_SFP 

• Flexible customization via daughter cards using expansion connector 

- Daughter card location on FPGA D,E,F 

• 400-pin FCI MEG-Array connector - Non proprietary, readily 

available, and cheap 


- 710 MHz (1/4 Gb/s) on all signals with source 

synchronous LVDS (assuming -3 speed grade) 


- Supplied power rails (fused): +12v (24W max), +3.3V (10W max) 


• High Speed expansion via GTX connector 

- Connector for each FPGA A, C, F, 8 GTX lanes per connector 

- 6.5 Gb/s per lane, each direction (with -3) 

• 5.- Gb/s with -1 and 01L speed grade 

• Fast and Painless FPGA configuration via USB, PCIe, Ethernet, JTAG 

• Stand-alone configuration with USB stick or on-board NAND FLASH 








- Enough illumination to act as automobile fog lights 

Virtex-6 

LX 

LXT 

SXT 


Speed 

Grades 

(slowest 

to fastest) 

4 

8 

GTX 

12 

GTX 

130 

130 

GTX Expansion 

Header 

DDR3 SODIMM 

(4GB Max) 

DDR3 SODIMM 

(4GB Max) 

128Mb 

Flash 

LUT 

Size 

FF's 

Gate 

Max 

(100% u 

(1000's 

LX760 -1,-2 6-input 948,480 9,105 

LX550(T) -1,-2 6-input 687,360 6,599 

LX365T -1,-2,-3 6-input 455,040 4,368 

LX240T -1,-2,-3 6-input 301,440 2,894 

LX195T -1,-2,-3 6-input 249,600 2,396 

LX130T -1,-2,-3 6-input 160,000 1,536 

SX475T -1,-2 6-input 595,200 5,714 

SX315T -1,-2 6-input 394,000 3,782 

26 

www.dinigroup.com

DN-DualV6-PCIe-4 

from FPGA A 

from FPGA B 

TP 

osc 

24 

MHz 

CLK_G0 

osc 

24 

MHz 


osc 

24 

MHz 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

CLK_G0 

CLK_G1 

(2KHz to 945 MHz) 

CLK_G2 

(iDELAY) 

SPI 


Virtex-5T 

LX50T 


100 

100 20 

QA 20 

2 GTX 

DDR3 SODIMM 

(4GB max) 

122 


Virtex-6 

SX475T / SX315T 

LX365T / LX240T 

LX195T / LX130T 

(FF1156) 

AB 

GTX (6.5 Gb/s) 

1 

1 

79 

79 

4 

DDR3 SODIMM 

(4GB max) 

122 


Virtex-6 

SX475T / SX315T 

LX365T / LX240T 

LX195T / LX130T 

(FF1156) 

99 

99 



RS232 

(device) 

PCIe 

LEDs 

(x8) 

(host) 

A 

JTAG 

SATA II 

B 

QB 

20 

OSC 

PCIe 

20 

JTAG Q 

(4-lanes) 

GTX 2 

MPP Bus 

1 1 

LEDs 

(x8) 

(device) 

(host) 

SATA II 

10/100/1000 

baseT 

RJ45 

USB 2.0 

(2x) 

RS232 

10/100/1000 

Phy 

RGMII 

USB 

DMA(4x) 

SATA 


PCIe 

FPU FPU 

CPU CPU 

64 

3 

128M x 64 

DDR2 

SPI 

Boot FLASH 



RTC 

4-lanes 

PCIe (GEN1) 

8 

NAND FLASH 

Boot 

PCI EXPRESS 

Features 

• Hosted in a 4-lane GEN1 PCIe (v1.1) slot, USB 2.0, 10/100/1000 

baseT Ethernet, stand alone 

• 1-2 Xilinx Virtex-6 FPGAs from the following list: 

- SX475T-2,-1,-1L, SX315T-3,-2,-1,-1L, LX365T-3,-2,-1,-1L 

- LX240T-3,-2,-1,-1L, LX195T-3,-2,-1,-1L, LX130T-3,-2,-1,-1L 

- 50A VCCINT power shared between both FPGAs 

• FF1156 package with 600 I/Os, all utilized 


stuffed with 2 Virtex-6 SX475T 

- 2016, 25 x 18 multipliers (with accumulator) per SX475 

• FPGA to FPGA interconnect is LVDS 

- 710 MHz LVDS chip to chip with -3 speed grade (1.4 Gb/s with DDR) 

• 650 MHz with -2 (1.3 Gb/s with DDR), 500 MHz with -1 (1.0 

Gb/s with DDR) 

- Pairs are length balanced and tested! 

- LVDS pairs can be used as two single-ended 

signals at reduced frequency (~225MHz) 


- 10x pin multiplexing per LVDS pair. Source synchronous clocking for LVDS 

• RocketI/O GTX Transceivers 

- 6.5 Gb/s (with -3, -2 speed grade), 5.0 Gb/s with -1 

- 4-lanes connected between FPGA A and FPGA B 

- 2 lanes connected from Config FPGA Q to FPGA A 

- 2 lanes connected from Config FPGA Q to FPGA B 

- Data examples provided using Aurora protocol 

• Auspy models for logic partitioning assistance 

• 2 separate DDR3 SODIMMs, one for each 

Virtex-6 FPGA (AB) 

- 533MHz, 1066 MB/s, PC3-8500 or better 





available (consult factory for availability): 

• SRAM: QDR, ASYNC, STD, or PSRAM, FLASH, DRAM: SDR, 

DDR1, PSRAM or RLDRAM, DDR2, Mictor, USB PHY, Extra 

Interconnect 

• Seven independent low-skew global clock networks: G0, G1, G2 

- High-resolution, user-programmable synthesizers for G0, G1, G2 


- User configurable via Marvell uP RS232, USB, PCIe, or Ethernet 


• Single-step clock 

- External clock input can be injected onto low-skew global clock networks 

- single-ended or differential 

• Flexible customization via daughter cards using expansion connector 

- Daughter card location on FPGA B 

- 400-pin FCI MEG-Array connector 

• Non proprietary, readily available, and cheap 

- 93 LVDS unidirectional pairs + clocks (or 186 single-ended) 

- 710 MHz on all signals with source synchronous LVDS(with -3 speed grade) 


• Supplied power rails (fused): +12v (24W max) and +3.3V (10W max) 



- USB, PCIe, Ethernet, JTAG. Stand-alone configuration with USB stick 


- Accelerated configuration readback for 

advanced debug 






- Bright enough to see from a low-space orbit, but won’t blind airline pilots. 

til) 

) 

Estimate 

Practical 

(60% util) 

(1000's) 

Max I/O's 

Multipliers 

(25x18) 

Blocks 

(18kbits) 

Memory 

Total 

(kbits) 

Total 

(kbytes) 

5,509 1,200 864 1,440 25,920 3,240 

3,959 1,200 864 1,264 22,752 2,844 

2,621 600 576 832 14,976 1,872 

1,736 600 768 832 14,976 1,872 

1,438 600 640 688 12,384 1,548 

922 600 480 528 9,504 1,188 

3,428 600 2,016 2,128 38,304 4,788 

2,269 600 1,344 1,408 25,344 3,168 

858 . 454 . 3419 27

Bottom 

Virtex - 6 

DNMEG_V6HXT 

4x 10 GbE 

or 

1x 40 GbE 

QSFP 

(40G) 

QSFP 

(40G) 

4 

4 

GTH 

GTH 

CPLD 

(SFP Control 

Signals) 

10 GbE 

to 6 GbE 

10/100/1000 

GbE 

100 GbE / 

40 GbE 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

SFP+ 

CFP 

(40G / 100G) 

4 

8 

SATA II 

Device 

Host 

Device 

Host 

sma 

GTH 

GTX 

GTX 

GTX 

GTH 10 

GTH 

DDR3 UDIMM 

(16 GB Max) 

LED 

(4) 

72-bit Data 

Virtex-6 HXT 


HT380T / 565T 

(FF1923) 

2 

8 

GTX 

150 

4 

GTX 

GTX 

110 

110 

GTX 

96 

96 

10 

FMC 

(Vita 57) 

Top 



JTAG 

2 

2 

FMC 

RS232 

(x2) 

SMA 

28 

SPI Flash 

SPI Flash 

Debug 

(JTAG) 

Control 

2 

Config 

MCU 

LPC1754 

25 MHz 

Quad 

Clock 

Synthe 

-sizer 

Si5338 


0 

1 

CLK_CFP 

CLK_QSFP 

CLK_SFP+HS 

CLK_SFP+LS 

FPGA Config 

GTX Expansion 

Header 

USB 2.0 

SEARAY 

Features 

• ASIC prototyping daughter card, stand-alone, or PCIe-hosted Serial I/O 

- 10GbE/40GbE/100GbE 

• Xilinx Virtex-6 HXT FPGA (FF1923) 

- HX565T-2,-1 or HX380T-3,-2,-1 (fastest to slowest) 

• 24 GTH transceivers (to ~11 Gb/s) 

• 40 GTX transceivers (to 6.5 Gb/s) 

• Virtex-6 HX565T resources: 

- 2M ASIC gates (ASIC measure) 

- 354k flip-flop/6-input LUTs (708k total FFs) 

- 4MB embedded memory (1824, 18 kbit blocks) 

- 864, 25x18 multipliers 

• Multiple High speed serial I/O Interfaces: 

- CFP Module – 10 lanes (GTH): 

• Single 40GbE (IEEE 802.3bg) or 100GbE 

- IEEE 802.3ba and IEEE 802.3bg 

- CAUI, XLAUI, OTL4.10, OTL3.4, and STL256.4 et al. 

- 2 – QSFP+ Modules (GTH) 

• Single 40GbE or 4 channels of 10GBASE 

- 4 – SFP+ Modules (GTH) 

• 4 channels 10GbE 

- 8 – SFP+ Modules (GTX) 

• 8 channels 10/100/1000GbaseT 

- Dual Serial ATA II (SATA II) Host/Device 

- 8 channels on GTX Expansion header 

- 2 GTH channels on SMAs 

• Bulk memory: 240-pin DDR3 uDIMM 

- 72-bit data width (64-bit with 8-bit ECC), 533MHz operation, PC3-8500 

- Addressing/power to support 16GB (+ ECC) 

RS232 

(LCD) 

JTAG 

CPLD 


4 

4 


iPASS Connector 


Board 

Cray/Sun/Intel/HP/et al. 



- Optional RLDRAM DIMM instead of DDR3 for ultra low latency 

• Optional cabled PCIe GEN1/GEN2 hosting (with DNMEG_CBL_GEN2) 

- Dual 1-lane, Dual 4-lane or single 8-lane 

- (Optional) PCIe clock slow down IP 

• Allows clocking the PIPE interface as slowly as 35 MHz 

- PCIe PIPE Slowdown Core 

• Flexible, abundant clock resources 

- 4 board-level clocks configurable clocks 

• Silicon Image Si5338: 0.16 to 710MHz 

- Fixed 150MHz oscillator for SATA II. Fixed 100MHZ oscillator for PCIe 

• Mount to DINI products with 400-pin MEG-Array connectors 


• 550MHz on all signals with source synchronous LVDS. Slower 

when used single-ended 

- Pin multiplexing to/from motherboard using ISERDES/OSERDES 

and LVDS (up to 10x) 

• Supplied power rails (fused): +12V (24W max), +5V (10W 

max), +3.3V (10W max) 


• FMC (Vita 57) interface for use with off-the-shelf I/O boards 

- A/D-D/A, CameraLink, DSP, and RF Transceivers 

• Fast and Painless FPGA configuration with integrated uC and EEPROM 

• Dual RS232 ports for embedded uP debug and monitoring 

• Battery socket for configuration bitfile encryption 


- ChipScope, ChipScope Pro, Veridae, and other third party solutions 

• Enough status LEDs to mystify a small trout

Specialty 204-pin SODIMM 

DNSODM204_SSRAM 

SSRAM: Pipeline or NoBL 

A [22:0] 

DQ [35:0] 

ADV / LD 

BW [A, B, C, D] 

23 

36 

SSRAM 

A [22:0] 

DQ [35:0] 

ADV / LD 

BW [3:0] 

DNSODM204_SE 

Mobile SDRAM, Flash 

Ck0 

RAS 

* 

CAS 

* 

WE 

* 

address 

15 

Mobile SDRAM 

WE 

CE [1:0] 

CEN 

ZZ 

OE 

CLK 0 

WE 

CE [1:0] 

CEN 

ZZ 

OE 

data 

Ck1 

16 

16M x 16 

Mobile SDRAM 

DQ [71:36] 

SSRAM 

A [22:0] 

DQ [35:0] 

BW [E, F, G, H] 

ADV / LD 

BW [3:0] 

data 

16 

WE 

CE [1:0] 

16M x 16 

CEN 

CLK 1 

ZZ 

OE 

8 

control 

address 25 

Flash 

(28F256) 

A [24:23] 

NC (future expansion) 

CS, SI, SO, RST, WP, SCK 

6 

Data Flash 

data 

16 

16M x 16 

DNSODM204_SSRAM1_8V 

SSRAM: Pileline or NoBL, 16M x 72 

+1.8V for Virtex-7, 144MB 

24FC256 IIC 

Serial EEPROM 

5 

SCL,SDA,SA0,SA1,VDDSPD 

204 

USB2.0 Phy, SPI Flash, NAND Flash 

5 Cntl[CKEn,Wn,En,Gn,BWxn,ADV,ZZ,LBOn] 

23 

A[22:0] 

4 

CLK[3:0] 

BA0 

Bank 0 only 

8 Data (12 Control) 

Nand Flash 

GS81284Z18-xxxV 

144Mb SSRAM 

8M x 18 NBT 

DQ[54:71] 

204-pin 

“DD3” SODIMM 


USB PHY USB 2.0 

(480Mb/s) 

To 


32 Data 

Header 


144Mb SSRAM 

8M x 18 NBT 

DQ[36:53] 

32 Data 

Header 

SPI Flash 


144Mb SSRAM 

8M x 18 NBT 

DQ[18:35] 



144Mb SSRAM 

8M x 18 NBT 

DQ[17:0] 

DNSODM204_QUADMIC 

4 Mictors 

MICTOR 

DNSODM204_DDR2_FAST 

DQ [63:0] 

64 

Ck Ck 

30 

DDR2 

64M x 8 

DDR2 

64M x 8 

MICTOR 

8 

8 

34 

DDR2 

64M x 8 

DDR2 

64M x 8 

MICTOR 

8 

8 

34 

DDR2 

64M x 8 

DDR2 

64M x 8 

MICTOR 

8 

8 

34 

Addr 

8 

DDR2 

64M x 8 

18 

8 

DDR2 

64M x 8 

Control 

(RAS, CAS, WE) 

858 . 454 . 3419 29

Virtex - 7 (using DINAR1_SODM204) | Virtex - 6 

DNSODM204_DDR2_2GB 

DNSODM204_ARMDEBUG 

ARM Debug and Trace Interfaces 

DQ [63:0] 

ck ck 

64 

MT47H256M8 

MT47H256M8 

DDR2 

256M x 8 

DDR2 

256M x 8 

8 

8 

MT47H256M8 

MT47H256M8 

8 

DDR2 

256M x 8 

MT47H256M8 

DDR2 

256M x 8 

8 

DDR2 

256M x 8 

MT47H256M8 

DDR2 

256M x 8 

COMING SOON. 

consult factory for details 

8 

8 

MT47H256M8 

MT47H256M8 

DDR2 

256M x 8 

DDR2 

256M x 8 

8 

8 

Addr 

control 

(RAS, CAS, WE) 

DNSODM204_QDRII+ 

QDRII+: 4M x 32 

DNSODM204_MICTOR_IO 

Mictor, DIP Switch, I/O, +5V tolerant, EEPROM, I2C 

C,C* 

18-pin IDC Connector 

CQ,CQ* 

D 

(17:0) 

DQ[15:0] 

18 

(16) 

4M x 18 QDR II+ SSRAM 

16 

16 

Level 

Trans 

(+5V Tolerant) 

A 

(19:0) 

CK* 

CK 

20 

K 

K 

Address 

Register 

CLK. 

Gen. 

Write Add. Decode 

Write Write Write Write 

Reg Reg Reg Reg 

Read Add. Decode 

1M x 18 Array 

1M x 18 Array 

1M x 18 Array 

1M x 18 Array 

Read Data Reg. 

Address 

Register 

Control 

Logic 

A 

20 (19:0) 

RPS 

C 

C 

CQ 

8 

8 

DIP 

Switches 

(2) 

72 

CQ 

WPS 

BWS 

[1:0] 

DK[47:32] 

Control 

Logic 

36 

36 

Reg. 

Reg. 

Reg. 

18 

18 

Q 

(16) [17:0] 

MICTOR 

16 

34 

DQ[31:16] 

D 

(17:0) 

A 

(19:0) 20 

CK* K 

CK K 

18 

Address 

Register 

CLK. 

Gen. 

(16) 

Write Add. Decode 

Write 

Reg 

1M x 18 Array 

Write 

Reg 

1M x 18 Array 

Write 

Reg 

1M x 18 Array 

Read Data Reg. 

Write 

Reg 

1M x 18 Array 

Read Add. Decode 

4M x 18 QDR II+ SSRAM 

Address 

Register 

Control 

Logic 

20 

RPS 

C 

C 

A 

(19:0) 

CQ 

2 

Ck1P 

EVENTn 

LED 

(2) 

SMA 

External Clock Input 

WPS 

BWS 

[1:0] 

DQ[63:48] 

RPS* 

Control 

Logic 

72 

36 

36 

Reg. 

Reg. 

Reg. 

18 

CQ 

18 

Q 

(16) [17:0] 

RSTn 

A0, A1 

SCL 

SDA 

EEPROM 

(24LC01) 

CQ,CQ* 

C,C* 

SCL 

I 2C 

Level 

Translator 

SDA 

I 2C Header 

+2.5V 

+3.3V 

30 

www.dinigroup.com

DINAR1 Daughter Cards 

DINAR1_SOC 

18 

RGMII 

KSZ9031RNX 

10/100/1000 

RGMII Ethernet 

Transceiver 

+5VDC 

RJ45 

10/100/1000 

Base-T 

Ethernet 

14 

ULPI 

USB3317 

USB 2.0 

Transceiver 

2 

Power 

Switch 

USB 2.0 

4 

Serial Data 

LTC2804CGN 

Dual RS232 

Transceiver 

4 

4 

Dual DB9 

Dual 

RS-232 

5 

4 

Serial Audio Data 

SPI/I2C 

PCM3793ARHBR 

Stereo Audio 

CODEC 

Mic In (2) 

Line Out 

Speaker Out 

(Stereo) 

DINAR1 Motherboard Header 

(400 pins) 

12 

2 

2 

8 

8 

2 

2 

12 

SD Bus 

Clock Inputs 

Clock Outputs 

8 GPIO + OE/DIR 

1.8V3.3V 

Translators 

(with bypass 

for 1.8V 

operation) 

IP4855CX25 

SD Card Voltage 

Translator 

GP SPI Bus 0 

GP SPI Bus 1 

GP IIC Bus 0 

GP IIC Bus 1 

GP Inputs/Outputs 

SD/SDHC/ 

SDXC/SDIO 

Clock Inputs 

Clock Outputs 

9 

ARM JTAG 

8 

DQ 

8 Controls 

16 DQ 

26 Address 

8 Controls 

2 x MT29F16G08 

2 GB (16 Gb) 

NAND Flash 

2 x 28F00AP30 

128 MB (1Gb) 

NOR Flash 

2 

8 

AT24C512 

IIC Bus 

64KB (512Kb) 

EEPROM 

SPI Bus (3 Chip Selects) 

Features 

• 10Base-T/100Base-T/1000Base-T Ethernet Transceiver (802.3) 

- RGMII bus interface 

• USB2.0 Transceiver 

- Device, host, or On-The-Go device (OTG) 

- ULPI bus interface 

• 2 – RS232 ports 

- DB9 connector 

• 16-Bit, Low-Power Stereo Audio CODEC (PCM3793) 

- Microphone Bias 

- Headphone 

- Digital Speaker Amplifier 

• Secure Digital Card Interface Connector (SDIO) 

- I/O Voltage translation 

- Power – 100ma@3.3V 

• Single channel external clock input 

- Via dual SMAs 

• Single channel clock output 

- Via dual SMAs 

AT25512 

64KB (512Kb) 

EEPROM 

AT25DL081 

1MB (8Mb) 

Serial Flash 

N25Q256A11E 

64MB (256Mb) 

Serial NOR Flash 

• Miscellaneous general purpose I/O (+3.3V) 

- 8-bits on 16-pin 0.1” IDC connector (2 sets) 

• Intended for SPI 


• Intended for I2C 


• Intended for GPIO of any sort 

• ARM JTAG Connector 

• NAND Flash – MT29F16G08 

- 16 Gb with 8-bit data 

• NOR Flash -- 28F00AP30 

- 1 Gb with 16-bit data 

• EEPROM – AT24C512 

- I2C interface, 512 Kb 

• Bussed on a shared SPI 

- EEPROM - AT25512, 512 Kb 

- Serial Flash - AT25DL081, 8Mb 

- Serial NOR Flash N25Q256A11E 

858 . 454 . 3419 31

LED 

(x8) 

LEDs 

(X8) 

DINAR1 Daughter Cards 

DINAR1_LOOPBACK 

38 

38 

Loopback adapter card intended for manufacturing 

test of the DINAR1 expansion connector 

DINAR1 

Resistor 

Array 

38 

38 


Add a 204-SODIMM memory module to any 

DINAR1 expansion connector 

DINAR1 Expansion 

Connector 

8 

10 pin IDC 

130 

64-bit 

data 

DDR3 SODIMM 

(4GB Max) 

204-pin module 

options are on page 

29 - 30 

Regulator 

DDR3 

VTT 

+12V 1.5V 

Regulator 

4.3A 

DIMM 

VDD 

DINAR1_CBL 

30” 

Connect two cards together via a cable 

DINAR1 Connector 

DINAR1 Connector 

SEAM 

SEAM 

DINAR1_OBS 

+3.3V 

+12V 

Power 

LEDs 

Linear 

Reg 

Linear 

Reg 

Linear 

Reg 

Linear 

Reg 

Linear 

Reg 

+12V +3.3V 

32 

DDR3 

IODELAY 

Calibration 

Clock In 

VCCO_0 

(+1.8V) 

VCCO_1 

(+1.8V) 

VCCO_2 

(+1.8V) 

2.5V 

2.55V 

SMA 

OSC 

8 

200 MHz 

Clock Out 

SMA 


2 

DINAR1 Expansion 

Connector 

4 

34 

19 

34 

19 

Voltage 

Translate 

MICTOR 0 

MICTOR 1 

8-pin IDC 

+3.3V 

User 

DIP Switch 

+1.8V 

+1.8V 

+3.3V 

LED 

VCCO_0 

VCCO_1 

GPIO 0 

GPIO 1 

40-pin 0.1” 

IDC Connector 

+1.8V 

40-pin 0.1” 

IDC Connector 

+1.8V 

Miscellaneous useful interfaces 

• Adjustable I/O voltages via on-board regulators 

- 3 separate banks individually configurable to +1.2V to +1.8V 

• Status LEDs: 

- Power: +12V, +3.3V, +2.5V 

- 8 user-controlled via FPGA pin 

• Two Mictor connectors: 34 single-ended signals each 

• Two 40-pin dual row IDC headers 

- 19 single-ended signals 

- +1.8V 

• Two 8-pin single row headers 

- 8 single-ended signals 

- +3.3V 

• Differential external clocks input via SMAs 

• Differential external clocks output via SMAs 

• 4 position DIP switch 

- 1 position with LED 

• Linear regulator for setting I/O bank voltage 

- 1 per bank (total of 3)

DINAR1 Daughter Cards | DNNMB 

DINAR1_FMC-LPC 

Low pin count FMC card transposer 

DINAR1_K7_FMC-HPC 

COMING SOON. 

consult factory for details 

DINAR1_INTERCON 

Add more FPGA to FPGA Interconnect 

DINAR1 

75 

75 

• Converts two, 400-pin, DINAR1 Expansion connectors into FPGA to FPGA interconnect 

- 75 pairs of length matched LVDS or 150 signals single-ended 

LVDS when paired, but 

can be run single-ended 

at a reduced frequency 

- LEDs indicate status for resets, power rails, and VCC voltages 

- VccI/O regulators 

DINAR1 

- Topside, Dual 400-pin, connectors for DINAR1_Obs Observation Daughter card 

DNNMB_CONNECTOR 

QSE 

Stacking transposer for NMB connector 

NMB CONNECTOR 

NMB1 

YMB 

NMB2 

CLKS 

CLKS 

CLKS 

40 

40 

40 

5 

5 

5 

QSE 

QSE 

QSE 

QSE 

QSE 

858 . 454 . 3419 33

HPI 

connector 

40-pin 

smc connector 

40-pin 

10-pin 

IDC 

IDC 

SMA 

38 

38 

10 

11 

sel 

+3.3V 

5 

6-pin 

1.8v 

1.8v 

1.8v 

1.8v 

3.3v 

+3.3v 

3.3v 

+3.3v 

DNMEG Daughter Cards 

DNMEG_OBS_III 

EXT_osc 

Aux 

(3.3v tolerant) 

SDIO 

ARM JTAG 

Header 

(+3.3v tolerant) 

GPIO 

(1.8v tolerant) 

MEG-Array Expansion 


Debug Header (Mictor for Logic Analyzer) 

I 2 S 

Audio 

Codec 

PCM3793 

MIC (L & R) 

Speaker (L) 

Speaker (R) 

SPI 

Reset 

Button 

SPI 

MAX 

3107 

MAX 

3205 

RS232 

Reset 

Switch 

SDIO - MicroSD 

Card Adapter 

DNMEG_ETHERNET 

Analog In DC 

SMA 

Phono 

Jack 

SMA 

MEG Array 

14.18 

MHz 

THS4509 

Diff. Amp 

SMA 

xfrmr 

couple 

ADC_Clkout 

DC 

13/14-bit ADC 

ADC 

ADS5474 (14 bits) 

or 

ADS5440 (13 bits) 

24 

24 

5 

LED 

(5) 

MEG Array Expansion Connector 

(400 - pin) 

2 

RGMII 

5 

Video DAC 

ADV7127 

10-bits 

RS232 

10/100/1000 

Base-T 

Phy 

(RTL8251CL) 10/100/1000 

Base-T 

Ethernet 

10-pin 

IDC Header 

Phono 

Jack 

Add multiple high speed 

Ethernet connections to 

Dini Group FPGA boards 

with this adapter. 

68-pin 

SCSI Style 

20 

40-pin 

IDC 

DNMEG_HAAPS 

MEG Array 

Virtex-6 and Stratix-4 

(28 diff pairs) Altera Banks 0-2 

(2 diff pairs Rx CLK) or 4 LVCMOS signals 

I 2 C Interface 

+2.5V PSU 

+3.3V Power 

FETs 

HAPPS Connector 

(Samtec) 

Connect third party peripheral 

boards using the 

Samtec ASP-125521-03 to 

Dini Group FPGA cards using 

this handi transposer. 

DNMEG_LCDDRIVER 

The DNMEG_LCDDRIV- 

ER board is a converter 

from lvcmos to 7x datarate 

LVDS signals with an appropriate 

pattern for LCD 

panels. 

34 

www.dinigroup.com

SMA 


DNMEG_SODIMM4_FLASHSOCKET 

MEG - Array Expansion 


Addr 9 

Data 16 

Control 13 

120 

DDR2 SODIMM 

(2GB Max) 

FLASH 

Socket 

(48TSOP) 

DNMEG_EXT 

Addr 

Data 

Control 

MICTOR 

MICTOR 

The DNMEG_SODIMM_4FLASH 

is a daughter card intended to add 

four Hynix FLASH memories and 

a DDR2 SODIMM to any expansion 

slot on an FPGA board from 

The Dini Group. A 48-pin TSOP 

socket is used, allowing the FLASH 

memories to be programmed by an 

off-the-shelf FLASH programmer. 

The Hynix HY28UG088g is the target 

FLASH device, but connections 

are provided to allow the use of almost 

any FLASH chip in a 48-pin TSOP 

package. The interface to all FLASH 

memories is easily debugged using a 

logic analyzer cabled to two mictor 

connectors. The two mictors are connected 

to all four of the FLASH memory’s 

address, data, clock, and control 

signals. A wide variety of SODIMMs 

can be used with this daughter card. 

The DNMEG_EXT riser card is a 

passive card that allows all signals to 

pass through. It raises a daughtercard 

by 14mm and is also useful for 

connecting multiple daughtercards. 

It is compatible with all Dini Group 

FPGA boards and daughtercards with 

MEG-Array connectors. 

DNMEG_FLASHSOCKET 

External 

Clock Input 

MEG - Array Expansion 


Addr (Control) 22 

Data 

Addr (SDRAM) 5 

DNMEG_OBS 

+3.3V 

32 

32 

7 

Control (SDRAM) 10 

Clk 

= LVDS when paired, 

but can be used 

single-ended at a 


I/O Voltage Control 

(1.2V to +3.3V) 

Bank 0 

Bank 1 

Linear 

Regulator 

+3.3V 

20-pin 

Header 

MICTOR 

Linear 

Regulator 

I/O Voltage Control 

Rocket I/O 

(1 Channel) 

MGTCLK input 

16 

VCC_B0 

v11 

SMA 

(Rx/Tx) 

SMA 

4 

26 

16 

(8 Pairs 

LVDS) 

VCC_B1 

1 

FLASH 

Socket 

(TSOP48) 

I/O 

68-pin 

‘SCSI-Style’ 

Connector 

Micron 

Mobile 

SDRAM 

I/O 

FCI 

MEG-array 

Ball Grid 

Connector 

300-pin 

+12V 

16 

+5V 

+3.3V 

26 

36 

(18 Pairs 

LVDS) 

3 

clk 2 

GCA 

GCB 

20 

Addr (Control) 

Addr (SDRAM) 

Data 

22 

5 

16 

Control (SDRAM) 10 

40-pin 

IDC Connector 

40-pin 

20 

IDC Connector 

40-pin 

11 

IDC Connector 

v10 

MICTOR 

(4A) 

(4A) 

(6A) 

40-pin Header 

(0.1" pin spacing) 

4 

Samtec 

(3 Rocket I/O 

channels) 

MICTOR 

MICTOR 

+12V +5V +3.3V 

GCC 

Power 

LEDs 

The DNMEG_Flashsocket is a daughter 

card intended to add a single Hynix 

FLASH to any expansion slot on FPGA 

boards from The Dini Group. A 48-pin 

TSOP socket is used, allowing the 

FLASH memory to be programmed 

by an off-the-shelf FLASH programmer. 

The Hynix HY28UG088G is the 

target FLASH device. We also provide 

connections to enable use of almost 

any FLASH chip in a 48-pin TSOP 

package. 

The DNMEG_Obs Observation 

Daughter card is a complete solution 

for observation of signals on a 

300-pin or 400-pin FCI MEG-Array 

connector and is used with the 

DN8000K10-series, DN7000K10- 

series, DN9000K10-series, and other 

FPGA-based products from The Dini 

Group. 

+3.3V 

Linear 

Regulator 

VCC_B2 

FPGA_clk_OUT [P,N] 

2 

Resistor 

Select 

Resistor 

Select 

Bank 2 

I/O Voltage 

Control 

40-pin 

Header 

4 

24 

(12 Pairs 

LVDS) 

400-pin 

36 

(18 Pairs 

LVDS) 

4 

40-pin Header 

2 

2 

2 

125MHz 

v1.01 

858 . 454 . 3419 35

PROM 


LEDs 

(8) 

Bottom 

Top 

(From FPGA) 

114.285MHz 

Clock Synth 

Si5326 

2KHz to 600MHz 

114.285MHz 

Clock Synth 

Si5326 


114.285MHz 

Clock Synth 

Si5326 




93 

93 

SMA 

clkmult 0 

clkmult 1 

clkmult 2 

XCF32 

Config 

PROM 

SPI 

Flash 

(16Mb) 

EXT_clk 

123 

8 2 

User 

LED's 

(8) 

17 11 

RS232 

4 

4 

1 

SMA 

DisplayPort 

(Source) 

4 pairs 

DisplayPort 

(Sink) 

4 pairs 

SFP Socket 

4 

4 

3 

2 

1 

0 


iPASS Connector 

Cray/Sun/Intel/HP/et al. 



DNMEG_V5T_PCIe 

JTAG 



Daughter Card to all: 

DN8000 

-- FX70T 

DN9000 Series Products 

} SX95T 

DN7000 

FX100T only 

LX110T 

} 

LX155T 

200 MHz 

step 

200 MHz 

100 MHz 

200 MHz 

100 MHz 

DDR2 SODIMM 

(4GB Max) 

DNMEG_AD_DA 

Aux Power JTAG 

+5V 

+12V 

sma 

sma 

AD8351 

ADC0 Clock 

AD8351 

ADC1 Clock 

EE 

ADC0 

AID 

Converter 

12-bit 

210 MSPS 

(AD9430) 

ADC1 

AID 

Converter 

12-bit 

210 MSPS 

(AD9430) 


8 

RS232 

AD Data 0 

Serial Flash 

(4 mbit) 

AD Data 1 

Config 

EEPROM 

13 

1 

6 

13 

1 

2 

DDR2 

PCIe 


Virtex-5T 

LX50T/LX85T/SX50T/ 

FX70T/SX95T/FX100T 

LX110T/LX155T 

(FF1136) 

GTP 

OSC 

OSC 

200 

MHz 

100 

MHz 

DDR2 SODIMM 

(4GB Max) 

123 


Virtex 4 

LX40, LX60 

LX80, LX100, 

SX55 

(FF1148) 

Mictor 

OSC 0 

OSC1 

200 MHz 

100 MHz 

34 

93 

16 

5 

+1.5V to +3.3V I/O 




Board 

sma 

A Data Channel 1 

DAC 

B Data 

sma 

Digital to 

Channel 2 

Control Analog 

Converter 

16-bit, 160 MSPS 

(AD9777) 

MICTOR 

DAC Clock 

16 

The DNMEG_V5T_PCIE allows an 

additional PCI Express interface to be 

added to any Dini Group FPGA board, 

including the DN9000K10. It connects 

to a base-board using the high-speed 

MEG-400 daughter card interface and 

can also be used stand-alone. In addition 

to two 4-lane PCIe cable interfaces, 

this card is equipped with an SFP, 

four RX/TX channels via SMAs, and 

one 4x DisplayPort Source/Sink. 

The DNMEG_AD-DA is intended to 

be a peripheral daughter card to our 

ASIC emulation products, but can be 

used stand-alone with an inexpensive 

ATX power supply. It allows designers 

two DAC channels and two ADC 

channels for Analog-to-Digital or Digital-to-Analog 

communication. 

DNMEG_S2GX 

AUX 

Power 

connector 

+5V 10A 1.2V 

Switcher 

+1.8V 

5A 

+3.3V 

Switcher 

19.53125 

MHz 

freq_sel 

OSC 

(DDR2 

clock) 

SMA Clock 

Input 

CLK_SMA 

User 

clock 

socket 

Clock 

synths 

(ICS844051) 

OSC 

156.25 

MHz 

OSC 

62.5 

MHz 

OSC 

optional 

fixed 

frequency 

(not 

stuffed) 

78.125 MHz or 156.25 MHz 

OSC 13 

OSC 14 

OSC 15 

= Differential, but can be used 


user 

LED's 

(8) 

ByteBlasterII 

Configuration 

Flash 

Serial 

Flash 

+1.5V to +3.3V I/O 

JTAG 

DNMEG_1G_SSRAM 

8 

123 

DDR2 SODIMM 

(4GB Max) 



6 

93 

93 


Stratix II GX 

2SGX90E 

(FF1152) 

4 

(Rx/Tx) 

1 

1 

2 

sma 

0 

1 2 3 

Host 

Peripheral 

SFP socket 

SFP socket 

SFP socket 

SFP socket 

RS232 

RS232 

Level Translator 

SATA 

Interface 

The DNMEG_S2GX is a daughter 

card that enables ASIC or IP designers 

to prototype logic and memory designs 

for a fraction of the cost of existing solutions. 

Of the 12 available high-speed 

channels, four are connected to SFPs, 

four to SMAs, and four to SATA connectors. 

Add 1Gb of SSRAM to Dini Group 

FPGA boards with this adapter. 

36 

www.dinigroup.com

114.285 

MHZ 

114.285 

MHZ 

114.285 

MHZ 

EEPROM 

EEPROM 

EEPROM 

clk 0 

clk 1 

control & config 

RESET 

clk 0 

clk 1 


clk 0 

clk 1 


GTP OSC 

GTP OSC 

114.285 MHz 

114.285 MHz 

114.285 MHz 

OSC0 

OSC1 

CLK2-1 

CLK QSE 

CLK1-1 

CLK1-2 

ClK0-1 

CLK0-2 

1 

2 

Top 

Bottom 

5 

10 

0 

DDR2 

OSC 

200 MHz 

Channel 0 

MICTOR 

1 

CLK-QSE 

3 

+1.21V 

+1.5V 

+1.2V 

+3.3V 

+1.8V 

DNIOB: High Speed Serial Interfaces 

+3.3V 

DNMEG_INTERCON 

External 

Power 

(stand alone 

operation only) 

JTAG 

I/O Bank 

reference Voltage 

Ref 

VCCO 

Bank0 

Ref 

VCCO 

Bank1 

Ref 

VCCO 

Bank2 

500mA 

Config 

PROM 

+5V 

+12V 


+2.5V 

+2.5V 

+2.5V 

+12V +5V +3.3V 

LED 

LED 

LED 

400-pin 

MEG-Array 

connector 

(P1) 

DNMEG_DVI 

B0 

B1 

B2 



93 93 

Base Board Connections 

1 2 3 4 

6.5 Gb/s 

Rocket I/O 

(tx/rx) 

400-pin MEG-Array 

connector (P3) 

- LVDS when paired, but can be used 

single-ended at reduced frequencies 

93 

93 

93 

Switching 

Regulator 

Switching 

Regulator 

Switching 

Regulator 

Switching 

Regulator 

Switching 

Regulator 

93 

400-pin 

MEG-Array 

connector 

(P2) 

B_RST 

T_RST 

The DNMEG_Intercon is a daughter 

card that bridges the expansion signals 

between two 400-pin MEG-Array connectors, 

adding 93 pairs of LVDS signals 

for FPGA to FPGA interconnect. 

At a lower frequency, the 93 pairs can 

be used as 186 signal ended signals. 

Linear regulators needed to drive the 

VCCIO voltages are provided, along 

with several LEDs for power presence 

and reset activity. 

The DNMEG_DVI-400 provides duallink 

input and dual-link output Digital 

Video interface (DVI) functionality. 

DVI Input 

(Dual-Link) 

Si5326 

Freq 

Synth 

2 

2 

DVI TX0 

SIL163B 

SIL163B 

24 

24 

Config 

PROM 

XCF32 

MGT 

OSC 

24 

24 

Virtex4 


FX60/FX100 

(FF1152) 

PPC PPC 

Rocket I/O 

12 

12 

32 

12 

12 

SIL1178 

SIL1178 

DVI Output 

(Dual-Link) 

Freq 

Synth 

2 

2 

DVI TX1 

Rocket I/O 

UART 

120 

Freq 

Synth 

2 

2 

2 

2 

1 

LED's 

DDR2 SODIMM 

MGT 

4 4 

RS232 

Santec High 

Speed Cable 

Connector (QSE-DP) 

SFP 

socket 

LVDS when paired, but can be run 

single-ended at reduced frequencies. 

DNMEG_MICTOR_DIFF 

The DNMEG_Mictor_Diff daughter 

card is a solution for connecting you 

Dini Group board to a differential 

(read: NON-AMP) mictor interface. 

The PCB is routed for maximum differential 

throughput and the connectors 

pinned out to minimize crosstalk 

between pairs. 

DNMEG_V5T 

Aux Power 

+5V 

+12V 

JTAG 

EE 

RS232 

Clock Synth 

Si5326 

Clock Synth 

Si5326 

Clock Synth 

Si5326 

LEDs 

(8) 

Green 


= Differential when paired, but 

can be used single ended at 


= SX95T, FX70T, FX100T, 

LX110T, LX155T only 

= SPI Flash Configuration 

8 

2 

2 

2 

2 

2 

2 

2 

2 

5 

Serial 

FLASH 

(16 Mbit) 

sma 

sma 

EXT Clock 

user GTP 

DDR2 SODIMM 

(4GB Max) 

123 


Virtex-5T 

LX50T/LX85T/SX50T 

SX95T/FX70T/FX100T 

LX110T/LX155T 

(FFG1136) 

Config 

EEPROM 

Battery 

2 

+ 

23 

11 

200 MHz 

OSC 

(DDR2) 

GTP 

GTP 

GTP 

GTP 

MICTOR 

4 

4 

4 

4 

93 

+1.5V to +3.3V I/O 

(bottom) 



(top) 

sma 

1 2 3 

Infiniband 

0 

SFP Socket (x4) 

QSE 

- TX Fault SFP Signals 

(LX110T/ - MOD_DEF0 not available 

SX95T - RATE_SEL with LX50T, 

only) 

- LOS 

LX85T, SX50T 

The DNMEG_V5T enables engineers 

to utilize the Xilinx Virtex-5T FPGA 

for high-speed serial interconnect. It is 

hosted on any Dini Group ASIC Emulation 

/product that has MEG-Array 

expansion capability but also can be 

operated in stand-alone mode with a 

separate power supply. Connectors 

for the high-speed MGTs include four 

SMA channels (Rx/Tx), one 4x Infiniband 

connector, four SFP sockets, and 

four high-speed channels on a QSE 

connector. 

858 . 454 . 3419 37

DC2 

DC3 

SMA 

SMA 

20 

96 

96 

20 

DDR2 SODIMM 

(4GB max) 

120 120 120 96 96 


0 

Virtex-5 

LX330 

(FF1760) 

240 240 


4 

Virtex-5 

LX330 

(FF1760) 

120 120 


8 

Virtex-5 

LX330 

(FF1760) 

120 120 


12 

Virtex-5 

LX330 

(FF1760) 

160 

20 20 

20 20 

120 

20 20 

20 20 

120 

20 20 

20 20 

160 

120 120 

120 120 

120 120 

20 20 

20 20 

20 20 

20 20 

20 20 

20 20 

120 120 120 

DDR2 SODIMM 

(4GB max) 

DIMM0 DIMM1 DIMM2 

DIMM3 

Serial 

FLASH 

128Mb 

Serial 

FLASH 

128Mb 

DDR2 SODIMM 

(4GB max) 


1 

Virtex-5 

LX330 

(FF1760) 


5 

Virtex-5 

LX330 

(FF1760) 


9 

Virtex-5 

LX330 

(FF1760) 


13 

Virtex-5 

LX330 

(FF1760) 

DDR2 SODIMM 

(4GB max) 

DIMM4 

Serial 

FLASH 

128Mb 

Serial 

FLASH 

128Mb 

120 

80 

80 

120 

DDR2 SODIMM 

(4GB max) 


2 

Virtex-5 

LX330 

(FF1760) 

1 0 1 0 


6 

Virtex-5 

LX330 

(FF1760) 

1 0 1 0 


10 

Virtex-5 

LX330 

(FF1760) 

1 0 100 


14 

Virtex-5 

LX330 

(FF1760) 

DDR2 SODIMM 

(4GB max) 

DIMM5 

Serial 

FLASH 

128Mb 

MBV 

20 20 

20 20 

20 20 

20 20 

20 20 

20 20 

Serial 

FLASH 

128Mb 

140 

80 

120 

120 

140 

SMA 

SMA 

+1.5V to +3.3V I/O 

DC4 




3 

Virtex-5 

LX330 

(FF1760) 

1 0 100 


7 

Virtex-5 

LX330 

(FF1760) 

1 0 

1 0 


11 

Virtex-5 

LX330 

(FF1760) 

1 0 1 0 


15 

Virtex-5 

LX330 

(FF1760) 

96 96 



DC9 

+1.5V to +3.3V I/O 

96 

MBH 

96 

96 

MBH 

96 

SMA 



+1.5V to +3.3V I/O 

DC5 



+1.5V to +3.3V I/O 

QuickSwitch 

DC6 





+1.5V to +3.3V I/O 

+1.5V to +3.3V I/O 

QuickSwitch 

DC7 

DC8 

SMA 

80 

(quickswitches) 

MBH 

MICTOR 

Control 

32 

CY7C68013 

uP Configuration 

controller 

Clock Mux 

Control 

MBCLK 

Reference Clock 

GCLK0 

GCLK1 

GCLK2 

DC_GCLK0 

DC_GCLK1 

DC_GCLK2 

DC_GCLK3 

SRAM 

128Kb x 8 

Flash 

1 M x 8 

Config 


LX80 

(FF1148) 

Single-Step Clock 

JTAG 

USB 2.0 

48 MHz 

8 

RS232 

4 Serial 

Ports 

(Tx/Rx) 

COMPACT FLASH 


CONFIGURATION 

Reset 

96 



+1.5V to +3.3V I/O 

Config PROM 

LCD 

Control 

Panel 

PCI0 

Clock Synth 

Si5326 

Clock Synth 

Si5326 

External 

Clock SMA's 

Clock Synth 

Si5326 

External 

Clock SMA's 

Clock Synth 

Si5326 

External 

Clock SMA's 

from Daughter Card 2 (DC2) 








LED 

(x32) 

104 

104 

32 

20 

32 

32 

32 

30 

29 

(USB 3300) 

40-pin 

IDC Headers 

(x5) 

Config 

EEPROM 

RJ45 

2 

3 

3 

15 

32 

7 

22 

16 

4 

36 

16 

SDRAM 

16M x 32 

FLASH 

(32/64 MBIT) 

(AT 

49BV320D) 

2M x 16 

SSRAM 

(512k x 36) 

CY7C 

1380D 

SoundMAX 

Codec 

(AD1881A) 


CD Audio 

Line Out 

Headphone 

In 

EE 


DNMEG_DOUBLE 

+3.3V 

I/O Bank 

Reference Voltage 

Ref +2.5V 

VCCO 

Bank0 

LED 

Ref 

VCCO 

Bank1 

Ref 

VCCO 

Bank2 

500mA 

B0 

+2.5V 

B1 

LED 

+2.5V 

B2 

LED 

400-pin 

MEG-Array 

Connector 

(P1) 

93 93 

93 

93 

93 93 

400-pin 

MEG-Array 

Connector 

(P2) 

B_RST 

T_RST 

Connect two DNV6_F2PCIE cards together. 

Also works for other cards in 

the V6 line of Dini products. 

External 

Clock 

Input 

p1 

p2 

400-pin 

MEG-Array 

Connector 

(P3) 


single-ended at reduced frequencies 

+12V 

+5V +3.3V 

DNMEG_HSMC 

(VCCO regulators set to +2.5V, 

for MEG Array Signals) 

LT1963A 

Power 

MEG 

Array 

Bank #1 Bank #3 Bank #2 Bank #0 

JTAG 

IIC 

IIC 

(Level Translators) 

Altera JTAG 

Header 

Probe 

Points 

Probe 

Points 

HS Serial 

LVDS 

LVDS 

HSMC #1 

HSMC #2 

Power Power 

Connect High Speed Mezzanine Card 

(HSMC) to Dini Group FPGA boards 

with this adapter. 

SMAs for GCC Insertion 

JTAG 

Altera JTAG 

Header 

Probe 

Points 

Probe 

Points 

HS Serial 


LEDs for Status, Power 

DNMEG_FMC 

(VCCO regulators 

set to +2.5V, LDO 

for MEG Array Signals) 

+VADJ 

Power 


IIC 

JTAG 

Xilinx JTAG 

Header 

LA/HA/HB Banks 

+VADJ 

Power 

The DNMEG_FMC board is a FPGA 

Mezzanine card. 

MEG 

Array 

SelectIO Pins 

+VIO (VCCO FOR HB Signals Only) 

QSE 

Headers 

HS Serial 

(DP) 

Clocking 

CLK_UP (C2M) 

CLK_DN (M2C) 

SMAs for Clock Insertion 

PG_M2C, PSNT_M2C 

PG_C2M 

Power monitors, 

daughtercard reset 

Clocking Sideband 

DNMEG_ARM_TILE 

CPLD 

(XC9572) 

ARM7 / ARM9 / ARM 11 

ARM 

Test 

Chip 

38 

LEDs for Status, Power 

Z Memory 

Expansion 

PISMO 

Y Memory 

Expansion 

PISMO 

ARM Coretile 

DN9000 & DN7000 Series 

ASIC Prototyping Boards 

(to 50M gates) 



+1.5V to +3.3V I/O 



+1.5V to +3.3V I/O 

Y[31:0] 

Y[169:150] 

Misc Control 

(power, clocks, 

memory type/sizes, 

board ID, etc.) 

HWDATA[31:0] 

HDRZ 

HDRY 

JTAG 

MEMEXPB [103:0] 

MEMEXPA [103:0] 

FPGA_LED 

FPGA_GPIO 

CPLD Config 

JTAG 

ARM ICE 

Config 

ARM ICE 

Debug 

JTAG 

AHB 

HDRX 

Clocks, Misc control 

HADDR[31:0] 

HDATA[31:0] 

HRDATA[31:0] 

Bus Control 



25 

MHz 


Xilinx 

Spartan 3 

XCS5000 

(FG900) 

100 

MHz 

USB-OTG 

Phy 

10/100/1000 

Ethernet 

Phy 

(UCS8601) 

Addr 

Data 

Addr 

Data 

Addr 

USB 2.0 

(mini AB) 


Cntl 

Cntl 

Data 

Cntl 

AC97 Audio 

10/100/1000 base T 

Ethernet 

RS232 

Mouse 

Keyboard 

JTAG (FPGA) 

The DNMEG_ARM_TILE is an intermediate 

host for an ARM RealView 

CoreTile. It adds the features and interfaces 

necessary to make the ARM9 

(or ARM11) processor useful for prototyping. 

The combination of the DN- 

MEG_ARM_TILE with the CoreTile 

can be mounted on an ASIC FPGA 

board from The Dini Group, enabling 

full-speed system prototyping and 

debugging of high gate count ARMbased 

systems. With a separate power 

supply, the DNMEG_ARM_TILE/ 

CoreTile combo can also be used 

standalone.

DNIOB: High Speed Serial Interfaces 

DNIOB_LOOPBACK 

DNIOB_CFP 

DNIOB_PCIe 

DNIOB_QSFP 

DNIOB_SFP 

DNIOB_SMA 

DNIOB_INTERCON 

DNIOB_USB3 

858 . 454 . 3419 39

SMA 

1 

GTX 

Flash 

Flash 

Phy 

SFP 

or 

SFP+ 

8 GTX 

GTX 

4 

GTX 

4 

4 

DDR3 SODIMM 

(4GB Max) 

D 

4 

60 

E 

58 

F 

130 

130 

60 

40 

58 

20 

24 

MHz 

G0 

(2KHz 

40 

20 

GTX 

4 

GTX 

GTX 

8 

16 

12 

95 

95 

40 

40 

40 

40 

40 

40 

40 

24 

MHz 


G1 

(2KHz 

12 

GTX 

GTX 

NMB 

GTX 

GTX 

4 

PCIe 

DDR3 SODIMM 

(4GB Max) 

A 

4 

4 

1 0 

24 

MHz 

B 

4 

120 

C 

G2 

(2KHz 

130 

130 

1 0 

40 

40 

120 

20 

40 

OSC 

G0 

8 

8 

GTX 

40 

GTX 

OSC 

PCIe 

(Gen1) 

MPP Bus 

Flash 

RGMII 

Phy 

64 

3 

CPU CPU 

SPI 

USB 

(3x) 

PCIe 

SATA 

8 

RTC 

Boot 

(host) 

2x 

RJ45 

RJ45 

D 

2 

125 

MHz 

RS232 

93 

56 

93 

93 

125 

MHz 

93 

93 

93 

40 

40 

DDR2 SODIMM 

(4GB Max) 

3 

3 

3 

120 

SPI 

FLASH 

16Mb 

SPI 

FLASH 

16Mb 

SPI 

FLASH 

16Mb 

LX330 

(FF1760) 

120 

GTP OSC 

GTP OSC 

1 0 1 0 

LX330 

(FF1760) 

120 120 

LX330 

(FF1760) 

16 

Configuration 


COMPACT 

FLASH 

config 

114.285 MHz 

114.285 MHz 

114.285 MHz 

QL5064 

DDR2 SODIMM 

(4GB Max) 

164 

70 

70 

1 0 

1 0 

120 

120 

40 

40 

40 

40 

40 

40 

40 

40 

uP Config 

Control 

Config RS232 

USB 2.0 

(480 Mb/s) 

OSC0 

OSC1 

CLK2-1 

CLK QSE 

CLK1-1 

CLK1-2 

ClK0-1 

CLK0-2 

config data 

DDR2 SODIMM 

(4GB Max) 

3 

120 

SPI 

FLASH 

16Mb 

LX330 

(FF1760) 

40 40 

120 120 

LX330 

(FF1760) 

3 140 140 

SPI 

FLASH 

16Mb 

SPI 

FLASH 

16Mb 

3 

LX330 

(FF1760) 

120 

Step 

QL5064 

DDR2 SODIMM 

(4GB Max) 

Step 

120 

90 

90 

120 

(250 

MHz) 

MICTOR 

34 

LX30T, 

LX50T, 

SX35T, 

SX50T, 

FX30T, 

FX70T 

EXT0 

sma 

EXT1 

FBB 

FBE 

sma sma 

250 

MHZ 

CLK-QSE 

PCIe Ref Clock 

100MHz 

sma 

External Input 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

sma 

sma 

SATA (6 Gb/s) 

SATA (6 Gb/s) 

sma 

SFP Connector 

SFP Connector 

sma 

SMAs 

Miscellaneous Peripherals 

DNJTAG_USB 

JTAG 1 

TDI TDO 

TMS 

USB to JTAG Adapter for in-chassis 

FPGA reconfiguration 

Xilinx 

JTAG 2 

TDI TDO 

USB 

(micro-B) 

USB 

to 

JTAG 

TDI 

TMS 

TCK 

TDO 

TMS 

JTAG 3 

TDI TDO 

TMS 

Diligent JTAG SMT1 

JTAG 4 

TDI TDO 

TMS 

TCK 

PCIe 

+12V 

DNPCIe-SATA 

100 

MHz 

PCIe Ref Clock 

100MHz 

sma 

2 

2 

2 

SATA (6 Gb/s) 

10/100/1000 

ETHERNET 

(VSC8201) 

8-lane PCIe Express to Serial ATA adapter 

External Input 

0 

1 

2 

3 

4 

5 

6 

7 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

2 

16-lane PCIe 

Connector 

2 

2 

sma 

SATA (6 Gb/s) 

sma 

sma 

sma 

SFP Connector 

SFP Connector 

SMAs 

A B C 

JTAG 

+1.5V to +3.3V I/O 

+1.5V to +3.3V I/O 

+1.5V to +3.3V I/O 

Q F E 







10/100/1000 

ETHERNET 

(VSC8201) 


(bussed) 


Reset 


Virtex 5 


Virtex 5 


Virtex 5 

MB [35:0] 

Spartan 3 

MB [163:0] 

clock config 


Virtex 5 


Virtex 5 


Virtex 5 

Global Clocks 

GCLK0 

Clock Synth 

Si2536 

GCLK1 

Clock Synth 

Si2536 

CLK_FB 

(from FPGA A) 

DDR2 SODIMM 

(4GB Max) 

DDR2 SODIMM 

(4GB Max) 

Xilinx 

Virtex 5T 

GCLK2 

Clock Synth 

Si2536 

(zero delay) 

Daughtercard D 

Daughtercard E 

(zero delay) 

Daughtercard F 

MB48CLK 

48MHz 



Ref_CLK 

100 

MHz 

16-lane PCIe 

Connector 

DNUSB30_USB20 

USB 3.0 

sma 

TX 

RX 

USB 2.0 

DM 

DP 

ID 

Micro - AB 

Mini - AB 

Aux Power 

+5V 

+12V 

DN9000K10PCIe-8T 

JTAG 

EE 

RS232 

Clock Synth 

Si5326 

Clock Synth 

Si5326 

Clock Synth 

Si5326 

LEDs 

(8) 

Green 


8 

2 

2 

2 

2 

2 

2 

2 

2 

5 

DDR2 SODIMM 

(4GB Max) 

123 


Virtex-5T 

LX50T/LX85T/SX50T 

SX95T/FX70T/FX100T 

LX110T/LX155T 

(FFG1136) 

2 

GTP 

GTP 

GTP 

GTP 

DNPCIe_SATA 

200 MHz 

OSC 

(DDR2) 

4 

4 

4 

4 

93 

Infiniband 

QSE 

(LX110T/ 

SX95T 

only) 

+1.5V to +3.3V I/O 



(top) 

USB3.0 Prototyping using GTX via SMAs 

sma 

SFP Socket (x4) 

- TX Fault 

- MOD_DEF0 

- RATE_SEL 

- LOS 

(bottom) 

1 2 3 

0 

SFP Signals 

not available 

with LX50T, 

LX85T, SX50T 

sma 

USB 2.0 

Mini - AB 

TX 

RX 

DM 

DP 

ID 

USB 3.0 

Micro - AB 

Floppy 

HDD Power 

Connector 

+5V 

5A 

5V 

Good 

(GRN) 

5V to 

3.3V 

PVBUS 3.3V 

1.5A Max 

USB Power 

DNPCIe_CBL_GEN2 

= Differential when paired, but 

can be used single ended at 


= SX95T, FX70T, FX100T, 

LX110T, LX155T only 

= SPI Flash Configuration 

Serial 

FLASH 

(16 Mbit) 

sma 

EXT Clock 

sma 

user GTP 

Config 

EEPROM 

23 

11 

MICTOR 

+ 

Battery 

ATX 

Power 

Supply 

+5V 

5A 

5V to 

3.3V 

5V 

Good 

(GRN) 

PVBUS 3.3V 

1.5A Max 

USB Power 

Bridge GNE2 PCIe with a iPASS cable 

GTX Expansion 

Header 

USER_R 



128Mb 



128Mb 






10/100/1000 

CLK_25 

(25 MHz) 

96 96 

96 96 

96 96 

SATA II 

(device) 

USER_L 





GTX FPGA 

GTX 


Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

DDR3 SODIMM 

(4GB Max) 

(host) 

114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

to 700 MHz) 

20 20 73 73 

40 74` 74 


Virtex-5 


114.285 MHz 

Frequency 

Synthesizer 

(Si5326) 

to700 MHz) 

114.285 MHz 


GTX FPGA 

GTX 


Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

Virtex-6 

LX240T/LX365T 

SX315T 

LX550T/SX475T 

(FF1759) 

DDR3 SODIMM 

(4GB Max) 

Frequency 

Synthesizer 

(Si5326) 

to 700 MHz) 

MGT Clock 

125 MHz 

150 MHz 

250 MHz 

312.5 MHz 

4 - lanes 

128Mb 

GTX Expansion 

Header 

128Mb 

FLASH 

GTX Expansion 

Header 

128M x 64 

DDR2 

128Mb 

Boot FLASH 


FPU FPU 

DMA(4x) 

10/100/1000 10/100/1000 

baseT 

RJ45 

RS232 

USB 2.0 

4-lanes 

256Mb 

SATA II 

PCIe (GEN1) 

NAND FLASH 

PCI EXPRESS 

iPASS 

Connector 

4 

4 

PCIe 

Driver 

Ref-Clk Jitter 

Attenuator 

iPASS 

Connector 

4 

4 

PCIe 

Driver 

DNPCIe_CBL_GEN2 (slot) 

iPASS 

Connector 

4 

4 

PCIe 

Driver 

Jitter Ref-Clk 

Attenuator 

iPASS 

Connector 

4 

4 

PCIe 

Driver 

DNPCIe_CBL_GEN2 (finger) 

Finger 

PCIe GEN2 

(8-lane) 

Host 

Computer 

Slot 

4 

Ref-Clk 

4 

PCIe GEN2 

(8-lane) 

PCIe 

Driver 

Jitter 

Attenuator 

PCIe 

Driver 

4 

4 

iPASS 

Connector 

iPASS 

Connector 

4 lanes 

4 lanes 

4 lanes 

4 lanes 

iPASS 

Connector 

iPASS 

Connector 

4 

4 

PCIe 

Driver 

Jitter 

Attenuator 

PCIe 

Driver 

4 

Ref-Clk 

4 

Finger 

PCIe GEN2 

(8-lane) 

40 

www.dinigroup.com

SEAM Expansion 

DNSEAM_IPASSx4 

Add 4 iPass connection to any Dinigroup 

board with a SEARAY connector. 

DNSEAM_CX4 

Add CX4 connection to any Dinigroup 

board with a SEARAY connector. 

DNSEAM_PCIe 

Add an 8-lane GEN1/GEN2 PCI Express 

connection to any Dinigroup board with a 

SEARAY connector. 

DNSEAM_SFP 

Expansion card that hosts 8 SFP sockets. 

Attaches to the SEARAY GTX Expansion 

connectors on the DN2076k10, 

DNV6F6PCIe, DNMEG_V6HXT . Adds 8 

channels of 1x/2x/4x Fibre Channel, 

10/100/1G Ethernet, XAUI, SATA, 

Serial RapidI/O (SRIO). 

858 . 454 . 3419 41

PC3-1600 

PC3-1600 

PC3-800 

DDR3 

PC3-800 

DDR3 

DDR3 

(128M DDR3x 16) 

(128M x 16) 

PC3-800 PC3-1600 

DDR3 

DDR3 

(128M x 16) (128M x 16) 

(128M x 16) (128M x 16) 

DDR3 DDR3 

DDR3 

DDR3 

DDR3 

DDR3 

(128M DDR3 x 16) (128M DDR3 x 16) 

( M x 16) ( M x 16) 

( M x 16) ( M x 16) 

(128M x 16) (128M x 16) 

DDR3 

DDR3 

( M x 16) 

( M x 16) 

Kintex-7 

Kintex-7 

7K410T/7K325T/ 

46 

7K410T/7K325T/ 

46 

7K160T 

7K160T 

Kintex-7 

FPGA 1 


6 

(FFG676) 

(FFG676) 

7K410T/7K325T 


(FFG900) 

46 

8 CFG Bus 

46 

JTAG 

6 

1 

0 2 

Kintex-7 

Kintex-7 

78 

7K410T/7K325T/ 

46 

7K410T/7K325T/ 

3 

7K160T 

7K160T 



CPLD 4 

PCIe 

(FFG676) 

(FFG676) 

DDR3 

DDR3 

DDR3 

DDR3 

( M x 16) ( M x 16) 

( M x 16) ( M x 16) 

DDR3 

DDR3 

DDR3 

DDR3 

( M x 16) ( M DDR3 x 16) 

( M x 16) ( DDR3 M x 16) 

PC3-800 

( M x 16) 

PC3-800 

( M x 16) 

I 2 C 2 

PC3-1600 

PC3-1600 

Serial 

cfg Prog 

5 

HPCLK 

(FF484) 

EEProm 

OSC 

DDR3 Clocks 

(all FPGAs) 

cfg Prog 

5 

Flash 

HRCLK 


OSC 

Config 


SYSCLK (all FPGAs) 

4-lane PCIe 

PCIe 

(GEN1 / GEN2) 

SFB Clock (CFG Bus Clocking) 


DNK7 F5PCIe 

PCIe 

Godzilla’s Bad Hair Day 

Block Diagram v1.10 

High Performance Computing 

DNK7F5_8_Cluster 

PCIe 

Bridge 

DNK7_F5PCIe 

PCIe (GEN1/GEN2) 

4 4 4 4 4 

4 4 4 

PCIe Fan Out 

Switch 

PCIe Fan Out 

Switch 

8 8 

PCIe 

Xeon E3-1275 

(CPU1) 

8 GB DDR3 

8 GB DDR3 

8 GB DDR3 

8 GB DDR3 

Platform 

Controller 

Hub 

(3420) 

6 

LAN 1 

10/100/1000 base-T 

LAN 2 

USB 0 

USB 1 

Video (SandyBridge) 

HDD 

Up to 6 HDD (SATA3 ) 

Features 

• 5U Rackmount Chassis containing: 

- 1 Intel Xeon® E3-1275 processor card 

- DNK7_F5PCIe FPGA cards each with 5 Xilinx of the largest 

Kintex 7 FPGAs (7K410T) 

• PCIe 4-lane (GEN1/GEN2) 

• 40 FPGAs in total, 100% dedicated to application 

- Other configurations with different CPU to FPGA ratios are available 

- 2 bays for SATA-2 hard drives 

• Processor card 

- Intel Xeon® E3-1200 series processors (Sandy Bridge), 3.4 GHz 

• Quad-Core, 8MB shared L2 cache 

• 4 GB DDR3 memory (4 GB total) 

• Options up to 32 GB (32 GB max) 

• VGA with standard D-Sub connector 

• 10/100/1000BASE-T Ethernet (2 ports) 

• USB 2.0 (4 ports total) 

- 2 ports on front panel 

- 2 ports on back bracket 

• Supports most all Linux distributions 

• DNK7_F5PCIe FPGA HPC Acceleration card 

- PCI Express (4-lane) FPGA-based algorithm acceleration 

peripheral with 5 Kintex-7 FPGAs 

• 4 Xilinx Kintex-7 FPGAs: 7K410T-1 (FFG676) 

- 7K410T-3,-2,-1, 7K325T-3,-2,-1, or 7K160T-3,-2,-1 

• 1 Xilinx Kintex-7 FPGA: 7K325T-1 (FFG900) 

- 7K410T-3,-2,-1 or 7K325T-3,-2,-1 

The DNK7_F5_8_Cluster is a complete, 5U rack mount FPGA acceleration 

cluster. The standard configuration contains the following: 

Trenton TSB7053 Xeon processor card 

8 DNK7_F5PCIe Kintex 7 FPGA cards with 5 7K410T-1 FPGAs per card. 

1.5 TB SATA II Hard Drive 

This system contains the maximum number of cost effective FPGA that 

can be reasonability integrated into a 5U chassis. Power and cooling are 

the constraining variables. High performance data paths between FPGA 

boards enable data movement under algorithmic control that is wholly 

separate from the host processor, enabling FPGA-based acceleration of 

whole new classes of data intensive algorithms. 

In short, the DNK7_F5_8_Cluster is a massive number of large, low 

cost FPGAs integrated with an excellent dual Xeon-based processor 

host. 

A partial list of possible applications includes: 

Bioinformatics 

Genomic Search 

Financial Analytics 

- Low Latency Analysis 

- Derivative Calculations 

Image Processing 

Signal Processing 

Radar 

Scientific Computing 

Video Compression 

Encryption/Decryption (Cryptography) 

42 

www.dinigroup.com

DNK7_F5PCIe 

PC3-800 

DDR3 

(256M DDR3 x 16) 

(256M x 16) 

DDR3 

(256M x 16) 

PC3-1600 

DDR3 

(256M DDR3 x 16) 

(256M x 16) 

DDR3 

(256M x 16) 

PC3-800 

DDR3 

(256M x 16) 

DDR3 

(256M x 16) 

PC3-1600 

DDR3 

(256M DDR3x 16) 

(256M x 16) 

DDR3 

(256M x 16) 

PC3-800 

DDR3 

(256M x 16) 

DDR3 

(256M x 16) 

PC3-1600 

DDR3 

(256M DDR3x 16) 

(256M x 16) 

DDR3 

(256M x 16) 

Kintex-7 

7K410T/7K325T 


(FFG900) 

46 

Kintex-7 

7K410T/7K325T 


(FFG676) 

46 

6 

Kintex-7 

7K410T/7K325T 


(FFG676) 

LED 

46 

46 

8 

CFG Bus 

JTAG 

1 

0 2 

CPLD 4 

PCIe 

3 

78 

Kintex-7 

7K410T/7K325T 


(FFG676) 

6 

46 

Kintex-7 

7K410T/7K325T 


(FFG676) 

PCIe 

Bridge 

(FF484) 

I 2 C 

2 

Serial 

EEProm 

Flash 


Config 

DDR3 

DDR3 

DDR3 

DDR3 

(256M x 16) 

DDR3 

(256M x 16) 

(256M x 16) 

DDR3 

(256M DDR3 x 16) 

(256M x 16) 

DDR3 

(256M x 16) 

(256M x 16) 

DDR3 

(256M DDR3 x 16) 

PC3-800 

(256M x 16) 

PC3-800 

(256M x 16) 

PC3-1600 

PC3-1600 

cfg 

cfg 

Prog 

OSC 

Prog 

OSC 


5 

5 

HPCLK 

HRCLK 

DDR3 Clocks 

(all FPGAs) 

SYSCLK (all FPGAs) 

PCIe 

4-lane PCIe 

(GEN1 / GEN2) 

PCIe 


SFB Clock (CFG Bus Clocking) 

The DNK7_F5PCIe is Xilinx Kintex-7 based FPGA board optimized for algorithmic acceleration applications requiring FPGAs with high performance local 

memory. Data movement to/from the FPGA grid is accomplished via a fixed 4-lane, GEN1/GEN2 PCIe bridge. Each field Kintex-7 FPGA (FPGAs 1-4 

in the block diagram) has five separate 256M x 16 DDR3 (4 Gb) memories. The Dataflow Manager FPGA (FPGA 0 in the block diagram) has six 256M x 

16 DDR3 memories. 

Features 

• PCI Express (4-lane) FPGA-based algorithm acceleration 

peripheral with 5 Kintex-7 FPGAs 

- 4 Xilinx Kintex-7 FPGAs: 7K325T-1 (FFG676) 

- 1 Xilinx Kintex-7 FPGA: 7K325T-1 (FFG900) 

• Fixed 4-lane PCIe interface and controller 

- PCIe GEN1/GEN2 

- Full mastering DMA 

• 2 transmit (host memory -> card) 

• 2 receive (card -> host memory) 

• Xilinx FPGA Kintex-7 7K325T-1 – 5 total user FPGAs 

- 407,600 flip-flops per FPGA 

• 203K flips-flops with 6-input LUT 

- 840, 25x18 multipliers + 48-bit accumulator per FPGA 

- 890, 18 Kbit block RAM (2 Mbytes) per FPGA (or 445, 

36 Kbit blocks) 

• Fully dual-ported 

• Each block RAM configurable as: 

32K × 1, 16K × 2, 8K × 4, 4K × 9 (or 8), 

2K × 18 (or 16), 1K × 36 (or 32), or 512 × 72 (or 64) 

- Options for the larger 7K410T when available. 

• FPGA to FPGA interconnect is single-ended 

- Source synchronous FPGA -> FPGA frequency: 400 MHz 

• 400 Mb/s per pin when using DDR 

• Config Bus (CFG) connects all Kintex-7 FPGAs (8 signals) 

- 90MHz 

• 5 separate 256Mb x 16 DDR3 memories for each field FPGA 

- 3 memories PC3-1600 


- Each memory has separate address, data, and control 

• 6 separate 256Mb x 16 DDR3 memories for Dataflow 

Manager FPGA 



- Each memory has separate address, data, and control 

• Two independent low-skew global clock networks distributed 

differentially and balanced 

• Fast and Painless FPGA configuration via PCIe 

- On-board battery for AES bitstream encryption 


- ChipScope, and other third-party debug solutions 

• FPGA-controlled LEDs 

- Enough light to use as a LED-based flashlight 

858 . 454 . 3419 43

(128M x 16) 

16 

(128M x 16) 

16 

Config 

EE 

User 

EEPROM 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

16 

16 

16 

16 

16 

16 

Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 

77 

77 

77 

77 

77 

LX150 

LX150 

LX150 

LX150 

LX150 

LX150 

FPGA 0 FPGA 1 FPGA 2 FPGA 3 FPGA 4 FPGA 5 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

MB (upper) 8 

64 MB (lower) 

64 

64 

64 

64 

64 77 

8 

Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 Spartan - 6 

77 

77 

77 

77 

77 

LX150 

LX150 

LX150 

LX150 

LX150 

LX150 

FPGA 11 FPGA 10 FPGA 9 FPGA 8 FPGA 7 FPGA 6 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

(FGG484) 

32 

32 

16 

16 

16 

16 

16 

16 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

DDR3 - 800 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

(128M x 16) 

PCIe 

100MHz Clock 

Bridge 


Q 

MB Clock 

4-lane PCIe (GEN1/GEN2) 

PCIe 

Expansion Board to Board 

Cards / Dataflow 

Top 

Bottom 

QSE 

QSE 

4 4 4 4 

data 

GTP 

77 

Spartan - 6 

LX150T 

User FPGA 

Dataflow 

data 

Manager 

77 

DM 

GTP 

GTP 

data 

data 

data 

data 

data 

data 

data 

data 

data 

data 

data 

data 

High Performance Computing 

DNBFC_S12_12_Cluster 

DDR3 - 800 

DDR3 - 800 

Each line represents 4 GTX 

serial I/O connections 

3.125 GB/s per line 

BFC_S10_PCIe 

PCIe (GEN1) 

4 4 4 4 4 4 

4 4 4 4 

PCIe Fan Out 

Switch 

PCIe Fan Out 

Switch 

8 8 

PCIe 

QPI 

Xeon 

(CPU2) 

Xeon 

(CPU1) 

2 GB DDR3 

2 GB DDR3 

2 GB DDR3 

2 GB DDR3 

2 GB DDR3 

2 GB DDR3 

Platform 

Controller 

Hub 

(3420) 

6 

LAN 1 

10/100/1000 base-T 

LAN 2 

USB 0 

USB 1 

Video (XGI) 

HDD 

Up to 6 HDD (SATA 3) 

Features 

• 5U Rackmount Chassis containing: 

- 1 Intel Xeon E3-1275 processor card 

- 12 DNBFC_S12_PCIe FPGA cards each with 13 Xilinx of the 

largest Spartan-6 FPGAs (XC6SLX150) 

• PCIe 4-lane (GEN1) 

• 156 FPGAs in total, 100% dedicated to application 

- Other configurations with different CPU to FPGA ratios are available 

- 2 bays for SATA-3 hard drives 

• Processor card 

- Intel Xeon E3-1200 series (Sandy Bridge) processors, 3.4 GHz 

• Quad-Core, 8MB shared L2 cache 

• 4 GB DDR3 memory (4 GB total) 

- Options up to 32 GB (32 GB max) 

• VGA with standard D-Sub connector 

• 10/100/1000BASE-T Ethernet (2 ports) 

• USB 2.0 (4 ports total) 

- 2 ports on front panel 

- 2 ports on back bracket 

• Supports most all Linux distributions 

The DNBFC_S12_12_Cluster is a complete, 5U rack mount FPGA acceleration 

cluster. The standard configuration contains the following: 

Trenton TSB7053 Xeon processor card 

12 DNBFC_S12_PCIe Spartan-6 FPGA cards with 13 LX150 FPGAs per card. 

2 TB SATA II Hard Drive 

This system contains the maximum number of cost effective FPGA that 

can be reasonability integrated into a 5U chassis. Power and cooling are 

the constraining variables. High performance data paths between FPGA 

boards enable data movement under algorithmic control that is wholly 

separate from the host processor, enabling FPGA-based acceleration of 

whole new classes of data intensive algorithms. 

In short, the DNBFC_S12_12_Cluster is a massive number of large, 

low cost FPGAs integrated with an excellent dual Xeon-based processor 

host. High speed serial cables between FPGA cards add as much a 5 

GB/s data throughput within the chassis. 

A partial list of possible applications includes: 

Bioinformatics 

Genomic Search 

Financial Analytics 

- Low Latency Analysis 

- Derivative Calculations 

Image Processing 

Signal Processing 

Radar 

Scientific Computing 

Video Compression 

Encryption/Decryption (Cryptography) 

44 

www.dinigroup.com

DNBFC_S12_PCIe 

Expansion 

Cards 

/ 

Board to Board 

Dataflow 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

Top 

Bottom 

QSE 

QSE 

16 

data 

16 

data 

16 

data 

16 

data 

16 

data 

16 

data 

DDR3 - 800 

(128M x 16) 

DDR3 - 800 

(128M x 16) 

data 

16 

data 

16 

GTP 

GTP 

Spartan - 6 

LX150T 

User FPGA 

Dataflow 

Manager 

GTP 

4 4 4 4 

DM 

77 

77 

Spartan - 6 

LX150 


(FGG484) 

64 

Spartan - 6 

LX150 


(FGG484) 

77 

MB (upper) 

MB (lower) 

77 

Spartan - 6 

LX150 


(FGG484) 

8 

8 

64 

Spartan - 6 

LX150 


(FGG484) 

77 

77 

Spartan - 6 

LX150 


(FGG484) 

64 

Spartan - 6 

LX150 


(FGG484) 

77 

77 

Spartan - 6 

LX150 


(FGG484) 

64 

Spartan - 6 

LX150 


(FGG484) 

77 

77 

Spartan - 6 

LX150 


(FGG484) 

64 

Spartan - 6 

LX150 


(FGG484) 

77 

77 

Spartan - 6 

LX150 


(FGG484) 

Spartan - 6 

LX150 


(FGG484) 

64 77 

32 

32 

16 

data 

16 

data 

16 

data 

16 

data 

16 

data 

16 

data 

Config 

EE 

User 

EEPROM 

PCIe 

Bridge 

Q 

4-lane PCIe (GEN1/GEN2) 

DDR3 - 800 

(128M x 16) 

100MHz Clock 


MB Clock 

DDR3 - 800 

(128M x 16) 

JTAG 

0 

DM 

1 2 

11 

10 

3 

9 

4 

5 

8 

6 

7 

DDR3 - 800 

(128M x 16) 

Frequency 

Synthesizer 

31.25 MHz- 

350 MHz 

DDR3 - 800 

(128M x 16) 

CLK A 


DDR3 - 800 

(128M x 16) 

Battery 

Bitstream 

Encryption 

DDR3 - 800 

(128M x 16) 

PCIe 

Features 

• PCI Express (4-lane) FPGA-based algorithm acceleration peripheral 

- 12 of the largest Xilinx Spartan-6 FPGAs: 6SLX150-2 

• 12, 128M x 16 (2Gb) DDR3-800 memories (1 per FPGA) 

- 1 Xilinx Spartan-6 FPGAs: 6SLX150T-2 

• 2, 128M x 16 (2Gb) DDR3-800 memories 

• Fixed 4-lane PCIe interface and controller 

- PCIe GEN1/GEN2 

- Full mastering DMA 

• 2 transmit (host memory -> card) 

• 2 receive (card -> host memory) 

• Xilinx FPGA Spartan-6 LX150-2 – 12 total 

- 184,464 flip-flops per FPGA 

• 92K flips-flops with 6-input LUT 

- 180, 18x18 multipliers + 48-bit accumulator per FPGA 

- 268, 18 Kbit block RAM (603 Kbytes) per FPGA 

• Fully dual-ported 

• Each block RAM configurable as: 

- 16K×1, 8K×2, 4K×4, 2K×8/9, 1K×16/18, or 512 x 32/36 

- Options for LX150-1L (lower power) or LX150-3 (higher frequency) 

• Also LX150T-3,-4 

- Options for LX100, LX75, LX45, LX25 (lower cost) 

• FPGA to FPGA interconnect single-ended 

- Source synchronous FPGA -> FPGA frequency: 150MHz 

• 300 Mb/s per pin when using DDR 

• Main Bus (MB) connects all Spartan-6 FPGAs (8 signals) 

- 90MHz 

• 128Mb x 16 fixed external DDR3 memory dedicated to each field FPGA (12 total) 

• 2 – 128Mb x 16 fixed external DDR3 memories dedicated to USER 

Dataflow Manager FPGA 

- DDR3-800 is stuffed. VCCINT is set to ‘Extended Performance’ operating range: 

• With LX150-2, LX150T-2: 667 Mbps (333.5 MHz) 

Designed for High Performance Computing (HPC) applications, the DNBFC_S12_PCIe is a FPGA-based 

peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost effective 

Xilinx Spartan-6 FPGAs. Data movement to/from the FPGA grid is accomplished via a fixed 4-lane, 

GEN1/GEN2 PCIe bridge. Each Spartan-6 FPGA has its own 128M x 16 DDR3 memory capable of clocked 

speeds up to 400MHz (800 Mb/s per data pin). Two additional 128M x 16 DDR3 memories are connected to 

the USER Dataflow Manager FPGA (LX150T) for bulk data storage. 

- 10.67 Gb/s maximum data rate 

• With LX150-3, LX150T-3,LX150T-4: 800 Mbps (400 MHz) 

- 12.8 Gb/s maximum data rate 

- Full support for FPGA memory block controller (MBC) 

• Up to 8 open banks 

• Configurable multi-port interface to FPGA fabric 

- 32-, 64-, or 128-bit data bus 

• Easy implementation with Xilinx CORE Generator 

• Expansion via high speed, low-power GTP transceivers (LX150T) 

- 3.125 Gb/s per lane, each direction with -3 or -4 (TX and RX) 

- 2.7 Gb/s per lane, each direction with -2 (TX and RX) 

- 4 lanes (4 RX and 4 TX) for daisy chain left 

- 4 lanes (4 RX and 4 TX) for daisy chain right 

- Board to board data communication 

• >1 GB/s per connector TX 

• >1 GB/s per connector RX 

• Non-proprietary, off-the-shelf Samtec cable assembly 

- Off-board daughter cards 

• Three independent low-skew global clock networks distributed 

differentially and balanced 

- G0: programmable in 1 MHz increments (ICS84314 clock synthesizer) 

• 32 MHz to 350 MHz 

- G1: 100MHz PCIe reference 

- G2: Main Bus (MB) clock 

• Fast and Painless FPGA configuration via PCIe 

- On-board battery for AES bitstream encryption 

- Unique Device DNA identifier for design authentication 


- ChipScope, and other third-party debug solutions 

• FPGA-controller LEDs 

- Enough for emergency lighting in a small parking structure 

858 . 454 . 3419 45

IP - TCP Offload (TOE) 

FIX Data Stream 

10GbE Ethernet 

Input to Output 

10GbE packet latency 

IP - PCIe (Gen1,2,3) Slowdown 

PCIe Clock Slowdown 

Pin Multiplexing 

FPGA 0 FPGA 1 

Logic 

data 

D 

SET 

Q 

data 

data 

SET 

D Q 

data 

Logic 

CLR Q 

DATA_P/N[18:0] 

CLR 

Q 

DNLVDS_PINMUX_TX 

DNLVDS_PINMUX_RX 

clock 

clock 

CLK_SS_P/N 

MMCM 

System clock 

MMCM 

Overview 

CLK 

Oscillator 

The Dini Group LVDS IO Pin Multiplexing design (DNLVDS_PINMUX) is intended to ease the 

strain of prototyping an ASIC design that spans multiple FPGAs by providing a low-latency IO 

pin multiplexing design. A latency of one clock cycle is achievable end-to-end, so the multiplexing 

essentially becomes invisible to the ASIC design. IO rates are maximized to allow for the highest 

internal frequency possible. Eye detection training and real-time eye monitoring are implemented 

inside the receiver module. 

858 . 454 . 3419 47

DINI GROUP | 7469 Draper Ave. La Jolla, CA 858.454.3419 | www.dinigroup.com | sales@dinigroup.com

FPGA Boards - The Dini Group

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