FPGA Boards - The Dini Group

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LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) LED (x4) Config PROM Frequency Synths (Si5326) Frequency Synths (Si5326) Frequency Synths (Si5326) COMPACT FLASH FPGA CONFIGURATION Stratix IV DN7020K10 +1.5V to +3.3V I/O DC0 MEG Array Expansion Connector (400-pin) DIMM_F1 DDR2 SODIMM (4GB max) DIMM_F2 DDR2 SODIMM (4GB max) DIMM_F3 DDR2 SODIMM (4GB max) +1.5V to +3.3V I/O DC2 MEG Array Expansion Connector (400-pin) MICTOR Boot EPROM RS232 serial port SMA SMA SMA SMA 12 12 12 62 24 61 190 120 120 120 190 SPI Flash SPI Flash SPI Flash (16Mb) (16Mb) (16Mb) Stratix IV 50 Stratix IV 51 Stratix IV 50 Stratix IV 50 Stratix IV FPGA F0 FPGA F1 FPGA F2 FPGA F3 FPGA F4 50 4SE820 4SE820 62 24 61 62 24 61 62 24 61 184 188 186 48 48 48 48 48 48 46 50 44 51 46 50 46 4SE820 4SE820 4SE820 50 51 50 50 51 50 48 48 48 48 48 48 138 140 138 48 48 48 48 48 48 48 48 Stratix IV Stratix IV Stratix IV Stratix IV Stratix IV 38 39 38 38 FPGA F5 FPGA F6 FPGA F7 FPGA F8 FPGA F9 38 39 38 38 4SE820 4SE820 4SE820 4SE820 4SE820 38 48 48 Stratix IV Stratix IV Stratix IV Stratix IV Stratix IV FPGA F10 38 FPGA F11 39 FPGA F12 38 FPGA F13 37 FPGA F14 38 39 38 36 4SE820 4SE820 4SE820 4SE820 4SE820 38 48 48 Stratix IV 50 Stratix IV 50 FPGA F15 FPGA F16 FPGA F17 FPGA F18 FPGA F19 4SE820 4SE820 40 50 40 40 46 Stratix IV 51 Stratix IV 51 Stratix IV 51 51 51 51 4SE820 51 4SE820 51 4SE820 SPI Flash (16Mb) 38 38 50 24 23 24 24 23 24 24 23 24 24 23 24 39 39 SPI Flash (16Mb) 39 39 51 24 23 24 24 23 24 24 23 24 24 23 24 138 140 138 48 48 48 48 48 48 48 48 48 38 38 48 48 48 48 48 48 SPI Flash (16Mb) 38 38 51 24 23 24 24 23 24 24 23 24 24 23 24 140 140 138 48 48 48 48 48 48 50 50 38 36 50 48 48 38 48 48 37 48 48 50 21 21 21 21 21 21 21 21 21 21 21 21 MBUS48B 180 184 180 Bus Switch 47 47 48 48 Bus Switch 47 47 48 48 Bus Switch 47 47 48 48 47 47 48 48 Bus Switch DC3 MEG Array Expansion Connector (400-pin) DC4 MEG Array Expansion Connector (400-pin) DC5 MEG Array Expansion Connector (400-pin) DC6 MEG Array Expansion Connector (400-pin) +1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O +1.5V to +3.3V I/O 34 Main Bus Connector SMA SMA F4 40 40 MICTOR MBUS48A MBUS48B MBCLK GCLK0 (to all FPGA’s) GCLK1 (to all FPGA’s) GCLK2 (to all FPGA’s) DCGCLK0 (to all FPGA’s) CY7C68013 uP Configuration controller SRAM 128Kb x 8 Flash 1 M x 8 Config FPGA 48 MHz 8 LCD Control Panel USB 2.0 (type b) RS232 Reset 96 96 SMA CFPGA Div Clk CFPGA Step Clk FPGA F19 SMA CFPGA Div Clk CFPGA Step Clk FPGA F19 SMA CFPGA Div Clk CFPGA Step Clk FPGA F19 G0 Si5326 FPGA F1 4 Serial Ports (Tx/Rx) MEG Array Expansion Connector (400-pin) SMA PLL DC10 SMA DC0 DC3 +1.5V to +3.3V I/O Features 20 JTAG www.dinigroup.com 0 5 1 6 2 7 10 11 12 13 14 15 16 17 3 8 18 4 9 19 190 120 120 48 DC1 DIMM F16 DIMM F17 MEG Array Expansion Connector (400-pin) +1.5V to +3.3V I/O • USB2.0-hosted logic prototyping system with 2-20 Altera Stratix IV FPGAs - Stratix IV 4SE530 or 4SE820 in high I/O package (FF1760) - Backwards compatible with the Stratix-3, 3SL340 - 100% FPGA resources available for user application • 130M+ ASIC gates (reasonable ASIC measure) with twenty 4SE820s - 82M+ with twenty 4SE530s • FPGA to FPGA interconnect is single-ended or LVDS - 600 MHz LVDS chip-to-chip DDR (1.2 Gb/s) - Reference designs for integrated I/O pad ISERDES/OSERDES • 10x FPGA to FPGA pin multiplexing per LVDS pair • Greatly simplified logic partitioning • Source synchronous clocking for LVDS • Main Busses for global connectivity: - Main Bus A (MBUS48A), all FPGAs: 48 single-ended signals - Main Bus B (MBUS48B), all FPGAs: 48 single-ended signals • Auspy AES models for partitioning assistance - Hooks for other third-party partitioning solutions • 6 separate DDR2 SODIMMs (350MHz) - 64-bit data width, 350MHz operation - PC2-5300 - Addressing/power to support 4GB in each socket - DDR2 Verilog/VHDL reference design provided (no charge) - DDR2 SODIMM data transfer rate: 32Gb/s - Alternate pin compatible memory cards available: • QDR SSRAM, Mictor, RLDRAM I, RLDRAM II, SSRAM, DDR3, DDR1, interconnect, SDRAM DRAM, FLASH, USB PHY, and others • SODIMM Daughtercard expansion - DNSODM200_Mictor - Mictor + 0.1” breakout - DNSODM200_Flash - two 4M x 32 flash chips DDR2 SODIMM (4GB max) DDR2 SODIMM (4GB max) = LVDS when paired, but can be used single-ended at reduced frequency 120 190 DIMM F18 DDR2 SODIMM (4GB max) - DNSODM200_Quadmic - Mictors - More... • 3 board-level global clock networks (GCLK[2:0]) - Separate programmable synthesizers for each network (Si5326) • Ultra-low jitter • 2 kHz – 710 MHz • User configurable via Compact FLASH or USB - Alternate clock sources: • Config FPGA - single-step - Divide • SMA for external clock insertion • 4 Daughter Card global clock networks (DC_GCLK[3:0]). Select from: - Clock from daughter card with PLL for zero-delay (ICS8745B-21) • DC_GCLK0: Select DC0 or DC3 as source • DC_GCLK1: Select DC2 or DC4 as source • DC_GCLK2: Select DC5 or DC7 as source • DC_GCLK3: Select DC1 or DC8 as source - SMA for external clock insertion - Selected FPGA outputs • DC_GCLK0: Select GCLK0 or FPGA1 as source • DC_GCLK1: Select GCLK1 or FPGA8 as source • DC_GCLK2: Select GCLK2 or FPGA13 as source • DC_GCLK3: Select FPGA14 or FPGA13 as source • 8, 400-pin MEG-Array connectors (FCI) for daughter card (DC) expansion - 190 single-ended on DC0,1,2,7 - 47 LVDS pairs (FPGA -> DC), 48 LVDS pairs (DC -> FPGA) on DC[6:3] • Can be used as 190 single ended signals - 600MHz on all signals with LVDS - Reset, presence detect - Supplied power rails (fused): • +12V (24W max) • +5V (10W max) MEG Array Expansion Connector (400-pin) +1.5V to +3.3V I/O DC7 Bus Switch 34 F19 DCGCLK1 (to all FPGA’s) DCGCLK2 (to all FPGA’s) DCGCLK3 (to all FPGA’s) G1 Si5326 FPGA F8 G2 Si5326 FPGA F13 FPGA F13 FPGA F14 • +3.3V (10W max) - Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x) • Fast and Painless FPGA configuration - Compact FLASH, and/or USB - Integrated sanity checks on configuration files - Accelerated configuration readback • Custom base plate (standard) and optional rackmount chassis - Provides protection from those drooling engineers • 4, RS232 ports for embedded uP debug - Accessible from all FPGAs • Full support for embedded logic analyzers via JTAG interface - SignalTap, and other third party tools • Convert a pair of MEG-Array expansion connectors to interconnect with the DNMEG_Intercon. • MEG-Array Daughtercard Expansion - DNMEG_Obs - breakout/observation - DNMEG_Intercon - more interconnect - More... • Enough status LEDs to adequately illuminate a Twisted Sister concert. PLL SMA PLL SMA PLL DC2 DC4 DC5 DC7 DC1 DC6
A B C D F A B C F E D F D FPGA A LED’s FPGA D LED’s 18 11 FPGA B LED’s FPGA E LED FPGA F LED’s FPGA C LED’s DN7406K10PCIe-8T JTAG RJ45 D +1.5V to +3.3V I/O MEG Array Expansion connector (400-pin) +1.5V to +3.3V I/O MEG Array Expansion connector (400-pin) +1.5V to +3.3V I/O MEG Array Expansion connector (400-pin) RJ45 F RS232 2 (bussed) ALL FPGAs 10/100/1000 ETHERNET (VSC8601) 125 MHz 48 48 47 47 48 48 47 47 9 48 48 47 47 125 MHz 125 MHz 10/100/1000 ETHERNET (VSC8601) Config USB 2.0 (480 Mb/s) RS232 Reset COMPACT FLASH config ALL FPGAs Configuration FPGA uP Config Control clock config Ethernet JTAG 16 MB [35:0] config data DDR2 SODIMM (4GB Max) QL5064 122 +2.5V I/O mac addr Flash (24C64) 36 8 User Serial Flash (16 Mbit) 1 17 2 5 FPGA D Stratix 4 4SE820 (FF1760) 62 62 62 62 46 2 clock input 14 9 9 184 9 9 48 48 48 48 x14 FPGA E Stratix 4 4SE820 (FF1760) MB [95:0] 96 9 clock input 1 9 9 clock input 186 9 9 9 9 FPGA F Stratix 4 4SE820 (FF1760) 62 62 62 62 62 62 62 62 46 1 2 5 14 17 mac addr Flash (24C64) 8 User Serial Flash (16 Mbit) x14 122 +2.5V I/O Main Bus Connector DDR2 SODIMM (4GB Max) 114.285MHz FPGA clock sourcing clk_TP single step clock (from config FPGA) clk_G0 from config FPGA 48 MHz 24 MHz 24 MHz 24 MHz Clock Synth Si5326 2Khz to 600MHz 114.285MHz Clock Synth Si5326 2Khz to 600MHz 114.285MHz Clock Synth Si5326 2Khz to 600MHz MB clock clk_G0 (General clocking) clk_G1 (DDR2) clk_G2 (LVDS) clk_MB48 DDR2 SODIMM (4GB Max) QL5064 122 89 89 PCIe Express Endpoint FPGA A Stratix 4 4SE820 (FF1760) (250 MHz) clock input 184 9 9 9 9 3 User Serial Flash (16 Mbit) x3 5 1 FPGA B Stratix 4 4SE820 (FF1760) MICTOR clock input 184 x11 clock input 45 User Serial Flash (16 Mbit) 45 45 45 21 1 21 5 21 21 FPGA C Stratix 4 4SE820 (FF1760) 11 x11 34 122 MICTOR DDR2 SODIMM (4GB Max) Daughter card D clk_EXT0 sma Daughter card F Daughter card E clk_EXT1 PCI Express 8 - lane GEN1 - 2.5 Gb/s (8-lanes) GEN2 - 5.0 Gb/s (4-lanes) = LVDS when paired, but can be used single-ended at reduced frequency Features PCIe endpoint clk_ref Global Clocks to all FPGA’s • PCI Express (8-lane) logic prototyping system with 2-6 Altera Stratix-4 FPGAs - EP4SE820-3, -2 (slowest to fastest) - EP4SE530-3, -2 • FF1760 package: 1,120 I/Os (with 4SE820) • Fixed 8-lane PCIe interface and controller provided - PCIe GEN1 rev 1.1 - PCIe GEN2 with upgrade • 40+ million ASIC gates (ASIC measure) when stuffed with 6 Stratix-4 4SE820s • FPGA to FPGA interconnect is a mix of single-ended and LVDS - 600 MHz LVDS chip to chip (1.2 Gb/s) - LVDS pairs can be used as two single-ended signals at reduced frequency (~225MHz) - Reference designs for integrated I/O pad ISERDES/OSERDES - 10x pin multiplexing per LVDS pair - Greatly simplified logic partitioning - Source synchronous clocking for LVDS • Main Bus (MB) connects all Stratix-4 FPGAs (96 signals) - Single-ended • Auspy models for partitioning assistance • 4 separate DDR2 SODIMMs (350MHz) - Direct connection to FPGAs A, C, F, D - PC2-4200 or better - Addressing/power to support 4GB in each socket - DDR2 Verilog/VHDL reference design provided (no charge) - DDR2 SODIMM data transfer rate: 32Gb/s - Alternate pin compatible memory cards available (consult factory for availability): • SRAM: QDR, ASYNC, STD, or PSRAM, FLASH • DRAM: SDR, DDR1, PSRAM or RLDRAM, DDR3 • Mictor, USB PHY, Extra Interconnect • Seven independent low-skew global clock networks - G0, G1, G2, M48, EXT0, EXT1, REF - Three, high-resolution, user-programmable synthesizers for G0, G1, G2 - User configurable via CompactFLASH, USB, and/or PCIe - All seven global clocks networks distributed differentially and balanced • Two independent single-step clocks - Seven independent external clocks inputs (single-ended or differential) can be injected onto low-skew global clock networks Stratix IV FPGA Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (100% util) (1000's) Practical (60% util) (1000's) • Flexible customization via daughter cards using expansion connectors - 3 daughter card locations: FPGAs D, E, F - 400-pin FCI MEG-Array connectors - 93 LVDS unidirectional pairs + clocks (or 186 single-ended) - 450MHz on all signals with source synchronous LVDS - Signal voltage set by daughter card (1.2v to 3.3V) - Reset - Supplied power rails (fused): • +12v (24W max) • +5V (10W max) • +3.3V (10W max) - Pin multiplexing to/from daughter cards using LVDS (up to 10x) • Fast and Painless FPGA configuration - CompactFLASH, USB, PCIe, JTAG - Configuration Error reporting - Accelerated configuration readback • RS232 port for embedded uP debug - Accessible from all FPGAs via separate 2-signal bus • Full support for embedded logic analyzers via JTAG interface - SignalTap, and other third-party debug solutions • 54 status FPGA-controller LEDs: bright enough to illuminate airplane landing strips Max I/O's MLAB (640) M9K (9 kbit) M144K (144 kbit) Total (kbits) Total (kbytes) 4SE820 -4,-3 6-input 656,000 10,496 6,508 1120 960 16261 1610 60 23,130 2,891 4SE530 -4,-3,-2 6-input 424,960 6,799 4,080 960 1024 10624 1280 64 20,736 2,592 Multipliers (18x18) Memory 858 . 454 . 3419 21
Page 1 and 2: April 2013 v5.0 FPGA Boards ASIC Pr
Page 3 and 4: WHO, WHAT, WHERE, WHY? Who are you?
Page 5 and 6: HOSTING THE LARGEST FPGA EVER! USB
Page 7 and 8: four Virtex-7 FPGAs | 7V2000T-1 | 5
Page 9 and 10: two Virtex-7 FPGAs | 7V2000T-1 | 28
Page 11 and 12: single Virtex-7 FPGA | 7V2000T-1 |
Page 13 and 14: SMA SMA SMA SMA SMA SMA SMA SMA SMA
Page 15 and 16: dual Altera Stratix V FPGAs | 5SGXA
Page 17 and 18: single Xilinx Kintex-7 FPGA | QDRII
Page 19: single Xilinx Kintex-7 FPGA | QDRII
Page 23 and 24: Alternate Memory: 200-pin SODIMM SO
Page 25 and 26: DNV6F2PCIe JTAG A DDR3 SODIMM (4GB
Page 27 and 28: DN-DualV6-PCIe-4 from FPGA A from F
Page 29 and 30: Specialty 204-pin SODIMM DNSODM204_
Page 31 and 32: DINAR1 Daughter Cards DINAR1_SOC 18
Page 33 and 34: DINAR1 Daughter Cards | DNNMB DINAR
Page 35 and 36: SMA DNMEG Daughter Cards DNMEG_SODI
Page 37 and 38: 114.285 MHZ 114.285 MHZ 114.285 MHZ
Page 39 and 40: DNIOB: High Speed Serial Interfaces
Page 41 and 42: SEAM Expansion DNSEAM_IPASSx4 Add 4
Page 43 and 44: DNK7_F5PCIe PC3-800 DDR3 (256M DDR3
Page 45 and 46: DNBFC_S12_PCIe Expansion Cards / Bo
Page 47 and 48: IP - PCIe (Gen1,2,3) Slowdown PCIe

FPGA Boards - The Dini Group

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