HY3118/HY3116 Datasheet

HY3118/HY3116
24-Bit Analog-to-Digital Convert
High Resolution Σ∆ADC
5. Register List
5.1. Register List
Register
Byte
Address Name 7 6 5 4 3 2 1 0
SYS - APO IRQEN ENADC ENLDO ENREFO ENOP -
000h Read/Write - R/W R/W R/W R/W R/W R/W -
Initial Status - 0 0 0 0 0 0 -
ADC1 - - INP[2] INP[1] INP[0] INN[2] INN[1] INN[0]
001h Read/Write - - R/W R/W R/W R/W R/W R/W
Initial Status - - 0 0 0 0 0 0
ADC2 VRPS[1] VRPS[0] VRNS[1] VRNS[0] DCSET[3] DCSET[2] DCSET[1] DCSET[0]
010h Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Status 0 0 0 0 0 0 0 0
ADC3 OSCS[1] OSCS[0] FRb PGA[2] PGA[1] PGA[0] ADGN[1] ADGN[0]
011h Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Status 0 0 0 0 0 0 0 0
ADC4 LDO[1] LDO[0] REFO HS OSR[2] OSR[1] OSR[0] -
100h Read/Write R/W R/W R/W R/W R/W R/W R/W -
Initial Status 0 0 0 0 0 0 0 -
ADOH
ADOH
Read/Write R R R R R R R R
Initial Status 0 0 0 0 0 0 0 0
ADOM
ADOM
101h Read/Write R R R R R R R R
Initial Status 0 0 0 0 0 0 0 0
ADOL ADOL ADST
Read/Write R R R R R R R R
Initial Status 0 0 0 0 0 0 0 0
“-”unused, “R/W”read/write, “R”read only, “”keep as 0
Table 2 Register List
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DS-HY3118- V08_EN
Page 10