Version 04

HY16F188 

Datasheet 

. 

High Precision Mixed-Signal Controller 

Embedded 65nV Resolution ADC 

32-bit Low Power MCU 

64K Byte Flash 

© 2013 HYCON Technology Corp 

www.hycontek.com 

DS-HY16F188-V06_EN

HY16F188 

21-Bit ENOB Σ∆ADC 

32-Bit MCU and 64 KB Flash 

Table of Content 

1. Features ..........................................................................................................................4 

2. Pin Definition....................................................................................................................5 

2.1 Introduction ................................................................................................................5 

2.2 Pin Name List.............................................................................................................9 

3. Application Circuit ..........................................................................................................19 

3.1 Bridge Sensor ..........................................................................................................19 

3.2 Blood Pressure Sensor ............................................................................................20 

3.3 Electrochemical Sensor ...........................................................................................21 

3.4 Touch Key Sensor ....................................................................................................22 

4. Function Outline.............................................................................................................23 

4.1 Internal Block Diagram.............................................................................................23 

4.2 Building Block Diagram ............................................................................................24 

4.3 Supporting Document ..............................................................................................24 

4.4 Clock System Network .............................................................................................25 

4.5 Power System Network............................................................................................26 



. 

4.6Σ∆ADC Network........................................................................................................27 

4.7 Rail to Rail OPAMP Network ....................................................................................28 

4.8 DAC Network ...........................................................................................................29 

4.9 Analog Comparator Network ....................................................................................30 

4.10 Watch Dog Timer Network .....................................................................................31 

4.11 Timer A Network .....................................................................................................32 

4.12 Timer B Network.....................................................................................................33 

4.13 Timer C Network ....................................................................................................34 

4.14 32-bit SPI Diagram.................................................................................................35 

4.15 UART Block Diagram .............................................................................................36 

4.16 I2C Block Diagram .................................................................................................37 

4.17 Hardware RTC Block Diagram ...............................................................................37 

4.18 GPIO Port Function Configuration..........................................................................38 

5. Ordering Information......................................................................................................39 

6. Package Information......................................................................................................40 

6.1 LQFP48 PKG Diagram.............................................................................................40 

6.2 QFN33 PKG Diagram ..............................................................................................41 

7. Electrical Characteristics ...............................................................................................42 

7.1 Recommended Operating Conditions ......................................................................42 

7.2 Clock System ...........................................................................................................43 

7.3 Power Management System ....................................................................................44 

DS-HY16F188-V06_EN 

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HY16F188 



7.4 Reset Management System.....................................................................................45 

7.5 Σ∆ADC ENOB and RMS Noise................................................................................45 

7.6 ADC Management System.......................................................................................48 

7.7 Temperature sensor .................................................................................................49 

7.8 DAC Management System.......................................................................................49 

7.9 OPA Management System .......................................................................................50 

7.10 CMP Management System ....................................................................................51 

8. Revision History.............................................................................................................51 

. 




page3

HY16F188 



1. Features 

Digital Circuit 

• 32-bit MCU 1T Andes Core N801 

• C Complier & User Friendly Development Tools 

• 2.2V to 3.6V operational voltage. 

• -40 to 85℃ operational environment 

• Low power operation: 

• MCU: 350uA/MIPS@3.3V 

• Low speed mode: 10uA@35KHz/2&3.3V 

• Sleep mode: 2.5uA@3.3V 

• 64K Byte Flash ROM 

• 8K Byte SRAM 

• 16-bit PWM controller 

• I2C/SPI/ UART communication Hardware IP 

• RTC Hardware IP 

• Low voltage detection/BOR circuit 

• Programmable Digital I/O Ports 

. 

Analog Circuit 

• An ultra low noise 24-bit SD ADC 

• Down to 65nVrms input refer noise 

• Conversion rate up to 350KSPS 

• Input amplification gain up to 128 

• Operation voltage 2.4V to 3.6V 

• External High Speed Oscillator Max 20MHz 

• External Low Speed Oscillator Mode 32768Hz 

• Internal High Speed Oscillator Max 20MHz 

• Internal Low Speed Oscillator 35KHz 

• Power management 

• Charge Pump regulation 

• Build-in selectable VDDA voltage LDO 

• 1.2V Band gap reference output 

• A 8-bit resistor ladders can be used as 8-bit DAC 

• Programmable potentiometer 

• Monotonic guarantee 

• A rail-to-rail operation amplifier 

• CMOS input, 1MHz bandwidth 

• Unit Gain Buffer, Integrator 

• S/H circuit, software SAR ADC 

• Can use as comparator 

• Multi-function Analog Comparator 

• Support touch key 

MCU 

Core 

Flash 

ROM 

SRAM 

24-bit 

Σ∆ADC 

I/O 

16-bit 

PWM 

HW 

RTC 

8-bit 

DAC 

OP 

AMP 

Analog 

CMP 

Hardware 

Communication 

UART SPI I 2 C 

TPS 

Sensor 

Package 

HY16F184 16KB 2KB 4-CH 19 2-CH 1 1 1 1 1 1 1 Y 

LQFP48 

QFN33 

HY16F187 32KB 4KB 4-CH 19 2-CH 1 1 1 1 1 1 1 Y 

LQFP48 

QFN33 

HY16F188 64KB 8KB 4-CH 25 2-CH 1 1 1 1 1 1 1 Y LQFP48 




page4

HY16F188 



2. Pin Definition 

2.1 Introduction 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

37 

PT2.4 

PT2.5 

PT2.6 

PT2.7 

VDD18 

NC 

VDD3V 

CP_O 

CH 

CL 

CP_I 

VSS 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

NC 

PT4.0/RST 

NC 

PT2.3 

PT2.2 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

48 47 46 45 44 43 42 41 40 39 38 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

HY16F188 

LQFP48 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

NC 

NC 

PT3.7 

EDIO 

VPP 

PT1.0 

PT1.1 

PT1.2 

PT1.3 

PT1.4 

PT1.5 

PT1.6 

PT1.7 

NC 

NC 

. 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

Figure 2-1 HY16F188 LQFP48 Pin Diagram 




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HY16F188 



36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

37 

PT2.4 

PT2.5 

PT2.6 

PT2.7 

VDD18 

NC 

VDD3V 

NC 

NC 

NC 

NC 

VSS 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

NC 

PT4.0/RST 

NC 

48 47 46 45 44 43 42 41 40 39 38 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

HY16F187 

HY16F184 

LQFP48 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

NC 

NC 

PT3.7 

EDIO 

VPP 

PT1.0 

PT1.1 

PT1.2 

PT1.3 

PT1.4 

PT1.5 

PT1.6 

PT1.7 

NC 

NC 

NC 

NC 

NC 

NC 

. 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

Figure 2-2 HY16F187/184 LQFP48 Pin Diagram 




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HY16F188 



PT2.5 

PT2.6 

PT2.7 

VDD18 

VDD3V 

VSS 

VPP 

PT4.0 

32 

31 

30 

29 

28 

27 

26 

25 

PT1.0 

PT1.1 

1 

2 

33 VSS PIN 

24 

PT2.4 

23 PT3.0 

PT1.2 

PT1.3 

3 

4 

HY16F184 

HY16F187 

22 

PT3.1 

21 PT3.2 

PT1.4 

PT1.5 

5 

6 

QFN33 

20 

PT3.3 

19 PT3.4 

PT1.6 

PT1.7 

7 

8 

. 

18 

PT3.5 

17 PT3.6 

9 

10 

11 

12 

13 

14 

15 

16 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

PT3.7 

EDIO 

ECK 

Figure 2-3 HY16F187/184 QFN33 Pin Diagram 




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HY16F188 



Function Priority: 

GPIO Port OSC Interrupt 

Timer C 

Timer B 

SPI IIC UART CMP Analog 

Capture 

PWM 

Priority 0 0 0 1 2 3 4 5 6 

PT1.0 INT1.0 TCI1_1 CS_1 SCL_1 TX_1 CH1 PWM0_1 

PT1.1 INT1.1 TCI2_1 CK_1 SDA_1 RX_1 CH2 PWM1_1 

PT1.2 INT1.2 TCI1_2 MISO_1 SCL_2 TX_2 CH3 PWM0_2 

PT1.3 INT1.3 TCI2_2 MOSI_1 SDA_2 RX_2 CL1 PWM1_2 

PT1.4 INT1.4 TCI1_3 CS_2 SCL_3 TX_3 CL2 PWM0_3 

PT1.5 INT1.5 TCI2_3 CK_2 SDA_3 RX_3 CL3 PWM1_3 

PT1.6 INT1.6 TCI1_4 MISO_2 SCL_4 TX_4 CL4 PWM0_4 

PT1.7 INT1.7 TCI2_4 MOSI_2 SDA_4 RX_4 CMPO1 PWM1_4 

PT2.0 INT2.0 TCI1_5 CS_3 SCL_5 TX_5 PWM0_5 

PT2.1 INT2.1 TCI2_5 CK_3 SDA_5 RX_5 PWM1_5 

PT2.2 INT2.2 TCI1_6 MISO_3 SCL_6 TX_6 PWM0_6 

PT2.3 INT2.3 TCI2_6 MOSI_3 SDA_6 RX_6 PWM1_6 

PT2.4 LSXT1 INT2.4 TCI1_7 CS_4 SCL_7 TX_7 PWM0_7 

PT2.5 LSXT2 INT2.5 TCI2_7 CK_4 SDA_7 RX_7 PWM1_7 

PT2.6 HSXT1 INT2.6 TCI1_8 MISO_4 SCL_8 TX_8 PWM0_8 

PT2.7 HSXT2 INT2.7 TCI2_8 MOSI_4 SDA_8 RX_8 PWM1_8 

PT3.0 

OPO1 

PT3.1 OPO2 DAO 

PT3.2 

AIO4 

PT3.3 

AIO5 

PT3.4 

AIO6 

PT3.5 

AIO7 

PT3.6 

. 

REFO 

PT3.7 

OPO 

PT4.0 

RST 

AIO0 

AIO0 

AIO1 

AIO1 

AIO2 

AIO2 

AIO3 

AIO3 




page8

HY16F188 



2.2 Pin Name List 

2.2.1 HY16F188 LQFP48 

PIN TYPE (1) NAME DESCRIPTION 

1 NC NC Not connect 

2 PI VPP Reserve (can’t connect to any pin) 

3 IO 

PT4.0 Digital Input/ Output Pin 

I 

4 IO 

AI 

I 

O 

I 

IO 

I 

IO 

5 IO 

AI 

I 

O 

I 

I 

I 

IO 

6 IO 

AI 

I 

O 

I 

IO 

I 

IO 

7 IO 

AI 

I 

O 

O 

I 

I 

IO 

8 IO 

AI 

I 

O 

I 

IO 

I 

IO 

RST 

PT1.0 

CH1 

INT1.0 

PWM0_1 

CS_1 

TX_1 

TCI1_1 

SCL_1 

PT1.1 

CH2 

INT1.1 

PWM1_1 

CK_1 

RX_1 

TCI2_1 

SDA_1 

PT1.2 

CH3 

INT1.2 

PWM0_2 

MISO_1 

TX_2 

TCI1_2 

SCL_2 

PT1.3 

CL1 

INT1.3 

PWM1_2 

MOSI_1 

RX_2 

TCI2_2 

SDA_2 

PT1.4 

CL2 

INT1.4 

PWM0_3 

CS_2 

TX_3 

TCI1_3 

SCL_3 

Reset IC PIN 

Digital Input/ Output PIN 

Comparator Analog Input PIN 

Interrupt Source INT1.0 

PWM0_1 Output PIN 

SPI Communication Interface PIN CS_1 

EUART Communication Interface PIN TX_1 

Timer C Capture Module PIN TCI1_1 

I2C Communication Interface PIN SCL_1 





SPI Communication Interface PIN CK_1 

EUART Communication Interface PIN RX_1 


. 

I2C Communication Interface PIN SDA_1 





SPI Communication Interface PIN MISO_1 








SPI Communication Interface MOSI_1 

EUART Communication Interface RX_2 

Timer C Capture Module PIN TC12_2 






SPI Communication Interface CS_2 

EUART Communication Interface TX_2 






page9

HY16F188 




9 IO 

AI 

I 

O 

I 

I 

I 

IO 

PT1.5 

CL3 

INT1.5 

PWM1_3 

CK_2 

RX_3 

TCI2_3 

SDA_3 









10 IO 

AI 

I 

O 

I 

IO 

I 

IO 

11 IO 

AO 

I 

O 

O 

I 

I 

IO 

PT1.6 

CL4 

INT1.6 

PWM0_4 

MISO_2 

TX_4 

TCI1_4 

SCL_4 

PT1.7 

CMPO1 

INT1.7 

PWM1_4 

MOSI_2 

RX_4 

TCI2_4 

SDA_4 

Digital Input/Output PIN 









Comparator Analog Output PIN 



SPI Communication Interface PIN MOSI_2 




12 NC NC Not Connect 

13 I ECK Embedded . Debug Module (EDM) Clock Input PIN 

14 IO EDIO Embedded Debug Module (EDM) Data Input/ Output PIN 

15 IO 

AO 

PT3.7 

OPO1 


RAIL-TO-RAIL OPAMP Output PIN 



18 PIO VDDA Analog Power Supply, LDO Output, or Analog Power Input 

19 AI AIO0 Analog Input Signal Port 0 




23 IO 

PIO 

PT3.6 

REFO 


Analog Reference Voltage 



26 IO 

AI 

PT3.5 

AIO7 


Analog Input Signal Port 7 

27 IO 

AI 

PT3.4 

AIO6 



28 IO 

AI 

PT3.3 

AIO5 






page10

HY16F188 




29 IO 

AI 

PT3.2 

AIO4 


Analog input signal port 4 

30 IO 

DO 

AO 

PT3.1 

OPO2 

DAO 


RAIL-TO-RAIL OPAMP Output 

DAC Output 

31 IO 

PT3.0 Digital Input/ Output PIN 

DO 

32 IO 

I 

O 

I 

IO 

I 

IO 

33 IO 

I 

O 

I 

I 

I 

IO 

34 IO 

I 

O 

I 

IO 

I 

IO 

35 IO 

I 

O 

O 

I 

I 

IO 

OPO1 

PT2.0 

INT2.0 

PWM0_5 

CS_3 

TX_5 

TCI1_5 

SCL_5 

PT2.1 

INT2.1 

PWM1_5 

CK_3 

RX_5 

TCI2_5 

SDA_5 

PT2.2 

INT2.2 

PWM0_6 

MISO_3 

TX_6 

TCI1_6 

SCL_6 

PT2.3 

INT2.3 

PWM1_6 

MOSI_3 

RX_6 

TCI2_6 

SDA_6 


37 IO 

XI 

I 

O 

I 

IO 

I 

IO 

PT2.4 

LS_XIN 

INT2.4 

PWM0_7 

CS_4 

TX_7 

TCI1_7 

SCL_7 



Interrupt Source INT 2.0 

















. 












LS_XIN 










page11

HY16F188 




38 IO 

XO 

I 

O 

I 

I 

I 

IO 

PT2.5 

LS_XOUT 

INT2.5 

PWM1_7 

CK_4 

RX_7 

TCI2_7 

SDA_7 


LS_XOUT 







39 IO 

XI 

I 

O 

I 

IO 

I 

IO 

PT2.6 

HS_XIN 

INT2.6 

PWM0_8 

MISO_4 

TX_8 

TCI1_8 

SCL_8 


HS_XIN 







40 IO 

XO 

I 

O 

O 

I 

I 

IO 

PT2.7 

HS_XOUT 

INT2.7 

PWM1_8 

MOSI_4 

RX_8 

TCI2_8 

SDA_8 


HS_XOUT 







41 PO VDD18 Digital Power Supply. LDO Output 1.8V 


43 PI VDD3V Power Input For System 

44 PO CP_O Charge Pump 3V Out 

45 PIO CH Charge Pump Capacitor High Voltage Plate 

46 PIO CL Charge Pump Capacitor Low Voltage Plate 

47 PI CP_I Charge Pump Power Input 

48 P VSS Power Ground Pad 

. 

Table 2-1 HY16F188 LQFP48 Pin Definition and Function description 

(1)TYPE Definition: 

I = Digital Input 

O = Digital Output 

OD = Open-drain Output 

AI = Analog Input 

AO = Analog Output 

P = Power Connection 




page12

HY16F188 



2.2.2 HY16F187/184 LQFP48 




3 IO 

PT4.0 Digital Input/ Output Pin 

I 

4 IO 

AI 

I 

O 

I 

IO 

I 

IO 

5 IO 

AI 

I 

O 

I 

I 

I 

IO 

6 IO 

AI 

I 

O 

I 

IO 

I 

IO 

7 IO 

AI 

I 

O 

O 

I 

I 

IO 

8 IO 

AI 

I 

O 

I 

IO 

I 

IO 

RST 

PT1.0 

CH1 

INT1.0 

PWM0_1 

CS_1 

TX_1 

TCI1_1 

SCL_1 

PT1.1 

CH2 

INT1.1 

PWM1_1 

CK_1 

RX_1 

TCI2_1 

SDA_1 

PT1.2 

CH3 

INT1.2 

PWM0_2 

MISO_1 

TX_2 

TCI1_2 

SCL_2 

PT1.3 

CL1 

INT1.3 

PWM1_2 

MOSI_1 

RX_2 

TCI2_2 

SDA_2 

PT1.4 

CL2 

INT1.4 

PWM0_3 

CS_2 

TX_3 

TCI1_3 

SCL_3 

Reset IC PIN 





















. 
























page13

HY16F188 




9 IO 

AI 

I 

O 

I 

I 

I 

IO 

PT1.5 

CL3 

INT1.5 

PWM1_3 

CK_2 

RX_3 

TCI2_3 

SDA_3 









10 IO 

AI 

I 

O 

I 

IO 

I 

IO 

11 IO 

AO 

I 

O 

O 

I 

I 

IO 

PT1.6 

CL4 

INT1.6 

PWM0_4 

MISO_2 

TX_4 

TCI1_4 

SCL_4 

PT1.7 

CMPO1 

INT1.7 

PWM1_4 

MOSI_2 

RX_4 

TCI2_4 

SDA_4 


















13 I ECK Embedded . Debug Module (EDM) Clock Input PIN 


15 IO 

AO 

PT3.7 

OPO1 










23 IO 

PIO 

PT3.6 

REFO 





26 IO 

AI 

PT3.5 

AIO7 



27 IO 

AI 

PT3.4 

AIO6 



28 IO 

AI 

PT3.3 

AIO5 






page14

HY16F188 




29 IO 

AI 

PT3.2 

AIO4 



30 IO 

DO 

AO 

PT3.1 

OPO2 

DAO 



DAC Output 

31 IO 

DO 

PT3.0 

OPO1 






37 IO 

XI 

I 

O 

I 

IO 

I 

IO 

38 IO 

XO 

I 

O 

I 

I 

I 

IO 

39 IO 

XI 

I 

O 

I 

IO 

I 

IO 

40 IO 

XO 

I 

O 

O 

I 

I 

IO 

PT2.4 

LS_XIN 

INT2.4 

PWM0_7 

CS_4 

TX_7 

TCI1_7 

SCL_7 

PT2.5 

LS_XOUT 

INT2.5 

PWM1_7 

CK_4 

RX_7 

TCI2_7 

SDA_7 

PT2.6 

HS_XIN 

INT2.6 

PWM0_8 

MISO_4 

TX_8 

TCI1_8 

SCL_8 

PT2.7 

HS_XOUT 

INT2.7 

PWM1_8 

MOSI_4 

RX_8 

TCI2_8 

SDA_8 




LS_XIN 








LS_XOUT 








HS_XIN 








HS_XOUT 















Table 2-2 HY16F187/184 LQFP48 Pin Definition and Function description 

. 




page15

HY16F188 



2.2.3 HY16F187/184 QFN33 


1 IO 

AI 

I 

O 

I 

IO 

I 

IO 

PT1.0 

CH1 

INT1.0 

PWM0_1 

CS_1 

TX_1 

TCI1_1 

SCL_1 









2 IO 

AI 

I 

O 

I 

I 

I 

IO 

3 IO 

AI 

I 

O 

I 

IO 

I 

IO 

4 IO 

AI 

I 

O 

O 

I 

I 

IO 

5 IO 

AI 

I 

O 

I 

IO 

I 

IO 

PT1.1 

CH2 

INT1.1 

PWM1_1 

CK_1 

RX_1 

TCI2_1 

SDA_1 

PT1.2 

CH3 

INT1.2 

PWM0_2 

MISO_1 

TX_2 

TCI1_2 

SCL_2 

PT1.3 

CL1 

INT1.3 

PWM1_2 

MOSI_1 

RX_2 

TCI2_2 

SDA_2 

PT1.4 

CL2 

INT1.4 

PWM0_3 

CS_2 

TX_3 

TCI1_3 

SCL_3 

















. 




















page16

HY16F188 




6 IO 

AI 

I 

O 

I 

I 

I 

IO 

PT1.5 

CL3 

INT1.5 

PWM1_3 

CK_2 

RX_3 

TCI2_3 

SDA_3 









7 IO 

AI 

I 

O 

I 

IO 

I 

IO 

PT1.6 

CL4 

INT1.6 

PWM0_4 

MISO_2 

TX_4 

TCI1_4 

SCL_4 









8 IO 

AO 

I 

O 

O 

I 

I 

IO 

PT1.7 

CMPO1 

INT1.7 

PWM1_4 

MOSI_2 

RX_4 

TCI2_4 

SDA_4 









9 I ECK Embedded Debug Module (EDM) Clock Input PIN 


11 IO 

AO 

PT3.7 

OPO1 








17 IO 

PIO 

18 IO 

AI 

19 IO 

AI 

20 IO 

AI 

PT3.6 

REFO 

PT3.5 

AIO7 

PT3.4 

AIO6 

PT3.3 

AIO5 

. 












page17

HY16F188 




21 IO 

AI 

PT3.2 

AIO4 



22 IO 

DO 

AO 

PT3.1 

OPO2 

DAO 



DAC Output 

23 IO 

PT3.0 Digital Input/ Output PIN 

DO 

24 IO 

XI 

I 

O 

I 

IO 

I 

IO 

25 IO 

XO 

I 

O 

I 

I 

I 

IO 

26 IO 

XI 

I 

O 

I 

IO 

I 

IO 

27 IO 

XO 

I 

O 

O 

I 

I 

IO 

OPO1 

PT2.4 

LS_XIN 

INT2.4 

PWM0_7 

CS_4 

TX_7 

TCI1_7 

SCL_7 

PT2.5 

LS_XOUT 

INT2.5 

PWM1_7 

CK_4 

RX_7 

TCI2_7 

SDA_7 

PT2.6 

HS_XIN 

INT2.6 

PWM0_8 

MISO_4 

TX_8 

TCI1_8 

SCL_8 

PT2.7 

HS_XOUT 

INT2.7 

PWM1_8 

MOSI_4 

RX_8 

TCI2_8 

SDA_8 



LS_XIN 








LS_XOUT 








HS_XIN 

Interrupt Source . INT 2.6 







HS_XOUT 











32 IO 

I 

PT4.0 

RST 

Digital Input/ Output Pin 

Reset IC PIN 


Table 2-3 HY16F187/184 QFN33 Pin Definition and Function description 




page18

HY16F188 



3. Application Circuit 

3.1 Bridge Sensor 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

NC 

PT2.3 

37 

48 47 46 45 44 43 42 41 40 39 38 

PT2.2 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

NC 

1~10uF 

1~10uF 

100K 

100nF 

VDD3V 

MSCL 

MSDA 

PT2.4 

PT2.5 

PT2.6 

PT2.7 

VDD18 

NC 

VDD3V 

CP_O 

CH 

CL 

CP_I 

VSS 

HY16F188 

LQFP48 

NC 

1 

VPP 

2 

PT4.0/RST 

3 

PT1.0 

4 

PT1.1 

5 

PT1.2 

6 

PT1.3 

7 

ADC 

REFN 

AIO3 

. 

PT1.4 

PT1.5 

8 9 

AIO0 

INP 

INN 

AIO1 

REFP 

AIO2 

PT1.6 

PT1.7 

NC 

10 11 12 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

NC 

NC 

PT3.7 

EDIO 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

0.1uF 

0.1uF 

1uF 

10k 

10k 

MSCL 

MSDA 

VDD3V 

D- 

SCL 

SDA 

VDD 

VDDA 

COM 

AIO2 

D+ 

AIO3 

SEG 

HY2613 

TSSOP48 

℃ 

℉ 

VLCD 

VR 

VSS 

Figure 3-1 Bridge Sensor Circuit 




page19

HY16F188 



3.2 Blood Pressure Sensor 

DC motor 

Electromagnetic 

valve 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

NC 

PT2.3 

PT2.2 

VBAT 

VBAT 

1K 

1K 

PWM2 

PWM1 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

NC 

VDDA 

1~10uF 

1~10uF 

VBAT 

100K 

VDD3V 

1uF 

10uF 

MSCL 

MSDA 

37 

48 47 46 45 44 43 42 41 40 39 38 

PT2.4 

PT2.5 

PT2.6 

PT2.7 

VDD18 

NC 

VDD3V 

CP_O 

CH 

CL 

CP_I 

VSS 

HY16F188 

LQFP48 

NC 

1 

VPP 

2 

PT4.0/RST 

3 

PT1.0 

4 

PT1.1 

5 

PT1.2 

6 

PT1.3 

7 

ADC 

REFN 

AIO3 

PT1.4 

PT1.5 

8 9 

INP 

INN 

REFP 

AIO2 

. 

PT1.6 

PT1.7 

NC 

10 11 12 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO0 AIO1 

AIO0 

AIO1 

VDDA 

NC 

NC 

PT3.7 

EDIO 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

0.1uF 

0.1uF 

1uF 

10k 

10k 

MSCL 

Pressure sensor 

4 

5 

S- 

6 

GND 

COM 

SEG 

SCL 

S+ 

GND 

℃ 

℉ 

VLCD 

3 

2 

1 

4.7K 

AIO3 

AIO0 

AIO2 

100nF 

MSDA 

VDD3V 

SDA 

VDD 

HY2613 

TSSOP48 

VR 

VSS 

Figure 3-2 Blood Pressure Sensor Circuit 




page20

HY16F188 



3.3 Electrochemical Sensor 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

NC 

PT2.3 

PT2.2 

37 

48 47 46 45 44 43 42 41 40 39 38 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

NC 

1~10uF 

1~10uF 

VDD3V 

100K 

MSCL 

MSDA 

PT2.4 

PT2.5 

PT2.6 

PT2.7 

VDD18 

NC 

VDD3V 

CP_O 

CH 

CL 

CP_I 

VSS 

HY16F188 

LQFP48 

NC 

1 

Control 

unit 

DAC 

VPP 

2 

PT4.0/RST 

3 

PT1.0 

4 

ADC 

INP 

INN 

REFN REFP 

VSS REFO 

PT1.1 

PT1.2 

PT1.3 

5 6 7 

AIO2 

AIO3 

PT1.4 

8 

AIO5 

PT1.5 

. 

0.2V 

9 

OPA 

PT1.6 

PT1.7 

10 11 

NC 

12 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

NC 

NC 

PT3.7 

EDIO 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

1K 

10K 

27pF 

Low Pass Filter 

1uF 

10k 

10k 

Vopo=0.4V 

0.2V 

I 

Rstrip 

10K 

℃ 

℉ 

COM 

SEG 

VLCD 

MSCL 

SCL 

100nF 

MSDA 

VDD3V 

SDA 

VDD 

HY2613 

TSSOP48 

VR 

VSS 

Figure 3-3 Electrochemical Sensor Circuit 




page21

HY16F188 



3.4 Touch Key Sensor 

36 

35 

34 

33 

32 

31 

30 

29 

28 

27 

26 

25 

NC 

37 

PT2.3 

48 47 46 45 44 43 42 41 40 39 38 

PT2.2 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

PT3.4 

PT3.5 

PT2.4 

VDD18 

NC 

VDD3V 

CP_O 

CH 

CL 

CP_I 

VSS 

NC 

NC 

1~10uF 

1~10uF 

VDD3V 

100K 

PT2.5 

PT2.6 

PT2.7 

MCO 

ENMC[0] 

HY16F188 

LQFP48 

1 

CMP 

VPP 

2 

PT4.0/RST 

3 

RLO 

MCH0 

PT1.0 

4 

I/O 

P15 

P14 

P13 

P12 

PT1.1 

5 

VDD3 

. 

PT1.2 

6 

NE0 NE1 

PT1.3 

7 

CPCLS[1:0] 

11 

10 

01 

00 

DTMB_CK 

MCNEC[0] 

PT1.4 

8 

MCL3 

MCL2 

MCL1 

MCL0 

I/O 

I/O 

I/O 

I/O 

PT1.5 

9 

PT1.6 

10 

PT1.7 

11 

NC 

12 

NC 

REFO/PT3.6 

AIO3 

AIO2 

AIO1 

AIO0 

VDDA 

NC 

NC 

PT3.7 

EDIO 

ECK 

24 23 22 21 20 19 18 17 16 15 14 13 

10k 

10k 

100nF 

100nF 

Touch PAD 

Figure 3-4 Touch Key Sensor Circuit 




page22

HY16F188 



4. Function Outline 

4.1 Internal Block Diagram 

UART 

32-bit SPI 

I2C 

PT1.0 

PT1.1 

PT1.2 

8KB 

SRAM 

64KB 

Flash 

N8 

32-bit MCU 

Debug 

Module 

Power 

Management 

PT1.3 

PT1.4 

Watch Dog 

Reset Control 

PT1.5 

Low Noise 

PGA 

24-bit ADC 

Analog 

Comparator 

PT1.6 

PT3.4 

PT1.7 

PT3.5 

ECK 

EDIO 

PT3.7/OPO 

VDDA 

AIO0 

AIO1 

VSS 

CP_I 

CL 

CH 

VDD18 

PT2.1 

PT2.0 

PT3.0 

PT3.1 

PT3.2 

PT3.3 

AIO2 

AIO3 

CP_O 

VDD3V 

PT2.7/LXOUT 

PT2.6/LXIN 

PT2.5/XIN 

PT2.4/XOUT 

VPP 

PT2.3 

RST/PT4.0 

Hardware 

RTC 

Clock System 

TimerA/B/C 

16-bit PWM 

PT2.3 

. 

Rail-to-Rail 

OPAMP 

Bandgap 

8-bit DAC 

Charge Pump 

PT3.6 

Figure 4-1 Internal Block Diagram 




page23

HY16F188 



4.2 Building Block Diagram 

To AICE 

2-wire JATG 

EDM 

32-bit N801 Core 

8K Byte 

Boost ROM 

64K Byte 

Flash ROM 

Instruction 

Fetch 

Load/Store 

Unit 

8K Byte 

SRAM 

Bus Interface Unit 

. 

APB 

Digital 

IP 

Analog 

IP 

Sensor 

IP 

Communication 

IP 

Figure 4-2 Build Block Diagram 

4.3 Supporting Document 

NO File Name Description 

1 DS-HY16F188 HY16F188 Data Sheet 

2 UG-HY16F188 HY16F188 Users’ Manual 

3 APD-HY16IDE001 HY16F188 IDE Software Manual 

4 APD-HY16IDE002 HY16F188 IDE Hardware Manual 




page24

HY16F188 



4.4 Clock System Network 

HSXT Enable(ENOHS) 

2~20MHz 

EN_HAO 

HAO[1:0] 

HAOTR[7:0] 

32.768KHz 

CKS 

HSXT 

2 ~20MHz 

HSRC 

2/4/10/20M 

Hz 

LSXT Enable(ENOLS) 

LSXT 

32.768KHz 

LSRC 

34KHz 

HSXT 

HSRC 

LSXT 

LSRC 

CKHS 

1 

0 

CKLS 

1 

0 

HS_CK 

MCUCKS 

0 

1 

LS_CK 

ENMCD 

Pre-scale 

1,2 

ENACD 

MCCK 

APCK 

ADCD[1:0] 

CPU 

APB 

LSXT 

LSRC 

0 

1 

CKS 

ENRTCK 

HS_CK 

Pre-scale 

6,12,30,60 

ADCK 

ADC 

APCK 

0 

1 

ENSD 

RTCDV 

128 

RTCK 

SPCD[2:0] 

RTC 

. 

LSRC 

Pre-scale 

256 

WDCK 

WDT 

APCK 

Pre-scale 

1,2,4, 

~2048 

SPCK 

32-bit 

SPI 

TACKS 

ENTAD 

HSXT 

HSRC 

TUCKS 

0 

1 

ENUD 

Pre-scale 

1,2,4, 

~128 

UACD[3:0] 

URCK 

UART 

HS_CK 

LS_CK 

0 

1 

Pre-scale 

32 

TACK 

Timer A 

APCK 

ENI2C 

Pre-scale 

1,2,4, 

~128 

TOPS[2:0] 

I2CK 

I2C 

HS_CK 

LS_CK 

TMCKS 

0 

1 

ENTD TMCD[1:0] 

Pre-scale 

1,2,4,8 

TBCK 

Timer B 

Timer C 

ENAD 

IOCKS 

IOCD[3:0] 

ADCK 

ADCKo 

0 

1 

CHPCK 

Pre-scale 4 

(internal used only) 

Charge 

Pump 

HS_CK 

LS_CK 

0 

1 

Pre-scale 

1,2,4, 

~16384 

IOCK 

PTIO 




page25

HY16F188 



4.5 Power System Network 

10uF 

CP_I 

CL 

1uF 

CH 

10uF 

VDD3V 

CP_O 

CPCLK 

Charge Pump 

ENCHP 

VDDLP 

1.8V 

VDD18 

1uF 

VDD3V 

ENVA[1:0] 

VDDA 

VDDA 

VDAS[1:0] 

=2.4/2.7/ 

3.0/3.3 V 

10uF 

VDDA 

ENRFO 

Bandgap 

Reference 

Voltage 

BGR 

REFOI 

REFO 

Buffer 

REFO 

0.1uF 

ENBGR || ENVA ==3 

VDDA 

Buffer 

ACMS 

. 

0 

1 

To ADC ACM 

Short:when PT3IE[6]==0 

Open:when PT3IE[6]==1 




page26

HY16F188 



4.6ΣΔADC Network 

ADINP[3:0] 

AIO0 

AIO1 

AIO2 

AIO3 

REFO 

OPO 

TSP0 

TSP1 

DAOI 

VDDA 

AIO0 

AIO1 

AIO2 

AIO3 

REFO 

OPO 

TSN0 

TSN1 

DAOI 

VSS 

0000 

0001 

0010 

0011 

0100 

0101 

0110 

0111 

1000 

1001 

0000 

0001 

0010 

0011 

0100 

0101 

0110 

0111 

1000 

1001 

INP 

VISHR 

INN 

ADINN[3:0] 

A 

PGA[2:0] 

PGA 

X 1,8,16,32 

B 

VRPS[1:0] 

DCSET[3:0] 

00 

V 

D 

D 

A 

01 

. 

A 

I 

O 

2 

ADGN x1,2,3,4 

2 order SD ADC 

REFP 

10 

A 

I 

O 

4 

VREF x 0.5,1 

11 

R 

E 

F 

O 

VRSHR 

00 

ADGN[1:0] 

ADCLK 

FRb 

ENADC 

ADFDR 

V 

S 

S 

A 

1bit 

REFN 

01 

A 

I 

O 

3 

10 

A 

I 

O 

5 

11 

R 

E 

F 

O 

Comb Filter 3 

CFRST 

OSR 

32bit 

VRNS[1:0] 

ADO[31:0] 




page27

HY16F188 



4.7 Rail to Rail OPAMP Network 

AIO2 

AIO4 

DAOI 

REFO 

AIO3 

AIO5 

OPPS[0] 

OPPS[1] 

OPPS[2] 

OPPS[3] 

OPNS[0] 

OPNS[1] 

ENOP 

+ 

R2ROP 

- 

OPOE 

OPOI 

OPCS 

OPO 

2us 

Delay 

OPDFR 

0 

1 

OPDEN 

OPOR 

0 

1 

OPOD/ 

OPOIF 

CHPCK 

OPOS 

0 

1 

OPO1/OPO2 

DAOI 

OPO 

OPOI 

OPNS[2] 

OPNS[3] 

OPNS[4] 

OPOC 

10pF 

1 

0 

OPOI 

VSSA 

OPOC 

OPNS[5] 

. 




page28

HY16F188 



4.8 DAC Network 

DAPS[1:0] 

ENDA 

VDD3V 

000 

VDDA 

REFO 

001 

010 

DA_Vrefp 

DABIT[7:0] 

OPO 

011 

AIO6 

100 

256 

Mux 

DAOE 

Internal 

DAO 

PT3.1 

DAO 

PT31DAO 

VSS 

REFO 

OPO 

AIO7 

00 

01 

10 

11 

DA_Vrefn 

. 

DABIT[7:0] 

0X00 

0X01 

DABIT 

1/256 

2/256 

0XFE 

254/256 

DANS[1:0] 

0XFF 

255/256 




page29

HY16F188 



4.9 Analog Comparator Network 

CP_I 

VDD3V 

CPRLH 

VDD18 

OFF 

CPRH[2:0] 

Hysteresis 

CPDM CMPO Divider 

0000 

0001 

0001 

0010 

0010 

0011 

0011 

X 

1 

0 

1 

0 

1 

0 

CPDA[3:0] 

CPDA[3:1],1 

CPDA[3:1],0 

CPDA[3:2],1,CPDA[0] 

CPDA[3:2],0,CPDA[0] 

CPDA[3:2],11 

CPDA[3:2],00 

CPNS[1:0] 

CL1 

CL2 

CL3 

CL4 

CPCLS[1:0] 

00 

01 

10 

11 

CPRLH 

ENCLIN 

Non-overlap 

CL3 

Clock Gen 

TBCLK 

22.5R 

CPDA[3:0] 

CPDM[3:0] 

CH1 

CH2 

00 

01 

CH1 

16R 

16 

R_DA 

Mux 

RLO 

CH3 

10 

11 

- 

ENCMP 

CPDF 

CPOR 

CPRL 

CPRLL 

20R 

CMPO 

CH1 

00 

CPIS 

+ 

2uS 

0 

Mux 

1 

0 

Mux 

1 

CMPO 

CMPIF 

CH2 

CH3 

01 

10 

. 

CMPHS 

V12 

11 

CPPS[1:0] 




page30

HY16F188 



4.10 Watch Dog Timer Network 

CWDT( ) 

Reset Signal 

Clear Counter 

WDT[2:0] 

ENWDT 

WDT_CK 

FWDT 

WDT 

Programmable Scaler 

Set TO on Overflow 

WDT[2:0] 

WDT_Scalar[14:0] 

000 FWT/2 

Non-mask-able 

Interrupt 

001 FWT/8 

010 

011 

100 

FWT/32 

FWT/128 

FWT/512 

WDT Interrupt 

101 

FWT/2048 

110 FWT/8192 

WDNMI 

111 FWT/32768 

. 




page31

HY16F188 



4.11 Timer A Network 

ENTA 

TMAR STOP 

Sleep( ) 

TACLR 

TMAS[3:0] 

TACK 

TMAR[15:0] 

TMA 

Overflow 

TMAIF 

Interrupt 

TMAS[3:0] 

TMAR[15:0] 

0000 TACK/2 

0001 TACK/4 

: : 

1110 TACK/32768 

. 

1111 TACK/65536 




page32

HY16F188 



4.12 Timer B Network 

CLR_TMB 

ENTMB 

PWM0_Mode[2:0] 

PWM_PORT[2:0] 

TMBR[15:8] TMBR[7:0] 

Comparator 

TMBC0[15:0] 

TMBC1_PWM[15:0] 

TMBC2_PWM[15:0] 

TBM_Mode[1:0] 

TMB 

Interrupt 

TMBIF 

PWMA 

PWMB 

PWMC 

PWMD 

PWME 

PWMF 

PWMG 

PWMG 

000 

001 

010 

011 

100 

101 

110 

111 

PWM0_INV 

PWM0 1 

0 

ENPWM0_PT 

000 

001 

010 

011 

100 

101 

110 

111 

PT1.0 

PT1.2 

PT1.4 

PT1.6 

PT2.0 

PT2.2 

PT2.4 

PT2.6 

TBM_00 

00 

PWM1_Mode[2:0] 

PWM_PORT[2:0] 

TBM_01 

TBM_10 

TBM_11 

Logic High 

CMPO 

OPODIG 

CPI1 

01 

10 

11 

00 

01 

10 

11 

TBCLK 

000 

PWMA 

001 

PWMB 

010 

PWMC 

011 

PWMD 

100 

PWME 

101 

PWMF 

PWMG 

PWMG 

. 

110 

111 

PWM1_INV 

PWM1 1 

0 

ENPWM1_PT 

000 

001 

010 

011 

100 

101 

110 

111 

PT1.1 

PT1.3 

PT1.5 

PT1.7 

PT2.1 

PT2.3 

PT2.5 

PT2.7 

TBEBS[1:0] 




page33

HY16F188 



4.13 Timer C Network 

CMPO 

OPOD 

LS_CK 

00 

01 

10 

CPI1 

TimerC 

Frequency 

Divider 

1 

0 

TMC0IF 

EN TMC 

TCR0[15:0] 

TCI1 

11 

CP1PS[3:0] 

CPI1P 

TBR[15:0] 

CPSS 

CPI1S[1:0] 

From GPIO TMCI2 

1 

0 

1 

0 

TMC1IF 

TCR1[15:0] 

TMC_PORT[2:0] 

TMC_PORT[2:0] 

CPI2P 

PT1.0 

PT1.2 

PT1.4 

PT1.6 

PT2.0 

PT2.2 

PT2.4 

PT2.6 

000 

001 

010 

011 

100 

101 

110 

111 

TMCI1 

PT1.1 

PT1.3 

PT1.5 

PT1.7 

PT2.1 

PT2.3 

PT2.5 

PT2.7 

000 

001 

010 

011 

100 

101 

110 

111 

. 

TMCI2 

CP1PS[3:0] CPI1 Divider 

0000 CPI1÷1 

0001 CPI1÷2 

: : 

1110 CPI1÷16384 

1111 CPI1÷32768 




page34

HY16F188 



4.14 32-bit SPI Diagram 

Master 

Slave 

MSBit LSBit MSBit LSBit 

SDIx SDO 

shift register 

MISO 

shift register 

SDOx 

MISO 

SDI 

Read 

Buffer 

Write 

Buffer 

SPI 

Controller 

SPI Clock 

Generator 

SCKx 

SCK 

CSx 

. 

CS 

SPI 

Controller 




page35

HY16F188 



4.15 UART Block Diagram 

EUART TRANSMIT BLOCK DIAGRAM 

ENSP[0] 

Enable EUART 

Exclusive OR 

PARITY[0] 

XOR 

8 

Data Bus 

8 

TXREG Register 

TX9D[0] 

TX9D 

TX9[0] 

ENADD[0] 

1 0 

TXIE[0] 

Interrupt 

TXIF 

ENTX[0] 

(8) (7) ………… 0 

MSB TSR Register 

LSB 

Buffer 

and 

Control 

TX pin 

BRGRH BRGRL 

Baud Rate Generator 

TRMT[0] 

EUART 8-BITs RECEIVE BLOCK DIAGRAM 

. 

ENCR[0] 

OERR[0] 

OERR[0] 

ENSP[0] 

Enable EUART 

RC pin 

ENSP[0] 

Pin Buffer 

and Control 

BRGRH BRGRL 

Baud Rate Generator 

Data 

Recover 

Stop 

PARITY[0] 

PERR[0] 1 

7 ………… 1 

RSR Register 

Exclusive OR 

XOR 

8 

0 Start 

Interrupt 

RXIF[0] 

Overflow 

RXIE[0] 

RXREG Register 

8 

FIFO 

1 Don care PERR[0] state of 8-bits receive mode 

Data Bus 




page36

HY16F188 



4.16 I2C Block Diagram 

SCL 

SDA 

Master 

Slave 

TX Ctrl 

ENI2C 

TOPS[2:0] 

APCK 

Pre-scale 

1,2,4, 

…,128 

I2CCK 

Clock 

Generator 

Register 

Time-out 

Ctrl 

Intetnal 

System Bus 

4.17 Hardware RTC Block Diagram 

RTKEY 

RTCEN 

RTINS 

RTCO 

Digital Compensation 

Controller 

. 

RTPT 

LSRC 

LSXT 

0 

1 

Pre-Scalar 

Input/256 

Secondary Scalar 

/128 

MUX 

RTPTF 

Periodic Timer 

Interrupt Mux 

RTLPYF 

Time Format (BCD) 

Year/Month/Day/WDay 

Time Format (BCD) 

Hour/Min/Sec 

RTPTF 

RTTAF 

RTWUF 

RCAFEN 

Alarm 

RTTAF 

RTWUEN 




page37

HY16F188 



4.18 GPIO Port Function Configuration 

GPIO Port OSC Interrupt 

Timer C 

Timer B 

SPI IIC UART CMP Analog 

Capture 

PWM 

Priority 0 0 0 1 2 3 4 5 6 

PT1.0 INT1.0 TCI1_1 CS_1 SCL_1 TX_1 CH1 PWM0_1 

PT1.1 INT1.1 TCI2_1 CK_1 SDA_1 RX_1 CH2 PWM1_1 

PT1.2 INT1.2 TCI1_2 MISO_1 SCL_2 TX_2 CH3 PWM0_2 

PT1.3 INT1.3 TCI2_2 MOSI_1 SDA_2 RX_2 CL1 PWM1_2 

PT1.4 INT1.4 TCI1_3 CS_2 SCL_3 TX_3 CL2 PWM0_3 

PT1.5 INT1.5 TCI2_3 CK_2 SDA_3 RX_3 CL3 PWM1_3 

PT1.6 INT1.6 TCI1_4 MISO_2 SCL_4 TX_4 CL4 PWM0_4 

PT1.7 INT1.7 TCI2_4 MOSI_2 SDA_4 RX_4 CMPO1 PWM1_4 

PT2.0 INT2.0 TCI1_5 CS_3 SCL_5 TX_5 PWM0_5 

PT2.1 INT2.1 TCI2_5 CK_3 SDA_5 RX_5 PWM1_5 

PT2.2 INT2.2 TCI1_6 MISO_3 SCL_6 TX_6 PWM0_6 

PT2.3 INT2.3 TCI2_6 MOSI_3 SDA_6 RX_6 PWM1_6 

PT2.4 LSXT1 INT2.4 TCI1_7 CS_4 SCL_7 TX_7 PWM0_7 

PT2.5 LSXT2 INT2.5 TCI2_7 CK_4 SDA_7 RX_7 PWM1_7 

PT2.6 HSXT1 INT2.6 TCI1_8 MISO_4 SCL_8 TX_8 PWM0_8 

PT2.7 HSXT2 INT2.7 TCI2_8 MOSI_4 SDA_8 RX_8 PWM1_8 

PT3.0 

OPO1 

PT3.1 OPO2 DAO 

PT3.2 

AIO4 

PT3.3 

AIO5 

PT3.4 

. 

AIO6 

PT3.5 

AIO7 

PT3.6 

REFO 

PT3.7 

OPO 

PT4.0 

RST 

AIO0 

AIO0 

AIO1 

AIO1 

AIO2 

AIO2 

AIO3 

AIO3 




page38

HY16F188 



5. Ordering Information 

Device No. 1 

Shipment 

Package 

Package 

Unit Material 

Pins 

Code 2 Packing 

Type 

Drawing 

Q’ty Composition 

Type 

MSL3 

HY16F188-D000 Die - D 000 - - 200 Green 4 - 

HY16F188-L048 LQFP 48 L 048 - Tray 250 Green 4 MSL-3 



HY16F187-N033 QFN 33 N 033 - Tray 490 Green 4 MSL-3 

HY16F184-N033 QFN 33 N 033 - Tray 490 Green 4 MSL-3 

1 

Device No.: Model No. – Package Type Description 

EXYou request in LQFP 48package. 

The device No. will be HY16F188-L048. 

And please clearly indicate the shipment packing type when placing orders. 

3 

MSL: 

The Moisture Sensitivity Level ranking conforms to IPC/JEDEC J-STD-020 industry standard categorization. 

The products are processed, packed, transported and used with reference to IPC/JEDEC J-STD-033. 

4 Green (RoHS & no Cl/Br): 

HYCON products are Green products that compliant with RoHS directive and are 

Halogen free (Br/Cl

HY16F188 



6. Package Information 

6.1 LQFP48 PKG Diagram 

Package Outline Drawing--- LQFP 7X7 48L Unit: mm 

. 

Note: 

(1)All dimensions refer to JEDEC OUTLINE MS-026. 

(2)Do not include Mold Flash or Protrusions. 




page40

HY16F188 



6.2 QFN33 PKG Diagram 

Package Outline Drawing--- QFN 5X5 33 Unit: mm 

PIN33=VSS 

D 

D2 

25 32 

PIN 1 

MARK 

24 

1 

E 

E2 

17 

8 

A1 

A3 

16 

e 

b 

9 

L 

. 

A 

SYMBOLS MIN NOM MAX 

A 0.70 0.75 0.80 

A1 0.00 0.02 0.05 

A3 

0.20 REF. 

b 0.18 0.25 0.30 

D 

5.00 BSC 

E 

5.00 BSC 

D2 3.10 3.20 3.30 

E2 3.10 3.20 3.30 

L 0.35 0.40 0.45 

e 

0.50 BSC 

Note: All dimensions refer to JEDEC OUTLINE MO-220. 




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HY16F188 



7. Electrical Characteristics 

Absolute maximum ratings over operating free-air temperature (unless otherwise noted) 

Voltage applied at VDD3V to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 4.0 V 

Voltage applied to any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to V DD3V + 0.3 V 

Diode current at any device terminal. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . ±2 mA 

Storage temperature, Tstg: (Unprogrammed device) . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . .−55℃ to 150℃ 

(Programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ………………………………… .. −40℃ to 85℃ 

Soldering Temperature (10 Sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ….. . .+260°C 

Maximum output current sink by any PORT1 to PORT3 I/O PIN . . . . . . . . . . . . . . . . . . . . . . . . …. . . . . .10mA 

This is a stress rating only and functional operation of the device at these or any other conditions above those 

indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating 

conditions for extended periods of time may affect reliability. 

7.1 Recommended Operating Conditions 

VDD3V=2.2V to 3.6V.T A =-40℃~85℃,Unless otherwise noted. 

Parameter Sym. Test Conditions Min. Typ. Max. Unit 

Supply Voltage VDD3V 2.2 3.6 V 

Supply Current 

I LDO+BOR -25% 2.0 +25% 

VDD3V = 2.2V to 3.6V. 

-25% 2.5 +25% 

I LDO+BOR+LPO 

. 

Power–Up Delay t PU,DLY Wake up from deep sleep 64 ms 

uA 




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HY16F188 



7.2 Clock System 

Typical values are at TA=25℃ and VDD3V= 3.0V.Unless otherwise noted. 

Sym. Parameter Test Conditions Min. Typ. Max. Unit 

2MHz 1.8 2 2.2 MHz 

High Speed Oscillator 

4MHz 3.6 4 4.4 MHz 

FXHS 

frequency 

10MHz 8.5 10 11.5 MHz 

20MHz 17 20 23 MHz 

IXHS High Speed Oscillator Current F XHS = 16MHz 100 uA 

DXHS Duty of High Oscillator 40 60 % 

TLXHS Temperature Trim Step 8MHz 0.25 ppm 

TRXHS Temperature Trim Range 8MHz -64 +63 LSB 

FXMS 

Middle Speed 

Oscillator frequency 

VDD18 = 1.8V 2 12 MHz 

IXMS Middle Speed Oscillator Current F XHS = 4MHz 25 uA 

DXMS Duty of Middle Oscillator 40 60 % 

TLXHS Temperature Trim Step 8MHz 0.25 ppm 

TRXHS Temperature Trim Range 8MHz -64 +63 LSB 

FXLS Low Speed Oscillator frequency VDD18 = 1.8V 32.768 KHz 

. 

IXLS Low Speed Oscillator Current 2 uA 

DXLS Duty of Low Speed Oscillator 40 60 % 

F HAO = 2MHz, before trim -10% 2 +10% MHz 

Internal High Speed 


FHAO 




Voltage Coefficient VDD3V = 2.2V ~3.6V -0.2 +0.2 % 

THAO Temperature Coefficient -40~85 -1.5 +1.5 % 

Internal High Speed 

F HAO = 2MHz 20 uA 

IHAO 

Oscillator Current F HAO = 20MHz 60 uA 

DHAO Duty of Oscillator 40 60 % 

WTHAO Wake up time F HAO = 2MHz 30 us 

FLPO 

Internal Low Speed 


VDD3V= 3.0V -10% 32 +10% KHz 

Voltage Coefficient VDD3V= 2.2V ~3.6V -2.5 +2.5 % 

TLPO Temperature Coefficient -40~85 -2.5 +2.5 % 

Internal Low Speed 

ILPO 

0.35 0.7 uA 

Oscillator Current 

DLPO Duty of Low Speed Oscillator 40 60 % 




page43

HY16F188 



7.3 Power Management System 

Typical values are at TA=25℃ and VDD3V = 3.0V. Unless otherwise noted. 


Coarse Bandgap Reference 

Operation Voltage 1.6 3.6 V 

Output Voltage VDD3V=3.0V 1.05 1.2 1.35 V 

Bandgap Performance 

Operation Voltage 1.7 1.8 V 

Output Voltage VDD3V=3.0V 1.15 1.2 1.25 V 

Temperature Coefficient 50 ppm/°C 

Start up Time 40 ms 

VDDA LDO 

Output Voltage Error -5% 5 % 

Capacitor Loading 22 10,000 nF 

Settling Time 

Capacitor loading = 100nF, 

99% of VDDA 

50 us 

Operation Current 

Bias + Band gap + 

VDDA LDO 

35 50 uA 

Dropout Voltage I=10mA 0.2 V 

Voltage Coefficient VDD3V= 2.5 ~ 3.6V `0.1 %/V 

VDDA voltage 1 2.4 V 




. 

@10Hz, Vpp = 300mV, 

VDDX Power Rejection Gain 

80 dB 

VDD3V=3.3V, VDDA=2.4V 

Temperature Coefficient By using BRG VDDA=3.0V 100 ppm/°C 

VDD18 LDO 

Output Voltage 1.7 1.8 1.9 V 

Capacitor Loading 100 10,000 nF 

Maxim Current VDD18=1.8V,VDD3V=2.5V 10 mA 

Voltage Coefficient VDD3V= 2.2 ~ 3.6V 1 %/V 

Temperature Coefficient 100 ppm/°C 

Load Regulation Load = 0.1~10mA 0.1 V/A 

Dropout voltage Load=10mA 0.2 V 

REFO Buffer 

Capacitor Loading 100 1000 pF 

Operation Current 15 uA 

Input Resistance 100uA push and pull 5 20 Ω 

Output Current 1% change voltage 0.25 1 mA 

Temperature Coefficient By using BRG VDDA=3.0V 80 ppm/°C 

Offset Voltage REFO = 1.2V 3 12 mV 

PSRR @100Hz -80 dB 

Noise BW 1~100Hz 1 V/√Hz 




page44

HY16F188 



7.4 Reset Management System 

Reset Management System = (Brownout/External RST Pin/Low Voltage Detect) 


Sym. Parameter Test Conditions Min. Typ. Max. unit 

Pulse length needed to accepted reset internally, t d-LVR 2 us 

V DD3V Start Voltage to accepted reset internally (LH),V LVR 1.8 1.95 2.1 V 

BOR Ta=-40℃~85℃ -0.50 +50 mV 

Hysteresis, V HYS-LVR 30 mV 

BOR Minimum operation voltage 1.2 V 

Minimum operation Slew Rate 0.1 V/us 

POR 

Start Voltage to accepted reset 0.6 V 

7.5 Σ∆ADC ENOB and RMS Noise 

Typical values are at TA=25℃ and VDD3V = 3.3V, VDDA=2.4V unless otherwise noted. 

HY16F188 provides important input noise specification that aims at Σ∆ADC. Table 7.5-1 and Table 7.5-2 lists 

out the relations of typical noise specification, Gain, Output rate, and maximum input voltage of single end. 

Test condition configuration and external input signal short, voltage reference: 1.2V and 1024 records were 

sampled. 

. 

ENOB(RMS) with OSR/GAIN at A/D Clock=333Khz, VDDA=2.4V, VREF=1.2V 

OSR 

32 64 128 256 512 1024 2048 4096 8192 16384 32768 

Max. Vin(mV) 

=0.9*VREF (1) Output rate(HZ) 

10417 5208 2604 1302 651 326 163 81 41 20 10 

Gain = PGA × ADGN 

±1080 1 = 1 × 1 12.5 15.0 16.6 17.3 17.7 18.1 18.7 19.2 19.6 20.3 20.7 

±540 2 = 1 × 2 12.4 14.4 16.3 16.9 17.0 17.4 17.9 19.1 19.3 20.0 20.4 

±135 4 = 1 × 4 12.2 14.6 16.1 16.6 16.9 17.2 17.9 18.8 19.4 19.8 20.3 

±33.75 32 = 8 × 4 12.2 13.7 15.1 15.6 16.1 16.5 17.0 17.7 18.1 18.6 19.1 

±16.875 64 = 16 × 4 12.1 13.8 14.6 15.2 15.6 16.2 16.7 17.2 17.6 18.1 18.5 

±11.25 96 = 24 × 4 12.1 13.4 14.4 14.8 15.4 15.9 16.4 16.9 17.4 17.9 18.3 

±8.435 128 = 32 × 4 12.0 13.3 14.1 14.7 15.1 15.6 16.1 16.6 17.1 17.6 18.1 

(1) Max.Vin (mV) is the max. input voltage of single end to ground (VSS). 

Table 7.5-1Σ∆ADC ENOB Table 

RMS Noise(uV) with OSR/GAIN at A/D Clock=333Khz, VDDA=2.4V, VREF=1.2V 

OSR 

32 64 128 256 512 1024 2048 4096 8192 16384 32768 

Max. Vin(mV) 

Output rate(HZ) 

=0.9*VREF 

10417 5208 2604 1302 651 326 163 81 41 20 10 

Gain = PGA × ADGN 

±1080 1 = 1 × 1 426.3 71.0 23.3 14.56 10.92 8.29 5.72 3.98 2.95 1.89 1.410 

±540 2 = 1 × 2 216.6 54.1 14.5 9.93 9.37 7.17 4.77 2.19 1.89 1.12 0.838 

±135 4 = 1 × 4 129.5 23.5 8.5 6.04 4.85 4.02 2.46 1.29 0.89 0.65 0.455 

±33.75 32 = 8 × 4 15.8 5.5 2.1 1.53 1.07 0.78 0.56 0.36 0.27 0.18 0.135 

±16.875 64 = 16 × 4 8.5 2.6 1.5 0.99 0.75 0.51 0.36 0.26 0.19 0.13 0.098 

±11.25 96 = 24 × 4 5.9 2.3 1.2 0.85 0.59 0.41 0.30 0.21 0.14 0.10 0.078 

±8.435 128 = 32 × 4 4.6 1.9 1.1 0.71 0.52 0.37 0.27 0.19 0.14 0.10 0.068 

Table 7.5 -2Σ∆ADC RMS Table 




page45

HY16F188 



RMS Noise Diagram 


350 

300 

Gain=1 

Output rate ~ 10sps (OSR:32768) 

6 

4 

Gain=1 


Occurrence 

250 

200 

150 

100 

Output Code (LSB) 

2 

0 

-2 

50 

-4 

0 

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 


LSB base on 21-bit output 

Figure7.5-2(a) RMS Noise Diagram 

-6 

1 201 401 601 801 1001 

Time (reading number) 


Figure7.5-2(b) Output Code Diagram 

Occurrence 

500 

450 

400 

350 

300 

250 

200 

150 

100 

50 

0 


Gain=128 


-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 




. 


8 

6 

4 

2 

0 

-2 

-4 

-6 


Gain=128 


-8 

1 201 401 601 801 1001 




Occurrence 

500 

450 

400 

350 

300 

250 

200 

150 

100 

50 

0 


Gain=128 

Output rate ~ 2.6ksps (OSR:128) 

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 





6 

4 

2 

0 

-2 

-4 


Gain=128 

Output rate ~ 2.6kksps (OSR:128) 

-6 

1 201 401 601 801 1001 







page46

HY16F188 





350 

300 

Gain=1 


8 

6 

Gain=1 


Occurrence 

250 

200 

150 

100 


4 

2 

0 

-2 

-4 

50 

-6 

0 

-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 




-8 

1 201 401 601 801 1001 




. 




page47

HY16F188 



7.6 ADC Management System 

All specifications at TA = –40°C to +85°C, VDDA=REFP=+3V, REFN=VSSA, and Gain=128, 

Unless otherwise noted. 


Analog Inputs 

Full-Scale Input Voltage 

(AINP – AINN) 

±0.5*VREF/Gain 

V 

Common-Mode 

Input Range 

Gain=1 VSS-0.2 VDDA+0.2 V 

System Performance 

Resolution No Missing Codes 24 Bits 

Internal Oscillator, 

SPEED = High 

80 SPS 

Data Rate 

Internal Oscillator, 

SPEED = Low 

10 SPS 

External Oscillator, 

SPEED = High 

f CLK /61440 

SPS 

External Oscillator, 

SPEED = Low 

f CLK /491520 

SPS 

Digital Filter Settling Time Full Settling 3 Data 

Differential Input, 

15 PPM 

End-Point Fit, G = 64 

Integral Nonlinearity (INL) 

Differential Input, 

15 PPM 

End-Point Fit, G = 128 

Gain Drift Reference Buffer . off 5 ppm/°C 

Normal-Mode Rejection 

fI N = 50/ Internal 

60Hz ±1Hz, OSC 

-70 dB 

f DATA = External 

10SPS OSC 

-80 dB 

Common-Mode Rejection at DC, detla VDDA = 0.1V 80 dB 

Input-Referred Noise 

fDATA = 10SPS 50 nV, rms 

fDATA = 80SPS 140 nV, rms 

Power-Supply Rejection at DC, delta VDDA = 0.1V 80 dB 

Voltage Reference Input 

Voltage Reference Input 

(VREF) 

VREF = REFP – REFN -0.15V VDDA+0.15V V 

Reference Buffer Range 0.9V VDDA-0.2 V 

Reference Buffer Current 30 uA 

Reference Noise 1~100Hz 0.5 1 V/√Hz 




page48

HY16F188 



7.7 Temperature sensor 

Typical values are at TA=25℃ and VDD3V = 3.0V, VDDA=2.4V unless otherwise noted. 


TC S Sensor temperature drift 178 uV/℃ 

KT Absolute Temperature Scale 0°K INBUF[0]=1 -285 ℃ 

TC ERR One point calibrate error temperature Calibration at 25℃ of -40℃~85℃ ±2 ℃ 

Temperature (℃) 

120 

100 

80 

60 

40 

20 

0 

-20 

-40 

-60 

TPS Performance 

Temperature(℃) 

Error(℃) 

-40 -20 0 25 45 65 85 100 

Temperature(℃) 

2.0 

1.5 

1.0 

0.5 

0.0 

-0.5 

-1.0 

-1.5 

-2.0 

Error (℃) 

7.8 DAC Management System 

Figure7.7-1 TPS Performance 

Typical values are at TA=25℃ and VDD3V = 3.0V. unless otherwise noted. 


Resolution Monotonic 8 Bit 

VDDA Power supply 2.2 3.6 V 

VOUT Output range DA output is between VR- and VR+ 0 VDD3V V 

VREFP 

Positive reference 

voltage range 

VREFP > VREFN 0 VDD3V V 

VREFN 

Negative reference 

voltage range 

0 VDD3V V 

RON DAC output switch 

VDD3V = 3.0V, 

200 Ω 

0.5V < DA_OP < VDD3V-0.5V 

VDD3V = 3.0V, 

10 Ω 

0.5V > DA_OP,DA_OP>VDD3V-0.5V 

RRSW Reference voltage switch Vrefp = 2.2V, Vrefn=0V, VDD3V= 3.0V 15 30 Ω 

RLADDE 

R 

One LSB 

resistance ladder 

. 

600 Ω 

INL Integral linearity error VR+ = 2.4V VR-= 0V ±0.5 ±1 LSB 

DNL Differential linearity error VR+ = 2.4V VR-= 0V ±0.5 ±1 LSB 

EOS Offset error VR+ = 2.4V VR-= 0V 1 LSB 




page49

HY16F188 



7.9 OPA Management System 

Typical values are at TA=25℃ and VDD3V = 3.0V. unless otherwise noted. 


VDDA Power supply 2.2 3.6 V 

VOUT Output range 0 VDDA V 

VIN Input common range 0 VDDA V 

IOA OA current Each OA 120 uA 

VDDA = 3.0V, 

IOA_LO Output current loading 0.3V < Output voltage < VDDA-0.3V 

1 mA 

AD 

(push or pull) 

VDDA = 2.2V, 

0.3V < Output voltage < VDDA-0.3V 

0.5 mA 

CLOAD Max output capacitor load 1000 pF 

SR ADC input clock 

Loading R=10K, 

C=100pF, 0.3 -> VDDA-0.3V 

0.6 V/us 

GOPEN Open Loop Ggain Loading C=100pF 120 dB 

UGB Unit Gain Bandwidth Loading C=100pF, 3dB 1000 KHz 

PM Phase Margin Loading C=100pF 68 Deg 

GM Gain Margin VR+ = 2.4V VR-= 0V 18 dB 

VOS Offset error Vin = 1.2V ±5 mV 

Power supply 

rejection ratio 

Vout=1.2V, ∆VDDA . = 100mV, at DC 70 dB 

Common mode 

rejection ratio 

Vout=1.2V, ∆V IN = 100mV, at DC 70 dB 

DFD Digital filter delay VDDA=3.0V 2 us 

PSRR 

CMRR 

CSA Sample capacitor 10 pF 




page50

HY16F188 



7.10 CMP Management System 



I MC 

Operation supply current ENCMP[0]=1, CMPHS[0]=1b 5 

uA 

Low Power Mode ENCMP[0]=1, CMPHS[0]=0b 1 

V IC Common-mode input voltage 0 VDD3V-1 V 

V OS Offset voltage -5 5 mV 

V hys Input hysteresis 0 0.7 1.5 mV 

V REF 

Reference Voltage CPPS[1:0]=11b 1.2 V 

Temperature Drift CPPS[1:0]=11b 50 ppm/℃ 

I R 

Multi-node resistor current 

CPRLS[0]=0b 10 

CPRLS[0]=1b 30 

uA 

8. Revision History 

. 

Major differences are stated thereinafter: 

Version Page Summary of Changes Date 

V01 ALL First edition 2013/05/20 

V05 ALL (1)Added HY16F184/187 Pin out 

2013/09/16 

(2)In Ordering Information added 

HY16F184/187 description. 

(3)In Package Information added 

LQFP48 and QFN33 description. 

V06 ALL (1)name change: VDD3 to VDD3V. VDD to VDD18. 2013/12/20 




page51

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