Version 04

HY16F188
21-Bit ENOB Σ∆ADC
32-Bit MCU and 64 KB Flash
7.6 ADC Management System
All specifications at TA = –40°C to +85°C, VDDA=REFP=+3V, REFN=VSSA, and Gain=128,
Unless otherwise noted.
Sym. Parameter Test Conditions Min. Typ. Max. Unit
Analog Inputs
Full-Scale Input Voltage
(AINP – AINN)
±0.5*VREF/Gain
V
Common-Mode
Input Range
Gain=1 VSS-0.2 VDDA+0.2 V
System Performance
Resolution No Missing Codes 24 Bits
Internal Oscillator,
SPEED = High
80 SPS
Data Rate
Internal Oscillator,
SPEED = Low
10 SPS
External Oscillator,
SPEED = High
f CLK /61440
SPS
External Oscillator,
SPEED = Low
f CLK /491520
SPS
Digital Filter Settling Time Full Settling 3 Data
Differential Input,
15 PPM
End-Point Fit, G = 64
Integral Nonlinearity (INL)
Differential Input,
15 PPM
End-Point Fit, G = 128
Gain Drift Reference Buffer . off 5 ppm/°C
Normal-Mode Rejection
fI N = 50/ Internal
60Hz ±1Hz, OSC
-70 dB
f DATA = External
10SPS OSC
-80 dB
Common-Mode Rejection at DC, detla VDDA = 0.1V 80 dB
Input-Referred Noise
fDATA = 10SPS 50 nV, rms
fDATA = 80SPS 140 nV, rms
Power-Supply Rejection at DC, delta VDDA = 0.1V 80 dB
Voltage Reference Input
Voltage Reference Input
(VREF)
VREF = REFP – REFN -0.15V VDDA+0.15V V
Reference Buffer Range 0.9V VDDA-0.2 V
Reference Buffer Current 30 uA
Reference Noise 1~100Hz 0.5 1 V/√Hz
© 2013 HYCON Technology Corp
www.hycontek.com
DS-HY16F188-V06_EN
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