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HY16F188 21-Bit ENOB Σ∆ADC 32-Bit MCU and 64 KB Flash 4.2 Building Block Diagram To AICE 2-wire JATG EDM 32-bit N801 Core 8K Byte Boost ROM 64K Byte Flash ROM Instruction Fetch Load/Store Unit 8K Byte SRAM Bus Interface Unit . APB Digital IP Analog IP Sensor IP Communication IP Figure 4-2 Build Block Diagram 4.3 Supporting Document NO File Name Description 1 DS-HY16F188 HY16F188 Data Sheet 2 UG-HY16F188 HY16F188 Users’ Manual 3 APD-HY16IDE001 HY16F188 IDE Software Manual 4 APD-HY16IDE002 HY16F188 IDE Hardware Manual © 2013 HYCON Technology Corp www.hycontek.com DS-HY16F188-V06_EN page24
HY16F188 21-Bit ENOB Σ∆ADC 32-Bit MCU and 64 KB Flash 4.4 Clock System Network HSXT Enable(ENOHS) 2~20MHz EN_HAO HAO[1:0] HAOTR[7:0] 32.768KHz CKS HSXT 2 ~20MHz HSRC 2/4/10/20M Hz LSXT Enable(ENOLS) LSXT 32.768KHz LSRC 34KHz HSXT HSRC LSXT LSRC CKHS 1 0 CKLS 1 0 HS_CK MCUCKS 0 1 LS_CK ENMCD Pre-scale 1,2 ENACD MCCK APCK ADCD[1:0] CPU APB LSXT LSRC 0 1 CKS ENRTCK HS_CK Pre-scale 6,12,30,60 ADCK ADC APCK 0 1 ENSD RTCDV 128 RTCK SPCD[2:0] RTC . LSRC Pre-scale 256 WDCK WDT APCK Pre-scale 1,2,4, ~2<strong>04</strong>8 SPCK 32-bit SPI TACKS ENTAD HSXT HSRC TUCKS 0 1 ENUD Pre-scale 1,2,4, ~128 UACD[3:0] URCK UART HS_CK LS_CK 0 1 Pre-scale 32 TACK Timer A APCK ENI2C Pre-scale 1,2,4, ~128 TOPS[2:0] I2CK I2C HS_CK LS_CK TMCKS 0 1 ENTD TMCD[1:0] Pre-scale 1,2,4,8 TBCK Timer B Timer C ENAD IOCKS IOCD[3:0] ADCK ADCKo 0 1 CHPCK Pre-scale 4 (internal used only) Charge Pump HS_CK LS_CK 0 1 Pre-scale 1,2,4, ~16384 IOCK PTIO © 2013 HYCON Technology Corp www.hycontek.com DS-HY16F188-V06_EN page25
Page 1 and 2: HY16F188 Datasheet . High Precision
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